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@@ -1,251 +1,260 @@
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+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
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+ * ARM Ltd. Fast Models
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*
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- * SPDX-License-Identifier: BSD-3-Clause
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+ * Copyright (c) 2012-2022 ARM Ltd.
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+ *
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+ * Versatile Express (VE) system model
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+ * Motherboard component
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+ *
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+ * VEMotherBoard.lisa
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*/
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+/ {
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+ v2m_clk24mhz: clk24mhz {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <24000000>;
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+ clock-output-names = "v2m:clk24mhz";
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+ };
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- motherboard {
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- arm,v2m-memory-map = "rs1";
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- compatible = "arm,vexpress,v2m-p1", "simple-bus";
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- #address-cells = <2>; /* SMB chipselect number and offset */
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- #size-cells = <1>;
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- ranges;
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+ v2m_refclk1mhz: refclk1mhz {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <1000000>;
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+ clock-output-names = "v2m:refclk1mhz";
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+ };
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- flash@0,00000000 {
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- compatible = "arm,vexpress-flash", "cfi-flash";
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- reg = <0 0x00000000 0x04000000>,
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- <4 0x00000000 0x04000000>;
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- bank-width = <4>;
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- };
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+ v2m_refclk32khz: refclk32khz {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <32768>;
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+ clock-output-names = "v2m:refclk32khz";
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+ };
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- vram@2,00000000 {
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- compatible = "arm,vexpress-vram";
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- reg = <2 0x00000000 0x00800000>;
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- };
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+ v2m_fixed_3v3: v2m-3v3 {
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+ compatible = "regulator-fixed";
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+ regulator-name = "3V3";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-always-on;
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+ };
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- ethernet@2,02000000 {
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- compatible = "smsc,lan91c111";
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- reg = <2 0x02000000 0x10000>;
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- interrupts = <15>;
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- };
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+ mcc {
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+ compatible = "arm,vexpress,config-bus";
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+ arm,vexpress,config-bridge = <&v2m_sysreg>;
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- v2m_clk24mhz: clk24mhz {
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- compatible = "fixed-clock";
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+ v2m_oscclk1: oscclk1 {
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+ /* CLCD clock */
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+ compatible = "arm,vexpress-osc";
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+ arm,vexpress-sysreg,func = <1 1>;
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+ freq-range = <23750000 63500000>;
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#clock-cells = <0>;
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- clock-frequency = <24000000>;
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- clock-output-names = "v2m:clk24mhz";
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+ clock-output-names = "v2m:oscclk1";
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};
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- v2m_refclk1mhz: refclk1mhz {
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- compatible = "fixed-clock";
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- #clock-cells = <0>;
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- clock-frequency = <1000000>;
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- clock-output-names = "v2m:refclk1mhz";
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+ reset {
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+ compatible = "arm,vexpress-reset";
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+ arm,vexpress-sysreg,func = <5 0>;
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};
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- v2m_refclk32khz: refclk32khz {
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- compatible = "fixed-clock";
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- #clock-cells = <0>;
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- clock-frequency = <32768>;
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- clock-output-names = "v2m:refclk32khz";
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+ muxfpga {
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+ compatible = "arm,vexpress-muxfpga";
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+ arm,vexpress-sysreg,func = <7 0>;
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};
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- iofpga@3,00000000 {
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- compatible = "arm,amba-bus", "simple-bus";
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- #address-cells = <1>;
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- #size-cells = <1>;
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- ranges = <0 3 0 0x200000>;
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-
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- v2m_sysreg: sysreg@10000 {
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- compatible = "arm,vexpress-sysreg";
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- reg = <0x010000 0x1000>;
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- gpio-controller;
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- #gpio-cells = <2>;
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- };
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-
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- v2m_sysctl: sysctl@20000 {
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- compatible = "arm,sp810", "arm,primecell";
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- reg = <0x020000 0x1000>;
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- clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
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- clock-names = "refclk", "timclk", "apb_pclk";
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- #clock-cells = <1>;
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- clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
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- };
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-
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- aaci@40000 {
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- compatible = "arm,pl041", "arm,primecell";
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- reg = <0x040000 0x1000>;
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- interrupts = <11>;
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- clocks = <&v2m_clk24mhz>;
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- clock-names = "apb_pclk";
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- };
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-
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- mmci@50000 {
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- compatible = "arm,pl180", "arm,primecell";
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- reg = <0x050000 0x1000>;
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- interrupts = <9>, <10>;
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- cd-gpios = <&v2m_sysreg 0 0>;
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- wp-gpios = <&v2m_sysreg 1 0>;
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- max-frequency = <12000000>;
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- vmmc-supply = <&v2m_fixed_3v3>;
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- clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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- clock-names = "mclk", "apb_pclk";
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- };
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-
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- kmi@60000 {
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- compatible = "arm,pl050", "arm,primecell";
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- reg = <0x060000 0x1000>;
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- interrupts = <12>;
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- clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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- clock-names = "KMIREFCLK", "apb_pclk";
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- };
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-
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- kmi@70000 {
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- compatible = "arm,pl050", "arm,primecell";
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- reg = <0x070000 0x1000>;
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- interrupts = <13>;
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- clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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- clock-names = "KMIREFCLK", "apb_pclk";
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- };
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-
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- v2m_serial0: uart@90000 {
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- compatible = "arm,pl011", "arm,primecell";
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- reg = <0x090000 0x1000>;
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- interrupts = <5>;
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- clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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- clock-names = "uartclk", "apb_pclk";
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- };
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-
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- v2m_serial1: uart@a0000 {
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- compatible = "arm,pl011", "arm,primecell";
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- reg = <0x0a0000 0x1000>;
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- interrupts = <6>;
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- clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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- clock-names = "uartclk", "apb_pclk";
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- };
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-
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- v2m_serial2: uart@b0000 {
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- compatible = "arm,pl011", "arm,primecell";
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- reg = <0x0b0000 0x1000>;
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- interrupts = <7>;
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- clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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- clock-names = "uartclk", "apb_pclk";
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- };
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-
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- v2m_serial3: uart@c0000 {
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- compatible = "arm,pl011", "arm,primecell";
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- reg = <0x0c0000 0x1000>;
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- interrupts = <8>;
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- clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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- clock-names = "uartclk", "apb_pclk";
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- };
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-
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- wdt@f0000 {
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- compatible = "arm,sp805", "arm,primecell";
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- reg = <0x0f0000 0x1000>;
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- interrupts = <0>;
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- clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
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- clock-names = "wdogclk", "apb_pclk";
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- };
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-
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- v2m_timer01: timer@110000 {
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- compatible = "arm,sp804", "arm,primecell";
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- reg = <0x110000 0x1000>;
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- interrupts = <2>;
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- clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
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- clock-names = "timclken1", "timclken2", "apb_pclk";
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- };
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-
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- v2m_timer23: timer@120000 {
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- compatible = "arm,sp804", "arm,primecell";
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- reg = <0x120000 0x1000>;
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- interrupts = <3>;
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- clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
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- clock-names = "timclken1", "timclken2", "apb_pclk";
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- };
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-
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- rtc@170000 {
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- compatible = "arm,pl031", "arm,primecell";
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- reg = <0x170000 0x1000>;
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- interrupts = <4>;
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- clocks = <&v2m_clk24mhz>;
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- clock-names = "apb_pclk";
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- };
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-
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- clcd@1f0000 {
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- compatible = "arm,pl111", "arm,primecell";
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- reg = <0x1f0000 0x1000>;
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- interrupts = <14>;
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- clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
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- clock-names = "clcdclk", "apb_pclk";
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- mode = "XVGA";
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- use_dma = <0>;
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- framebuffer = <0x18000000 0x00180000>;
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- };
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+ shutdown {
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+ compatible = "arm,vexpress-shutdown";
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+ arm,vexpress-sysreg,func = <8 0>;
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+ };
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- virtio_block@130000 {
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- compatible = "virtio,mmio";
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- reg = <0x130000 0x1000>;
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- interrupts = <0x2a>;
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- };
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+ reboot {
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+ compatible = "arm,vexpress-reboot";
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+ arm,vexpress-sysreg,func = <9 0>;
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};
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- v2m_fixed_3v3: fixedregulator {
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- compatible = "regulator-fixed";
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- regulator-name = "3V3";
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- regulator-min-microvolt = <3300000>;
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- regulator-max-microvolt = <3300000>;
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- regulator-always-on;
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+ dvimode {
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+ compatible = "arm,vexpress-dvimode";
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+ arm,vexpress-sysreg,func = <11 0>;
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};
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+ };
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- mcc {
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- compatible = "arm,vexpress,config-bus", "simple-bus";
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- arm,vexpress,config-bridge = <&v2m_sysreg>;
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-
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- v2m_oscclk1: osc {
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- /* CLCD clock */
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- compatible = "arm,vexpress-osc";
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- arm,vexpress-sysreg,func = <1 1>;
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- freq-range = <23750000 63500000>;
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- #clock-cells = <0>;
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- clock-output-names = "v2m:oscclk1";
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+ bus@8000000 {
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+ compatible = "simple-bus";
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+ #address-cells = <2>;
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+ #size-cells = <1>;
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+ ranges = <0 0x8000000 0 0x8000000 0x18000000>;
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+
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+ motherboard-bus@8000000 {
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+ compatible = "arm,vexpress,v2m-p1", "simple-bus";
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+ #address-cells = <2>; /* SMB chipselect number and offset */
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+ #size-cells = <1>;
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+ ranges = <0 0 0 0x08000000 0x04000000>,
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+ <1 0 0 0x14000000 0x04000000>,
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+ <2 0 0 0x18000000 0x04000000>,
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+ <3 0 0 0x1c000000 0x04000000>,
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+ <4 0 0 0x0c000000 0x04000000>,
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+ <5 0 0 0x10000000 0x04000000>;
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+
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+ flash@0 {
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+ compatible = "arm,vexpress-flash", "cfi-flash";
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+ reg = <0 0x00000000 0x04000000>,
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+ <4 0x00000000 0x04000000>;
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+ bank-width = <4>;
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};
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- /*
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- * Not supported in FVP models
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- *
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- * reset@0 {
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- * compatible = "arm,vexpress-reset";
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- * arm,vexpress-sysreg,func = <5 0>;
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- * };
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- */
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-
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- muxfpga {
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- compatible = "arm,vexpress-muxfpga";
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- arm,vexpress-sysreg,func = <7 0>;
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+ ethernet@202000000 {
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+ compatible = "smsc,lan91c111";
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+ reg = <2 0x02000000 0x10000>;
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+ interrupts = <15>;
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};
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- /*
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- * Not used - Superseded by PSCI sys_poweroff
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- *
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- * shutdown@0 {
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- * compatible = "arm,vexpress-shutdown";
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- * arm,vexpress-sysreg,func = <8 0>;
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- * };
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- */
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-
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- /*
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- * Not used - Superseded by PSCI sys_reset
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- *
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- * reboot@0 {
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- * compatible = "arm,vexpress-reboot";
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- * arm,vexpress-sysreg,func = <9 0>;
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- * };
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- */
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-
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- dvimode {
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- compatible = "arm,vexpress-dvimode";
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- arm,vexpress-sysreg,func = <11 0>;
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+ iofpga-bus@300000000 {
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+ compatible = "simple-bus";
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ ranges = <0 3 0 0x210000>;
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+
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+ v2m_sysreg: sysreg@10000 {
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+ compatible = "arm,vexpress-sysreg";
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+ reg = <0x010000 0x1000>;
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+ gpio-controller;
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+ #gpio-cells = <2>;
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+ };
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+
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+ v2m_sysctl: sysctl@20000 {
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+ compatible = "arm,sp810", "arm,primecell";
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+ reg = <0x020000 0x1000>;
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+ clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
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+ clock-names = "refclk", "timclk", "apb_pclk";
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+ #clock-cells = <1>;
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+ clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
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+ assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
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+ assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
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+ };
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+
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+ aaci@40000 {
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+ compatible = "arm,pl041", "arm,primecell";
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+ reg = <0x040000 0x1000>;
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+ interrupts = <11>;
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+ clocks = <&v2m_clk24mhz>;
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+ clock-names = "apb_pclk";
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+ };
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+
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+ mmc@50000 {
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+ compatible = "arm,pl180", "arm,primecell";
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+ reg = <0x050000 0x1000>;
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+ interrupts = <9>, <10>;
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+ cd-gpios = <&v2m_sysreg 0 0>;
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+ wp-gpios = <&v2m_sysreg 1 0>;
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+ max-frequency = <12000000>;
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+ vmmc-supply = <&v2m_fixed_3v3>;
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+ clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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+ clock-names = "mclk", "apb_pclk";
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+ };
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+
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+ kmi@60000 {
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+ compatible = "arm,pl050", "arm,primecell";
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+ reg = <0x060000 0x1000>;
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+ interrupts = <12>;
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+ clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
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+ clock-names = "KMIREFCLK", "apb_pclk";
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+ };
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|
+
|
|
|
+ kmi@70000 {
|
|
|
+ compatible = "arm,pl050", "arm,primecell";
|
|
|
+ reg = <0x070000 0x1000>;
|
|
|
+ interrupts = <13>;
|
|
|
+ clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
|
|
|
+ clock-names = "KMIREFCLK", "apb_pclk";
|
|
|
+ };
|
|
|
+
|
|
|
+ v2m_serial0: serial@90000 {
|
|
|
+ compatible = "arm,pl011", "arm,primecell";
|
|
|
+ reg = <0x090000 0x1000>;
|
|
|
+ interrupts = <5>;
|
|
|
+ clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
|
|
|
+ clock-names = "uartclk", "apb_pclk";
|
|
|
+ };
|
|
|
+
|
|
|
+ v2m_serial1: serial@a0000 {
|
|
|
+ compatible = "arm,pl011", "arm,primecell";
|
|
|
+ reg = <0x0a0000 0x1000>;
|
|
|
+ interrupts = <6>;
|
|
|
+ clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
|
|
|
+ clock-names = "uartclk", "apb_pclk";
|
|
|
+ };
|
|
|
+
|
|
|
+ v2m_serial2: serial@b0000 {
|
|
|
+ compatible = "arm,pl011", "arm,primecell";
|
|
|
+ reg = <0x0b0000 0x1000>;
|
|
|
+ interrupts = <7>;
|
|
|
+ clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
|
|
|
+ clock-names = "uartclk", "apb_pclk";
|
|
|
+ };
|
|
|
+
|
|
|
+ v2m_serial3: serial@c0000 {
|
|
|
+ compatible = "arm,pl011", "arm,primecell";
|
|
|
+ reg = <0x0c0000 0x1000>;
|
|
|
+ interrupts = <8>;
|
|
|
+ clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
|
|
|
+ clock-names = "uartclk", "apb_pclk";
|
|
|
+ };
|
|
|
+
|
|
|
+ watchdog@f0000 {
|
|
|
+ compatible = "arm,sp805", "arm,primecell";
|
|
|
+ reg = <0x0f0000 0x1000>;
|
|
|
+ interrupts = <0>;
|
|
|
+ clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
|
|
|
+ clock-names = "wdog_clk", "apb_pclk";
|
|
|
+ };
|
|
|
+
|
|
|
+ v2m_timer01: timer@110000 {
|
|
|
+ compatible = "arm,sp804", "arm,primecell";
|
|
|
+ reg = <0x110000 0x1000>;
|
|
|
+ interrupts = <2>;
|
|
|
+ clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
|
|
|
+ clock-names = "timclken1", "timclken2", "apb_pclk";
|
|
|
+ };
|
|
|
+
|
|
|
+ v2m_timer23: timer@120000 {
|
|
|
+ compatible = "arm,sp804", "arm,primecell";
|
|
|
+ reg = <0x120000 0x1000>;
|
|
|
+ interrupts = <3>;
|
|
|
+ clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
|
|
|
+ clock-names = "timclken1", "timclken2", "apb_pclk";
|
|
|
+ };
|
|
|
+
|
|
|
+ virtio@130000 {
|
|
|
+ compatible = "virtio,mmio";
|
|
|
+ reg = <0x130000 0x200>;
|
|
|
+ interrupts = <42>;
|
|
|
+ };
|
|
|
+
|
|
|
+ rtc@170000 {
|
|
|
+ compatible = "arm,pl031", "arm,primecell";
|
|
|
+ reg = <0x170000 0x1000>;
|
|
|
+ interrupts = <4>;
|
|
|
+ clocks = <&v2m_clk24mhz>;
|
|
|
+ clock-names = "apb_pclk";
|
|
|
+ };
|
|
|
+
|
|
|
+ clcd@1f0000 {
|
|
|
+ compatible = "arm,pl111", "arm,primecell";
|
|
|
+ reg = <0x1f0000 0x1000>;
|
|
|
+ interrupt-names = "combined";
|
|
|
+ interrupts = <14>;
|
|
|
+ clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
|
|
|
+ clock-names = "clcdclk", "apb_pclk";
|
|
|
+ memory-region = <&vram>;
|
|
|
+
|
|
|
+ port {
|
|
|
+ clcd_pads: endpoint {
|
|
|
+ remote-endpoint = <&panel_in>;
|
|
|
+ arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
};
|
|
|
};
|
|
|
};
|
|
|
+};
|