Kalyani Chidambaram Vaidyanathan cb6c8efc4f fix(tegra210): mark bits [23:17] as zero for Fast SMCs пре 1 година
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drivers 35aa1c1e51 Tegra210: SE: switch SE clock source to CLK_M пре 4 година
plat_psci_handlers.c 96d07af402 feat(tegra): implement 'pwr_domain_off_early' handler пре 1 година
plat_secondary.c 09d40e0e08 Sanitise includes across codebase пре 6 година
plat_setup.c 3ff448f9a7 Tegra: add platform specific 'runtime_setup' handler пре 4 година
plat_sip_calls.c cb6c8efc4f fix(tegra210): mark bits [23:17] as zero for Fast SMCs пре 1 година
platform_t210.mk 7581dc8958 Tegra: platform specific GIC sources пре 4 година