gic-x00.c 6.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232
  1. /*
  2. * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
  3. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  4. *
  5. * SPDX-License-Identifier: BSD-3-Clause
  6. */
  7. /*
  8. * Driver for GIC-500 and GIC-600 specific features. This driver only
  9. * overrides APIs that are different to those generic ones in GICv3
  10. * driver.
  11. *
  12. * GIC-600 supports independently power-gating redistributor interface.
  13. */
  14. #include <assert.h>
  15. #include <arch_helpers.h>
  16. #include <common/debug.h>
  17. #include <drivers/arm/arm_gicv3_common.h>
  18. #include <drivers/arm/gicv3.h>
  19. #include "gicv3_private.h"
  20. /* GIC-600 specific register offsets */
  21. #define GICR_PWRR 0x24U
  22. /* GICR_PWRR fields */
  23. #define PWRR_RDPD_SHIFT 0
  24. #define PWRR_RDAG_SHIFT 1
  25. #define PWRR_RDGPD_SHIFT 2
  26. #define PWRR_RDGPO_SHIFT 3
  27. #define PWRR_RDPD (1U << PWRR_RDPD_SHIFT)
  28. #define PWRR_RDAG (1U << PWRR_RDAG_SHIFT)
  29. #define PWRR_RDGPD (1U << PWRR_RDGPD_SHIFT)
  30. #define PWRR_RDGPO (1U << PWRR_RDGPO_SHIFT)
  31. /*
  32. * Values to write to GICR_PWRR register to power redistributor
  33. * for operating through the core (GICR_PWRR.RDAG = 0)
  34. */
  35. #define PWRR_ON (0U << PWRR_RDPD_SHIFT)
  36. #define PWRR_OFF (1U << PWRR_RDPD_SHIFT)
  37. static bool gic600_errata_wa_2384374 __unused;
  38. #if GICV3_SUPPORT_GIC600
  39. /* GIC-600/700 specific accessor functions */
  40. static void gicr_write_pwrr(uintptr_t base, unsigned int val)
  41. {
  42. mmio_write_32(base + GICR_PWRR, val);
  43. }
  44. static uint32_t gicr_read_pwrr(uintptr_t base)
  45. {
  46. return mmio_read_32(base + GICR_PWRR);
  47. }
  48. static void gicr_wait_group_not_in_transit(uintptr_t base)
  49. {
  50. uint32_t pwrr;
  51. do {
  52. pwrr = gicr_read_pwrr(base);
  53. /* Check group not transitioning: RDGPD == RDGPO */
  54. } while (((pwrr & PWRR_RDGPD) >> PWRR_RDGPD_SHIFT) !=
  55. ((pwrr & PWRR_RDGPO) >> PWRR_RDGPO_SHIFT));
  56. }
  57. static void gic600_pwr_on(uintptr_t base)
  58. {
  59. do { /* Wait until group not transitioning */
  60. gicr_wait_group_not_in_transit(base);
  61. /* Power on redistributor */
  62. gicr_write_pwrr(base, PWRR_ON);
  63. /*
  64. * Wait until the power on state is reflected.
  65. * If RDPD == 0 then powered on.
  66. */
  67. } while ((gicr_read_pwrr(base) & PWRR_RDPD) != PWRR_ON);
  68. }
  69. static void gic600_pwr_off(uintptr_t base)
  70. {
  71. /* Wait until group not transitioning */
  72. gicr_wait_group_not_in_transit(base);
  73. /* Power off redistributor */
  74. gicr_write_pwrr(base, PWRR_OFF);
  75. /*
  76. * If this is the last man, turning this redistributor frame off will
  77. * result in the group itself being powered off and RDGPD = 1.
  78. * In that case, wait as long as it's in transition, or has aborted
  79. * the transition altogether for any reason.
  80. */
  81. if ((gicr_read_pwrr(base) & PWRR_RDGPD) != 0U) {
  82. /* Wait until group not transitioning */
  83. gicr_wait_group_not_in_transit(base);
  84. }
  85. }
  86. static uintptr_t get_gicr_base(unsigned int proc_num)
  87. {
  88. uintptr_t gicr_base;
  89. assert(gicv3_driver_data != NULL);
  90. assert(proc_num < gicv3_driver_data->rdistif_num);
  91. assert(gicv3_driver_data->rdistif_base_addrs != NULL);
  92. gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
  93. assert(gicr_base != 0UL);
  94. return gicr_base;
  95. }
  96. static bool gicv3_redists_need_power_mgmt(uintptr_t gicr_base)
  97. {
  98. uint32_t reg = mmio_read_32(gicr_base + GICR_IIDR);
  99. /*
  100. * The Arm GIC-600 and GIC-700 models have their redistributors
  101. * powered down at reset.
  102. */
  103. return (((reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_600) ||
  104. ((reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_600AE) ||
  105. ((reg & IIDR_MODEL_MASK) == IIDR_MODEL_ARM_GIC_700));
  106. }
  107. #endif /* GICV3_SUPPORT_GIC600 */
  108. void gicv3_distif_pre_save(unsigned int proc_num)
  109. {
  110. arm_gicv3_distif_pre_save(proc_num);
  111. }
  112. void gicv3_distif_post_restore(unsigned int proc_num)
  113. {
  114. arm_gicv3_distif_post_restore(proc_num);
  115. }
  116. /*
  117. * Power off GIC-600 redistributor (if configured and detected)
  118. */
  119. void gicv3_rdistif_off(unsigned int proc_num)
  120. {
  121. #if GICV3_SUPPORT_GIC600
  122. uintptr_t gicr_base = get_gicr_base(proc_num);
  123. /* Attempt to power redistributor off */
  124. if (gicv3_redists_need_power_mgmt(gicr_base)) {
  125. gic600_pwr_off(gicr_base);
  126. }
  127. #endif
  128. }
  129. /*
  130. * Power on GIC-600 redistributor (if configured and detected)
  131. */
  132. void gicv3_rdistif_on(unsigned int proc_num)
  133. {
  134. #if GICV3_SUPPORT_GIC600
  135. uintptr_t gicr_base = get_gicr_base(proc_num);
  136. /* Power redistributor on */
  137. if (gicv3_redists_need_power_mgmt(gicr_base)) {
  138. gic600_pwr_on(gicr_base);
  139. }
  140. #endif
  141. }
  142. #if GIC600_ERRATA_WA_2384374
  143. /*******************************************************************************
  144. * Apply part 2 of workaround for errata-2384374 as per SDEN:
  145. * https://developer.arm.com/documentation/sden892601/latest/
  146. ******************************************************************************/
  147. void gicv3_apply_errata_wa_2384374(uintptr_t gicr_base)
  148. {
  149. if (gic600_errata_wa_2384374) {
  150. uint32_t gicr_ctlr_val = gicr_read_ctlr(gicr_base);
  151. gicr_write_ctlr(gicr_base, gicr_ctlr_val |
  152. (GICR_CTLR_DPG0_BIT | GICR_CTLR_DPG1NS_BIT |
  153. GICR_CTLR_DPG1S_BIT));
  154. gicr_write_ctlr(gicr_base, gicr_ctlr_val &
  155. ~(GICR_CTLR_DPG0_BIT | GICR_CTLR_DPG1NS_BIT |
  156. GICR_CTLR_DPG1S_BIT));
  157. }
  158. }
  159. #endif /* GIC600_ERRATA_WA_2384374 */
  160. void gicv3_check_erratas_applies(uintptr_t gicd_base)
  161. {
  162. unsigned int gic_prod_id;
  163. uint8_t gic_rev;
  164. assert(gicd_base != 0UL);
  165. gicv3_get_component_prodid_rev(gicd_base, &gic_prod_id, &gic_rev);
  166. /*
  167. * This workaround applicable only to GIC600 and GIC600AE products with
  168. * revision less than r1p6 and r0p2 respectively.
  169. * As per GIC600/GIC600AE specification -
  170. * r1p6 = 0x17 => GICD_IIDR[19:12]
  171. * r0p2 = 0x04 => GICD_IIDR[19:12]
  172. */
  173. if ((gic_prod_id == GIC_PRODUCT_ID_GIC600) ||
  174. (gic_prod_id == GIC_PRODUCT_ID_GIC600AE)) {
  175. if (((gic_prod_id == GIC_PRODUCT_ID_GIC600) &&
  176. (gic_rev <= GIC_REV(GIC_VARIANT_R1, GIC_REV_P6))) ||
  177. ((gic_prod_id == GIC_PRODUCT_ID_GIC600AE) &&
  178. (gic_rev <= GIC_REV(GIC_VARIANT_R0, GIC_REV_P2)))) {
  179. #if GIC600_ERRATA_WA_2384374
  180. gic600_errata_wa_2384374 = true;
  181. VERBOSE("%s applies\n",
  182. "GIC600/GIC600AE errata workaround 2384374");
  183. #else
  184. WARN("%s missing\n",
  185. "GIC600/GIC600AE errata workaround 2384374");
  186. #endif /* GIC600_ERRATA_WA_2384374 */
  187. } else {
  188. VERBOSE("%s not applies\n",
  189. "GIC600/GIC600AE errata workaround 2384374");
  190. }
  191. }
  192. }