plat.ld.S 767 B

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  1. /*
  2. * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
  3. *
  4. * SPDX-License-Identifier: BSD-3-Clause
  5. */
  6. #ifndef __ROCKCHIP_PLAT_LD_S__
  7. #define __ROCKCHIP_PLAT_LD_S__
  8. MEMORY {
  9. PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE
  10. }
  11. SECTIONS
  12. {
  13. . = PMUSRAM_BASE;
  14. /*
  15. * pmu_cpuson_entrypoint request address
  16. * align 64K when resume, so put it in the
  17. * start of pmusram
  18. */
  19. .pmusram : {
  20. ASSERT(. == ALIGN(64 * 1024),
  21. ".pmusram.entry request 64K aligned.");
  22. KEEP(*(.pmusram.entry))
  23. __bl31_pmusram_text_start = .;
  24. *(.pmusram.text)
  25. *(.pmusram.rodata)
  26. __bl31_pmusram_text_end = .;
  27. __bl31_pmusram_data_start = .;
  28. *(.pmusram.data)
  29. __bl31_pmusram_data_end = .;
  30. } >PMUSRAM
  31. }
  32. #endif /* __ROCKCHIP_PLAT_LD_S__ */