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Use a different hint for incomplete trap frame on ARM.

Qemu was allowing the reserved bit 20 of the CPSR to actually be set,
causing failures on things like fork since the trap frame looked
incomplete but wasn't. Restoring the bit was starting to look like more
work than just setting another value. So I moved the hint to be
TRAP_FRAME.ExceptionCpsr == -1. This should never happen accidentally
because bits 20-23 at least are reserved in the CPSR and should be zero.
Evan Green 7 anni fa
parent
commit
d17d20b569
3 ha cambiato i file con 5 aggiunte e 15 eliminazioni
  1. 1 8
      include/minoca/kernel/arm.h
  2. 0 2
      include/minoca/kernel/arm.inc
  3. 4 5
      kernel/armv7/trap.S

+ 1 - 8
include/minoca/kernel/arm.h

@@ -142,7 +142,7 @@ Author:
 //
 
 #define IS_TRAP_FRAME_COMPLETE(_TrapFrame) \
-    (((_TrapFrame)->Cpsr & PSR_FLAG_RESERVED20) == 0)
+    ((_TrapFrame)->ExceptionCpsr != 0xFFFFFFFF)
 
 //
 // This macro manipulates the bitfields in the coprocessor access mask.
@@ -191,13 +191,6 @@ Author:
 #define PSR_FLAG_IRQ        0x00000080
 #define PSR_FLAG_FIQ        0x00000040
 
-//
-// This bit is always zero architecturally, but is set in the system call
-// handler's trap frames when the trap frame is incomplete.
-//
-
-#define PSR_FLAG_RESERVED20 0x00100000
-
 //
 // Interrupt vector ranges.
 //

+ 0 - 2
include/minoca/kernel/arm.inc

@@ -54,8 +54,6 @@ Environment:
 #define PSR_FLAG_IRQ        0x00000080
 #define PSR_FLAG_FIQ        0x00000040
 
-#define PSR_FLAG_RESERVED20 0x00100000
-
 ##
 ## Processor modes
 ##

+ 4 - 5
kernel/armv7/trap.S

@@ -212,13 +212,12 @@ FUNCTION ArpSoftwareInterruptEntry
     cpsie   i, #ARM_MODE_SVC                    @ Enable interrupts, svc mode.
 
     ##
-    ## Set a reserved bit in the CPSR as a hint that this trap frame is
-    ## incomplete.
+    ## Set the exception CPSR to something wild as a hint that this trap frame
+    ## is incomplete.
     ##
 
-    ldr     %r3, [%sp, #TRAP_CPSR]              @ Get CPSR.
-    orr     %r3, #PSR_FLAG_RESERVED20           @ Set reserved flag.
-    str     %r3, [%sp, #TRAP_CPSR]              @ Store CPSR.
+    mov     %r3, #0xFFFFFFFF                    @ Create -1.
+    str     %r3, [%sp, #TRAP_EXCEPTION_CPSR]    @ Save into exception CPSR.
 
     ##
     ## The system call routine takes three parameters: the system call number,