Minoca-os/drivers/net/wireless/rtlw81xx/rtlw81.h

/*++

Copyright (c) 2015 Minoca Corp. All Rights Reserved

Module Name:

    rtlw81.h

Abstract:

    This header contains definitions for the wireless RLT81xx family of USB
    WIFI Controllers.

Author:

    Chris Stevens 7-Oct-2015

--*/

//
// ------------------------------------------------------------------- Includes
//

//
// ---------------------------------------------------------------- Definitions
//

#define RTLW81_ALLOCATION_TAG 0x31387752 // '18wR'

//
// Define the set of RTLW81xx flags.
//

#define RTLW81_FLAG_8188E          0x00000001
#define RTLW81_FLAG_8192C          0x00000002
#define RTLW81_FLAG_8192C_1T2R     0x00000004
#define RTLW81_FLAG_UMC            0x00000008
#define RTLW81_FLAG_UMC_A_CUT      0x00000010
#define RTLW81_FLAG_CCK_HIGH_POWER 0x00000020

//
// Define the firmware files to use for different devices.
//

#define RTLW81_8188E_FIRMWARE_PATH "rtlw8188eufw.bin"
#define RTLW81_8188C_UMC_FIRMWARE_PATH "rtlw8188cufwUMC.bin"
#define RTLW81_DEFAULT_FIRMWARE_PATH "rtlw8192cufw.bin"

//
// Define the maximum size of the control transfer data.
//

#define RTLW81_MAX_CONTROL_TRANSFER_SIZE (sizeof(USB_SETUP_PACKET) + 256)

//
// Define the size of each bulk in transfer.
//

#define RTLW81_BULK_IN_TRANSFER_SIZE (16 * _1KB)

//
// Define the maximum size of single packet, including any headers and footers.
//

#define RTLW81_MAX_PACKET_SIZE 2312

//
// Define the number of bytes needed at the front of every transmit packet.
//

#define RTLW81_TRANSMIT_HEADER_SIZE sizeof(RTLW81_TRANSMIT_HEADER)

//
// Define maximum number of bulk out endpoints.
//

#define RTLW81_MAX_BULK_OUT_ENDPOINT_COUNT 3

//
// Define the number of bulk in transfers.
//

#define RTLW81_BULK_IN_TRANSFER_COUNT 1

//
// Define the bulk in packet alignment.
//

#define RTLW81_BULK_IN_PACKET_ALIGNMENT 0x80

//
// Define the number of times a read from an EFUSE register will be retried
// before the present value is returned.
//

#define RTLW81_EFUSE_RETRY_COUNT 100

//
// Define the default timeout to wait for register state to change.
//

#define RTLW81_DEVICE_TIMEOUT 1

//
// Define the maximum number of chains on an RTL81xx wireless device.
//

#define RTLW81_MAX_CHAIN_COUNT 2

//
// Define the maximum supported channel.
//

#define RTLW81_MAX_CHANNEL 11

//
// Define the default number of transmit and receive chains.
//

#define RTLW81_DEFAULT_TRANSMIT_CHAIN_COUNT 1
#define RTLW81_DEFAULT_RECEIVE_CHAIN_COUNT 1
#define RTLW81_8192C_TRANSMIT_CHAIN_COUNT 2
#define RTLW81_8192C_RECEIVE_CHAIN_COUNT 2
#define RTLW81_8192C_1T2R_TRANSMIT_CHAIN_COUNT 1

//
// Define the number of channel groups.
//

#define RTLW81_DEFAULT_GROUP_COUNT 3
#define RTLW81_8188E_GROUP_COUNT 6

//
// Define the total number of power states needed to program and channel.
//

#define RTLW81_POWER_STATE_COUNT 28

//
// Define the maximum value for a transmit power state.
//

#define RTLW81_MAX_TRANSMIT_POWER 0x3F

//
// Define the ROM sizes for the device versions.
//

#define RTLW81_DEFAULT_ROM_SIZE 128
#define RTLW81_8188E_ROM_SIZE 512

//
// Define offsets within the default ROM.
//

#define RTLW81_DEFAULT_ROM_MAC_ADDRESS_OFFSET 0x16
#define RTLW81_DEFAULT_ROM_CCK_TRANSMIT_POWER_OFFSET 0x5A
#define RTLW81_DEFAULT_ROM_HT_40_TRANSMIT_POWER_OFFSET 0x60
#define RTLW81_DEFAULT_ROM_HT_40_TRANSMIT_POWER_DIFF_OFFSET 0x66
#define RTLW81_DEFAULT_ROM_HT_20_TRANSMIT_POWER_DIFF_OFFSET 0x69
#define RTLW81_DEFAULT_ROM_OFDM_TRANSMIT_POWER_DIFF_OFFSET 0x6C
#define RTLW81_DEFAULT_ROM_HT_40_MAX_POWER_OFFSET 0x6F
#define RTLW81_DEFAULT_ROM_HT_20_MAX_POWER_OFFSET 0x72
#define RTLW81_DEFAULT_ROM_RF_OPT1_OFFSET 0x79

//
// Define the offsets within the RTL8188E ROM.
//

#define RTLW81_8188E_ROM_CCK_TRANSMIT_POWER_OFFSET 0x10
#define RTLW81_8188E_ROM_HT_40_TRANSMIT_POWER_OFFSET 0x16
#define RTLW81_8188E_ROM_POWER_OPTION_OFFSET 0x1B
#define RTLW81_8188E_ROM_CRYSTAL_CAPABILITY_OFFSET 0xB9
#define RTLW81_8188E_ROM_RF_OPT1_OFFSET 0xC1
#define RTLW81_8188E_ROM_MAC_ADDRESS_OFFSET 0xD7

//
// Define values for the RTLW8188E crystal capability byte.
//

#define RTLW81_8188E_ROM_CRYSTAL_CAPABILITY_INVALID 0xFF
#define RTLW81_8188E_ROM_CRYSTAL_CAPABILITY_DEFAULT 0x20
#define RTLW81_8188E_ROM_CRYSTAL_CAPABILITY_MASK 0x3F

//
// Define the bits for the RTLW8188E power option byte.
//

#define RTLW81_8188E_ROM_POWER_OPTION_BW_20_MASK    0xF0
#define RTLW81_8188E_ROM_POWER_OPTION_BW_20_SHIFT   4
#define RTLW81_8188E_ROM_POWER_OPTION_OFDM_MASK     0x0F
#define RTLW81_8188E_ROM_POWER_OPTION_OFDM_SHIFT    0
#define RTLW81_8188E_ROM_POWER_OPTION_HIGH_BITS_SET 0x08
#define RTLW81_8188E_ROM_POWER_OPTION_HIGH_BITS     0xF0

//
// Define the flags for the ROM's RF OPT1 byte.
//

#define RTLW81_ROM_RF_OPT1_REGULATORY_MASK     0x07
#define RTLW81_ROM_RF_OPT1_REGULATORY_SHIFT    0
#define RTLW81_ROM_RF_OPT1_BOARD_TYPE_MASK     0xE0
#define RTLW81_ROM_RF_OPT1_BOARD_TYPE_SHIFT    5
#define RTLW81_ROM_RF_OPT1_BOARD_TYPE_DONGLE   0
#define RTLW81_ROM_RF_OPT1_BOARD_TYPE_HIGHPA   1
#define RTLW81_ROM_RF_OPT1_BOARD_TYPE_MINICARD 2
#define RTLW81_ROM_RF_OPT1_BOARD_TYPE_SOLO     3
#define RTLW81_ROM_RF_OPT1_BOARD_TYPE_COMBO    4

//
// Define the device firmware signature values.
//

#define RTLW81_88E_FIRMWARE_SIGNATURE 0x88E
#define RTLW81_88C_FIRMWARE_SIGNATURE 0x88C
#define RTLW81_92C_FIRMWARE_SIGNATURE 0x92C

//
// Define values related to writing the device firmware to the device.
//

#define RTLW81_FIRMWARE_PAGE_SIZE 4096
#define RTLW81_MAX_FIRMWARE_WRITE_SIZE 196

//
// Define the USB control transfer request value used to read and write
// registers.
//

#define RTLW81_VENDOR_REQUEST_REGISTER 0x05

//
// Define the various queue page counts for the different devices.
//

#define RTLW81_DEFAULT_PUBLIC_QUEUE_PAGE_COUNT 231
#define RTLW81_DEFAULT_TRANSMIT_PAGE_COUNT 248
#define RTLW81_DEFAULT_TRANSMIT_PAGE_BOUNDARY \
    (RTLW81_DEFAULT_TRANSMIT_PAGE_COUNT + 1)

#define RTLW81_DEFAULT_TRANSMIT_PACKET_COUNT 256
#define RTLW81_DEFAULT_RECEIVE_BOUNDARY2 0x27FF

#define RTLW81_8188E_PUBLIC_QUEUE_PAGE_COUNT 142
#define RTLW81_8188E_TRANSMIT_PAGE_COUNT 169
#define RTLW81_8188E_TRANSMIT_PAGE_BOUNDARY \
    (RTLW81_8188E_TRANSMIT_PAGE_COUNT + 1)

#define RTLW81_8188E_TRANSMIT_PACKET_COUNT 177
#define RTLW81_8188E_HIGH_QUEUE_PAGE_COUNT 13
#define RTLW81_8188E_NORMAL_QUEUE_PAGE_COUNT 13
#define RTLW81_8188E_LOW_QUEUE_PAGE_COUNT 0
#define RTLW81_8188E_RECEIVE_BOUNDARY2 0x23FF

//
// Define the bits for the system ISO control register.
//

#define RTLW81_SYS_ISO_CONTROL_PWC_EV12V 0x8000
#define RTLW81_SYS_ISO_CONTROL_PWC_EV25V 0x4000
#define RTLW81_SYS_ISO_CONTROL_DIOR      0x0200
#define RTLW81_SYS_ISO_CONTROL_EB2CORE   0x0100
#define RTLW81_SYS_ISO_CONTROL_DIOE      0x0080
#define RTLW81_SYS_ISO_CONTROL_DIOP      0x0040
#define RTLW81_SYS_ISO_CONTROL_IP2MAC    0x0020
#define RTLW81_SYS_ISO_CONTROL_PD2CORE   0x0010
#define RTLW81_SYS_ISO_CONTROL_PA2PCIE   0x0008
#define RTLW81_SYS_ISO_CONTROL_UD2CORE   0x0004
#define RTLW81_SYS_ISO_CONTROL_UA2USB    0x0002
#define RTLW81_SYS_ISO_CONTROL_MD2PP     0x0001

//
// Define the bits for the system function enable register.
//

#define RTLW81_SYS_FUNCTION_ENABLE_MREGEN     0x8000
#define RTLW81_SYS_FUNCTION_ENABLE_HWPDN      0x4000
#define RTLW81_SYS_FUNCTION_ENABLE_DIO_RF     0x2000
#define RTLW81_SYS_FUNCTION_ENABLE_ELDR       0x1000
#define RTLW81_SYS_FUNCTION_ENABLE_DCORE      0x0800
#define RTLW81_SYS_FUNCTION_ENABLE_CPUEN      0x0400
#define RTLW81_SYS_FUNCTION_ENABLE_DIOE       0x0200
#define RTLW81_SYS_FUNCTION_ENABLE_PCIED      0x0100
#define RTLW81_SYS_FUNCTION_ENABLE_PPLL       0x0080
#define RTLW81_SYS_FUNCTION_ENABLE_PCIEA      0x0040
#define RTLW81_SYS_FUNCTION_ENABLE_DIO_PCIE   0x0020
#define RTLW81_SYS_FUNCTION_ENABLE_USBD       0x0010
#define RTLW81_SYS_FUNCTION_ENABLE_UPLL       0x0008
#define RTLW81_SYS_FUNCTION_ENABLE_USBA       0x0004
#define RTLW81_SYS_FUNCTION_ENABLE_BB_GLB_RST 0x0002
#define RTLW81_SYS_FUNCTION_ENABLE_BBRSTB     0x0001

//
// Define the bits for the APS FSMCO register.
//

#define RTLW81_APS_FSMCO_XOP_BTCK          0x80000000
#define RTLW81_APS_FSMCO_SOP_A8M           0x40000000
#define RTLW81_APS_FSMCO_SOP_RCK           0x20000000
#define RTLW81_APS_FSMCO_SOP_AMB           0x10000000
#define RTLW81_APS_FSMCO_SOP_ABG           0x08000000
#define RTLW81_APS_FSMCO_SOP_FUSE          0x04000000
#define RTLW81_APS_FSMCO_SOP_MRST          0x02000000
#define RTLW81_APS_FSMCO_ROP_SPS           0x00400000
#define RTLW81_APS_FSMCO_ROP_PWD           0x00200000
#define RTLW81_APS_FSMCO_ROP_ALD           0x00100000
#define RTLW81_APS_FSMCO_SUS_HOST          0x00020000
#define RTLW81_APS_FSMCO_READ_MAC_ON       0x00010000
#define RTLW81_APS_FSMCO_APDM_HPDN         0x00008000
#define RTLW81_APS_FSMCO_APDM_HOST         0x00004000
#define RTLW81_APS_FSMCO_APDM_MAC          0x00002000
#define RTLW81_APS_FSMCO_AFSM_PCIE         0x00001000
#define RTLW81_APS_FSMCO_AFSM_HSUS         0x00000800
#define RTLW81_APS_FSMCO_APFM_RSM          0x00000400
#define RTLW81_APS_FSMCO_APFM_OFF          0x00000200
#define RTLW81_APS_FSMCO_APFM_ONMAC        0x00000100
#define RTLW81_APS_FSMCO_PDN_PL            0x00000020
#define RTLW81_APS_FSMCO_PDN_EN            0x00000010
#define RTLW81_APC_FSMCO_PFM_WOWL          0x00000008
#define RTLW81_APC_FSMCO_PFM_LDKP          0x00000004
#define RTLW81_APS_FSMCO_PFM_AUTOLOAD_DONE 0x00000002
#define RTLW81_APS_FSMCO_PFM_LOAD_ALL      0x00000001

//
// Define the bits for the system clock register.
//

#define RTLW81_SYS_CLOCK_RING_ENABLE    0x00002000
#define RTLW81_SYS_CLOCK_SYS_ENABLE     0x00001000
#define RTLW81_SYS_CLOCK_MAC_ENABLE     0x00000800
#define RTLW81_SYS_CLOCK_SEC_ENABLE     0x00000400
#define RTLW81_SYS_CLOCK_PHY_SSC_RSTB   0x00000200
#define RTLW81_SYS_CLOCK_80M_SSC_EN_HO  0x00000100
#define RTLW81_SYS_CLOCK_80M_SSC_DIS    0x00000080
#define RTLW81_SYS_CLOCK_LOADER_ENABLE  0x00000020
#define RTLW81_SYS_CLOCK_MACSLP         0x00000010
#define RTLW81_SYS_CLOCK_ANA8M          0x00000002
#define RTLW81_SYS_CLOCK_ANAD16V_ENABLE 0x00000001

//
// Define the default value to program the SPS0 control register.
//

#define RTLW81_SPS0_CONTROL_DEFAULT 0x2b

//
// Define the default value to program the temperature control register.
//

#define RTLW81_TEMPERATURE_CONTROL_DEFAULT 0xE9

//
// Define the bits for the PA setting register.
//

#define RTLW81_PA_SETTING_INIT_BIT   0x10
#define RTLW81_PA_SETTING_INIT_MASK  0xF0
#define RTLW81_PA_SETTING_INIT_VALUE 0x90

//
// Define the bits for the RF control register.
//

#define RTLW81_RF_CONTROL_SDMRSTB 0x04
#define RTLW81_RF_CONTROL_RSTB    0x02
#define RTLW81_RF_CONTROL_ENABLE  0x01

//
// Define the bits for the LDOV12D control register.
//

#define RTLW81_LDOV12D_CONTROL_LDV12_ENABLE 0x01

//
// Define the default value to program the LDOHCI12 control register.
//

#define RTLW81_LDOHCI_12_CONTROL_DEFAULT 0x0F

//
// Define the default value to program the LPLDO register.
//

#define RTLW81_LPLDO_CONTROL_DISABLE 0x10

//
// Define the bits for the AFE XTAL control register.
//

#define RTLW81_AFE_XTAL_CONTROL_ENABLE         0x00800000
#define RTLW81_AFE_XTAL_CONTROL_ADDRESS2_MASK  0x007E0000
#define RTLW81_AFE_XTAL_CONTROL_ADDRESS2_SHIFT 17
#define RTLW81_AFE_XTAL_CONTROL_ADDRESS1_MASK  0x0001F800
#define RTLW81_AFE_XTAL_CONTROL_ADDRESS1_SHIFT 11

#define RTLW81_AFE_XTAL_CONTROL1_DEFAULT 0x80
#define RTLW81_AFE_XTAL_CONTROL2_ENABLE 0x80

//
// Define the default value to program the AFE PLL control register.
//

#define RTLW81_AFE_PLL_CONTROL_DEFAULT 0xDB83

//
// Define the bits for the EFUSE control register.
//

#define RTLW81_EFUSE_CONTROL_VALID         0x80000000
#define RTLW81_EFUSE_CONTROL_ADDRESS_MASK  0x0003FF00
#define RTLW81_EFUSE_CONTROL_ADDRESS_SHIFT 8
#define RTLW81_EFUSE_CONTROL_DATA_MASK     0x000000FF
#define RTLW81_EFUSE_CONTROL_DATA_SHIFT    0

//
// Define the bits for the GPIO MUX configuration register.
//

#define RTLW81_GPIO_MUX_CONFIG_ENABLE_BT 0x0020

//
// Define the bits for the LED register.
//

#define RTLW81_LED_SAVE_MASK 0x70
#define RTLW81_LED_DISABLE   0x08

//
// Define the bits for the MCU firmware download register.
//

#define RTLW81_MCU_FIRMWARE_DOWNLOAD_CPRST           0x00800000
#define RTLW81_MCU_FIRMWARE_DOWNLOAD_CLEAR           0x00080000
#define RTLW81_MCU_FIRMWARE_DOWNLOAD_PAGE_MASK       0x00070000
#define RTLW81_MCU_FIRMWARE_DOWNLOAD_PAGE_SHIFT      16
#define RTLW81_MCU_FIRMWARE_DOWNLOAD_RAM_DL_SELECT   0x00000080
#define RTLW81_MCU_FIRMWARE_DOWNLOAD_WINTINI_READY   0x00000040
#define RTLW81_MCU_FIRMWARE_DOWNLOAD_RFINI_READY     0x00000020
#define RTLW81_MCU_FIRMWARE_DOWNLOAD_BBINI_READY     0x00000010
#define RTLW81_MCU_FIRMWARE_DOWNLOAD_MACINI_READY    0x00000008
#define RTLW81_MCU_FIRMWARE_DOWNLOAD_CHECKSUM_REPORT 0x00000004
#define RTLW81_MCU_FIRMWARE_DOWNLOAD_READY           0x00000002
#define RTLW81_MCU_FIRMWARE_DOWNLOAD_ENABLE          0x00000001

//
// Define the bits for RTL8188EU interrupt mask register.
//

#define RTLW81_8188E_INTERRUPT_MASK_PS_TIMEOUT 0x20000000
#define RTLW81_8188E_INTERRUPT_MASK_TBDER      0x04000000
#define RTLW81_8188E_INTERRUPT_MASK_CPWM2      0x00000200
#define RTLW81_8188E_INTERRUPT_MASK_CPWM       0x00000100

//
// Define the bits for RTL8188EU extra interrupt mask register.
//

#define RTLW81_8188E_INTERRUPT_EXTRA_MASK_TRANSMIT_ERROR 0x00000800
#define RTLW81_8188E_INTERRUPT_EXTRA_MASK_RECEIVE_ERROR  0x00000400
#define RTLW81_8188E_INTERRUPT_EXTRA_MASK_TRANSMIT_FOVM  0x00000200
#define RTLW81_8188E_INTERRUPT_EXTRA_MASK_RECEIVE_FOVM   0x00000100

//
// Define the bits for the EFUSE access register.
//

#define RTLW81_EFUSE_ACCESS_OFF 0x00
#define RTLW81_EFUSE_ACCESS_ON  0x69

//
// Define the bits for the HPON FSM chip bonding register.
//

#define RTLW81_HPON_FSM_CHIP_BONDING_ID_MASK       0x00C00000
#define RTLW81_HPON_FSM_CHIP_BONDING_ID_SHIFT      22
#define RTLW81_HPON_FSM_CHIP_BONDING_ID_8192C_1T2R 1

//
// Define the bits for the system configuration register.
//

#define RTLW81_SYS_CONFIGURATION_TYPE_8192C      0x08000000
#define RTLW81_SYS_CONFIGURATION_BD_HCI_SEL      0x04000000
#define RTLW81_SYS_CONFIGURATION_BD_PKG_SEL      0x02000000
#define RTLW81_SYS_CONFIGURATION_TRP_BT_ENABLE   0x01000000
#define RTLW81_SYS_CONFIGURATION_TRP_VAUX_ENABLE 0x00800000
#define RTLW81_SYS_CONFIGURATION_PAD_HWPD_IDN    0x00400000
#define RTLW81_SYS_CONFIGURATION_VENDOR_UMC      0x00080000
#define RTLW81_SYS_CONFIGURATION_BT_FUNC         0x00010000
#define RTLW81_SYS_CONFIGURATION_VERSION_MASK    0x0000F000
#define RTLW81_SYS_CONFIGURATION_VERSION_SHIFT   12
#define RTLW81_SYS_CONFIGURATION_IC_MACPHY_MODE  0x00000800
#define RTLW81_SYS_CONFIGURATION_BD_MAC1         0x00000400
#define RTLW81_SYS_CONFIGURATION_BD_MAC2         0x00000200
#define RTLW81_SYS_CONFIGURATION_SIC_IDLE        0x00000100
#define RTLW81_SYS_CONFIGURATION_TRP_B15V_ENABLE 0x00000080
#define RTLW81_SYS_CONFIGURATION_V15_VALID  0x00000020
#define RTLW81_SYS_CONFIGURATION_PCIRSTB    0x00000010
#define RTLW81_SYS_CONFIGURATION_PCLK_VALID 0x00000008
#define RTLW81_SYS_CONFIGURATION_UCLK_VALID 0x00000004
#define RTLW81_SYS_CONFIGURATION_ACLK_VALID 0x00000002
#define RTLW81_SYS_CONFIGURATION_XCLK_VALID 0x00000001

//
// Define the bits for the configuration register.
//

#define RTLW81_CONFIGURATION_NETWORK_TYPE_MASK       0x00030000
#define RTLW81_CONFIGURATION_NETWORK_TYPE_SHIFT      16
#define RTLW81_CONFIGURATION_NETWORK_TYPE_NO_LINK    0
#define RTLW81_CONFIGURATION_NETWORK_TYPE_AD_HOC     1
#define RTLW81_CONFIGURATION_NETWORK_TYPE_INFRA      2
#define RTLW81_CONFIGURATION_NETWORK_TYPE_AP         3
#define RTLW81_CONFIGURATION_CALTMR_ENABLE           0x00000400
#define RTLW81_CONFIGURATION_SEC_ENABLE              0x00000200
#define RTLW81_CONFIGURATION_MAC_RECEIVE_ENABLE      0x00000080
#define RTLW81_CONFIGURATION_MAC_TRANSMIT_ENABLE     0x00000040
#define RTLW81_CONFIGURATION_SCHEDULE_ENABLE         0x00000020
#define RTLW81_CONFIGURATION_PROTOCOL_ENABLE         0x00000010
#define RTLW81_CONFIGURATION_RECEIVE_DMA_ENABLE      0x00000008
#define RTLW81_CONFIGURATION_TRANSMIT_DMA_ENABLE     0x00000004
#define RTLW81_CONFIGURATION_HCI_RECEIVE_DMA_ENABLE  0x00000002
#define RTLW81_CONFIGURATION_HCI_TRANSMIT_DMA_ENABLE 0x00000001

//
// Define the bits for the page configuration register.
//

#define RTLW81_PAGE_CONFIGURATION_TRANSMIT_PAGE_SIZE_MASK  0xF0
#define RTLW81_PAGE_CONFIGURATION_TRANSMIT_PAGE_SIZE_SHIFT 4
#define RTLW81_PAGE_CONFIGURATION_RECEIVE_PAGE_SIZE_MASK   0x0F
#define RTLW81_PAGE_CONFIGURATION_RECEIVE_PAGE_SIZE_SHIFT  0
#define RTLW81_PAGE_CONFIGURATION_PAGE_SIZE_64 0
#define RTLW81_PAGE_CONFIGURATION_PAGE_SIZE_128 1
#define RTLW81_PAGE_CONFIGURATION_PAGE_SIZE_256 2
#define RTLW81_PAGE_CONFIGURATION_PAGE_SIZE_512 3
#define RTLW81_PAGE_CONFIGURATION_PAGE_SIZE_1024 4

//
// Define the bits for the transmit/receive DMA register.
//

#define RTLW81_TRANSMIT_RECEIVE_DMA_QMAP_MASK            0xFFF0
#define RTLW81_TRANSMIT_RECEIVE_DMA_QMAP_HIGH_NORMAL_LOW 0xF5B0
#define RTLW81_TRANSMIT_RECEIVE_DMA_QMAP_HIGH_LOW        0xF5F0
#define RTLW81_TRANSMIT_RECEIVE_DMA_QMAP_HIGH_NORMAL     0xFAF0
#define RTLW81_TRANSMIT_RECEIVE_DMA_QMAP_LOW             0x5550
#define RTLW81_TRANSMIT_RECEIVE_DMA_QMAP_NORMAL          0xAAA0
#define RTLW81_TRANSMIT_RECEIVE_DMA_QMAP_HIGH            0xFFF0
#define RTLW81_TRANSMIT_RECEIVE_DMA_AGG_ENABLE           0x0004

//
// Define the bits for the LLT initialization register.
//

#define RTLW81_LLT_INIT_OP_MASK       0xC0000000
#define RTLW81_LLT_INIT_OP_SHIFT      30
#define RTLW81_LLT_INIT_OP_WRITE      1
#define RTLW81_LLT_INIT_OP_NO_ACTIVE  0
#define RTLW81_LLT_INIT_ADDRESS_MASK  0x0000FF00
#define RTLW81_LLT_INIT_ADDRESS_SHIFT 8
#define RTLW81_LLT_INIT_DATA_MASK     0x000000FF
#define RTLW81_LLT_INIT_DATA_SHIFT    0

//
// Define the bits for the HMENTFR3 register.
//

#define RTLW81_HMENTFR3_RESET 0x20

//
// Define the bits for the queue page count register.
//

#define RTLW81_QUEUE_PAGE_COUNT_LOAD         0x80000000
#define RTLW81_QUEUE_PAGE_COUNT_PUBLIC_MASK  0x00FF0000
#define RTLW81_QUEUE_PAGE_COUNT_PUBLIC_SHIFT 16
#define RTLW81_QUEUE_PAGE_COUNT_LOW_MASK     0x0000FF00
#define RTLW81_QUEUE_PAGE_COUNT_LOW_SHIFT    8
#define RTLW81_QUEUE_PAGE_COUNT_HIGH_MASK    0x000000FF
#define RTLW81_QUEUE_PAGE_COUNT_HIGH_SHIFT   0

//
// Define the bits for the transmit descriptor control register.
//

#define RTLW81_TRANSMIT_DESCRIPTOR_CONTROL_BLOCK_COUNT_MASK 0x000000F0
#define RTLW81_TRANSMIT_DESCRIPTOR_CONTROL_BLOCK_COUNT_SHIFT 4
#define RTLW81_TRANSMIT_DESCRIPTOR_CONTROL_BLOCK_COUNT_DEFAULT 6

//
// Define the default values for the receive DMA AGG PG TH registers.
//

#define RTLW81_RECEIVE_DMA_AGG_PG_TH0_DEFAULT 48
#define RTLW81_RECEIVE_DMA_AGG_PG_TH1_DEFAULT 4

//
// Define the bits for the firmware/hardware transmit queue control register.
//

#define RTLW81_FIRMWARE_HARDWARE_TRANSMIT_QUEUE_CONTROL_AMPDU_RETRY_NEW 0x80

//
// Define the default value to program the hardware sequencing control register.
//

#define RTW81_HARDWARE_SEQUENCING_CONTROL_DEFAULT 0xFF

//
// Define the bits for the SPEC SIFS register.
//

#define RTLW81_SPEC_SIFS_OFDM_MASK  0xFF00
#define RTLW81_SPEC_SIFS_OFDM_SHIFT 8
#define RTLW81_SPEC_SIFS_CCK_MASK   0x00FF
#define RTLW81_SPEC_SIFS_CCK_SHIFT  0

#define RTLW81_SPEC_SIFS_DEFAULT 0x100A
#define RTLW81_SPEC_SIFS_ASSOCIATED 0x0A0A

//
// Define the bits for the retry limit register.
//

#define RTLW81_RETRY_LIMIT_SHORT_MASK  0x3F00
#define RTLW81_RETRY_LIMIT_SHORT_SHIFT 8
#define RTLW81_RETRY_LIMIT_LONG_MASK   0x003F
#define RTLW81_RETRY_LIMIT_LONG_SHIFT  0

#define RTLW81_RETRY_LIMIT_DEFAULT 0x3030

//
// Define the default values for the DARFRC and RARFRC registers.
//

#define RTLW81_DARFRC0_DEFAULT 0x00000000
#define RTLW81_DARFRC1_DEFAULT 0x10080404
#define RTLW81_RARFRC0_DEFAULT 0x04030201
#define RTLW81_RARFRC1_DEFAULT 0x08070605

//
// Define the bits for the receive response rate register.
//

#define RTLW81_RECEIVE_RESPONSE_RATE_SHORT             0x00800000
#define RTLW81_RECEIVE_RESPONSE_RATE_RSC_UPPER_CHANNEL 0x00400000
#define RTLW81_RECEIVE_RESPONSE_RATE_RSC_LOWER_CHANNEL 0x00200000
#define RTLW81_RECEIVE_RESPONSE_RATE_BITMAP_MASK       0x000FFFFF
#define RTLW81_RECEIVE_RESPONSE_RATE_BITMAP_SHIFT      0
#define RTLW81_RECEIVE_RESPONSE_RATE_CCK_ONLY_1M       0xFFFF1

//
// Define the default value for the aggregate length limit register.
//

#define RTLW81_AGGREGATE_LENGTH_LIMIT_DEFAULT 0x99997631

//
// Define the RTS rate select values for various modes.
//

#define RTLW81_INI_RTS_RATE_SELECT_11B 0
#define RTLW81_INI_RTS_RATE_SELECT_11BG 3

//
// Define the default values for the max aggregation number register.
//

#define RTLW81_MAX_AGGREGATION_NUMBER_DEFAULT 0x0708
#define RTLW81_MAX_AGGREGATION_NUMBER_8188E_DEFAULT 0x07

//
// Define the default value for the beacon TCFG register.
//

#define RTLW81_BEACON_TCFG_DEFAULT 0x660F

//
// Define the default value for the aggregate break time register.
//

#define RTLW81_AGGREGATE_BREAK_TIME_DEFAULT 0x16

//
// Define the bits for the RD control register.
//

#define RTLW81_RD_CONTROL_DISABLE_EDCA_COUNTDOWN 0x0800

//
// Define the default value for the TBTT prohibit register.
//

#define RTLW81_TBTT_PROHIBIT_DEFAULT 0x6404

//
// Define the default value for the beacon control register.
//

#define RTLW81_BEACON_CONTROL_DEFAULT 0x1010

//
// Define the bits for the beacon control register.
//

#define RTLW81_BEACON_CONTROL_DISABLE_TSF_UDT0    0x10
#define RTLW81_BEACON_CONTROL_ENABLE_BEACON       0x08
#define RTLW81_BEACON_CONTROL_TRANSMIT_BEACON_RPT 0x04
#define RTLW81_BEACON_CONTROL_ENABLE_MBSSID       0x02

//
// Define the default value for the driver early init register.
//

#define RTLW81_DRIVER_EARLY_INIT_DEFAULT 0x05

//
// Define the default value for the beacon DMA time register.
//

#define RTLW81_BEACON_DMA_TIME_DEFAULT 0x02

//
// Define the default value for the beacon max error register.
//

#define RTLW81_BEACON_MAX_ERROR_DEFAULT 0xFF

//
// Define the bits for the APSD control register.
//

#define RTLW81_APSD_CONTROL_OFF        0x40
#define RTLW81_APSD_CONTROL_STATUS_OFF 0x80

//
// Define the bits for the bandwidth register.
//

#define RTLW81_BANDWIDTH_MODE_20MHZ 0x04
#define RTLW81_BANDWIDTH_MODE_5G    0x02
#define RTLW81_BANDWIDTH_MODE_11J   0x01

//
// Define the bits for the receive configuration register.
//

#define RTLW81_RECEIVE_CONFIGURATION_APP_FCS      0x80000000
#define RTLW81_RECEIVE_CONFIGURATION_APP_MIC      0x40000000
#define RTLW81_RECEIVE_CONFIGURATION_APP_ICV      0x20000000
#define RTLW81_RECEIVE_CONFIGURATION_APP_PHYSTS   0x10000000
#define RTLW81_RECEIVE_CONFIGURATION_APP_BA_SSN   0x08000000
#define RTLW81_RECEIVE_CONFIGURATION_ENMBID       0x01000000
#define RTLW81_RECEIVE_CONFIGURATION_LSIGEN       0x00800000
#define RTLW81_RECEIVE_CONFIGURATION_MFBEN        0x00400000
#define RTLW81_RECEIVE_CONFIGURATION_HTC_LOC_CTRL 0x00004000
#define RTLW81_RECEIVE_CONFIGURATION_AMF          0x00002000
#define RTLW81_RECEIVE_CONFIGURATION_ACF          0x00001000
#define RTLW81_RECEIVE_CONFIGURATION_ADF          0x00000800
#define RTLW81_RECEIVE_CONFIGURATION_AICV         0x00000200
#define RTLW81_RECEIVE_CONFIGURATION_ACRC32       0x00000100
#define RTLW81_RECEIVE_CONFIGURATION_CBSSID_BCN   0x00000080
#define RTLW81_RECEIVE_CONFIGURATION_CBSSID_DATA  0x00000040
#define RTLW81_RECEIVE_CONFIGURATION_APWRMGT      0x00000020
#define RTLW81_RECEIVE_CONFIGURATION_ADD3         0x00000010
#define RTLW81_RECEIVE_CONFIGURATION_AB           0x00000008
#define RTLW81_RECEIVE_CONFIGURATION_AM           0x00000004
#define RTLW81_RECEIVE_CONFIGURATION_APM          0x00000002
#define RTLW81_RECEIVE_CONFIGURATION_AAP          0x00000001

//
// Define the default values for the EDCA parameter registers.
//

#define RTLW81_EDCA_VO_PARAM_DEFAULT 0x002FA226
#define RTLW81_EDCA_VI_PARAM_DEFAULT 0x005EA324
#define RTLW81_EDCA_BE_PARAM_DEFAULT 0x005EA42B
#define RTLW81_EDCA_BK_PARAM_DEFAULT 0x0000A44f

//
// Define the default and associated values for the SIFS CCK register.
//

#define RTLW81_SIFS_CCK_DEFAULT 0x100A
#define RTLW81_SIFS_CCK_ASSOCIATED 0x0A0A

//
// Define the default and associated values for the SIFS OFDM register.
//

#define RTLW81_SIFS_OFDM_DEFAULT 0x100A
#define RTLW81_SIFS_OFDM_ASSOCIATED 0x0A0A

//
// Define the bits for the MAC SPEC SIFS register.
//

#define RTLW81_MAC_SPEC_SIFS_OFDM_MASK  0xFF00
#define RTLW81_MAC_SPEC_SIFS_OFDM_SHIFT 8
#define RTLW81_MAC_SPEC_SIFS_CCK_MASK   0x00FF
#define RTLW81_MAC_SPEC_SIFS_CCK_SHIFT  0

#define RTLW81_MAC_SPEC_SIFS_DEFAULT 0x100A
#define RTLW81_MAC_SPEC_SIFS_ASSOCIATED 0x0A0A

//
// Define the associated values for the T2T and R2T SIFS.
//

#define RTLW81_T2T_SIFS_ASSOCIATED 0x0A0A
#define RTLW81_R2T_SIFS_ASSOCIATED 0x0A0A

//
// Define the default value for the driver information size register.
//

#define RTLW81_DRIVER_INFORMATION_SIZE_DEFAULT 4

//
// Define the default value for the ACK timeout register.
//

#define RTLW81_ACK_TIMEOUT_DEFAULT 0x40

//
// Define the bits for the CAM command register.
//

#define RTLW81_CAM_COMMAND_POLLING       0x80000000
#define RTLW81_CAM_COMMAND_CLEAR         0x40000000
#define RTLW81_CAM_COMMAND_WRITE         0x00010000
#define RTLW81_CAM_COMMAND_ADDRESS_MASK  0x0000FFFF
#define RTLW81_CAM_COMMAND_ADDRESS_SHIFT 0

//
// Define the bits for the RFMOD register.
//

#define RTLW81_RFMOD_OFDM_ENABLE 0x02000000
#define RTLW81_RFMOD_CCK_ENABLE  0x01000000
#define RTLW81_RFMOD_CCK_TXSC    0x00000030
#define RTLW81_RFMOD_JAPAN       0x00000002
#define RTLW81_RFMOD_40MHZ       0x00000001

//
// Define the default masks and values for the FPGA0 transmit info register.
//

#define RTLW81_FPGA0_TRANSMIT_INFO_INIT1_MASK  0x00000003
#define RTLW81_FPGA0_TRANSMIT_INFO_INIT1_VALUE 0x00000002
#define RTLW81_FPGA0_TRANSMIT_INFO_INIT2_MASK  0x00300033
#define RTLW81_FPGA0_TRANSMIT_INFO_INIT2_VALUE 0x00200022

//
// Define the bits for the HSSI parameter 1 register.
//

#define RTLW81_HSSI_PARAMETER1_PI 0x00000100

//
// Define the bits for the HSSI parameter 2 register.
//

#define RTLW81_HSSI_PARAMETER2_READ_EDGE          0x80000000
#define RTLW81_HSSI_PARAMETER2_READ_ADDRESS_MASK  0x7F800000
#define RTLW81_HSSI_PARAMETER2_READ_ADDRESS_SHIFT 23
#define RTLW81_HSSI_PARAMETER2_DATA_LENGTH        0x00000800
#define RTLW81_HSSI_PARAMETER2_ADDRESS_LENGTH     0x00000400
#define RTLW81_HSSI_PARAMETER2_CCK_HIGH_POWER     0x00000200

//
// Define the bits for the LSSI parameter register.
//

#define RTLW81_LSSI_PARAMETER_8188E_ADDRESS_MASK    0x0FF00000
#define RTLW81_LSSI_PARAMETER_8188E_ADDRESS_SHIFT   20
#define RTLW81_LSSI_PARAMETER_DEFAULT_ADDRESS_MASK  0x03F00000
#define RTLW81_LSSI_PARAMETER_DEFAULT_ADDRESS_SHIFT 20
#define RTLW81_LSSI_PARAMETER_DATA_MASK             0x000FFFFF
#define RTLW81_LSSI_PARAMETER_DATA_SHIFT            0

//
// Define the bits for the FPGA0 ANA parameter 2 register.
//

#define RTLW81_FPGA0_ANA_PARAM2_CBW20 0x00000400

//
// Define the bits for the LSSI readback register.
//

#define RTLW81_LSSI_READBACK_DATA_MASK  0x000FFFFF
#define RTLW81_LSSI_READBACK_DATA_SHIFT 0

//
// Define the bits for the FPGA0 RF OE interface register.
//

#define RTLW81_FPGA0_RF_OE_INTERFACE_ENABLE      0x00100000
#define RTLW81_FPGA0_RF_OE_INTERFACE_HIGH_OUTPUT 0x00000010

//
// Define the bits for the FPGA0 RF software interface register.
//

#define RTLW81_FPGA0_RF_SOFTWARE_INTERFACE_TYPE 0x10

//
// Define the initial mask and value for the CCK 0 AFE settings register.
//

#define RTLW81_CCK0_AFE_SETTING_INIT_MASK  0xFF000000
#define RTLW81_CCK0_AFE_SETTING_INIT_VALUE 0x45000000

//
// Define the initial mask and value for the OFDM 0 transmit path enable
// register.
//

#define RTLW81_OFDM0_TRANSMIT_PATH_ENABLE_INIT_MASK  0x000000FF
#define RTLW81_OFDM0_TRANSMIT_PATH_ENABLE_INIT_VALUE 0x00000023

//
// Define the two initialization values for the OFDM0 AGC core 1 register.
//

#define RTLW81_OFDM0_AGC_CORE1_INIT1 0x69553422
#define RTLW81_OFDM0_AGC_CORE1_INIT2 0x69553420

//
// Define the bits for the OFDM0 AGC core 1 register.
//

#define RTLW81_OFDM0_AGC_CORE1_GAIN_MASK  0x0000007F
#define RTLW81_OFDM0_AGC_CORE1_GAIN_SHIFT 0

#define RTLW81_OFDM0_AGC_CORE1_GAIN_PROBE_VALUE 0x20
#define RTLW81_OFDM0_AGC_CORE1_GAIN_AUTHENTICATE_VALUE 0x32

//
// Define the initial mask and value for the OFDM 0 AGC parameter 1 register.
//

#define RTLW81_OFDM0_AGC_PARAM1_INIT_MASK  0x00000030
#define RTLW81_OFDM0_AGC_PARAM1_INIT_VALUE 0x00000010

//
// Define the bits for the OFDM 1 LSTF 3 register.
//

#define RTLW81_OFDM1_LSTF3_TRANSMIT_ENABLED 0x70

//
// Define the bits for the transmit AGC rate 06-18 register.
//

#define RTLW81_TRANSMIT_AGC_RATE_18_MASK  0xFF000000
#define RTLW81_TRANSMIT_AGC_RATE_18_SHIFT 24
#define RTLW81_TRANSMIT_AGC_RATE_12_MASK  0x00FF0000
#define RTLW81_TRANSMIT_AGC_RATE_12_SHIFT 16
#define RTLW81_TRANSMIT_AGC_RATE_09_MASK  0x0000FF00
#define RTLW81_TRANSMIT_AGC_RATE_09_SHIFT 8
#define RTLW81_TRANSMIT_AGC_RATE_06_MASK  0x000000FF
#define RTLW81_TRANSMIT_AGC_RATE_06_SHIFT 0

//
// Define the bits for the transmit AGC rate 24-54 register.
//

#define RTLW81_TRANSMIT_AGC_RATE_54_MASK  0xFF000000
#define RTLW81_TRANSMIT_AGC_RATE_54_SHIFT 24
#define RTLW81_TRANSMIT_AGC_RATE_48_MASK  0x00FF0000
#define RTLW81_TRANSMIT_AGC_RATE_48_SHIFT 16
#define RTLW81_TRANSMIT_AGC_RATE_36_MASK  0x0000FF00
#define RTLW81_TRANSMIT_AGC_RATE_36_SHIFT 8
#define RTLW81_TRANSMIT_AGC_RATE_24_MASK  0x000000FF
#define RTLW81_TRANSMIT_AGC_RATE_24_SHIFT 0

//
// Define the bits for the transmit AGC MSC 00-03 register.
//

#define RTLW81_TRANSMIT_AGC_MCS03_MASK  0xFF000000
#define RTLW81_TRANSMIT_AGC_MCS03_SHIFT 24
#define RTLW81_TRANSMIT_AGC_MCS02_MASK  0x00FF0000
#define RTLW81_TRANSMIT_AGC_MCS02_SHIFT 16
#define RTLW81_TRANSMIT_AGC_MCS01_MASK  0x0000FF00
#define RTLW81_TRANSMIT_AGC_MCS01_SHIFT 8
#define RTLW81_TRANSMIT_AGC_MCS00_MASK  0x000000FF
#define RTLW81_TRANSMIT_AGC_MCS00_SHIFT 0

//
// Define the bits for the transmit AGC MSC 04-07 register.
//

#define RTLW81_TRANSMIT_AGC_MCS07_MASK  0xFF000000
#define RTLW81_TRANSMIT_AGC_MCS07_SHIFT 24
#define RTLW81_TRANSMIT_AGC_MCS06_MASK  0x00FF0000
#define RTLW81_TRANSMIT_AGC_MCS06_SHIFT 16
#define RTLW81_TRANSMIT_AGC_MCS05_MASK  0x0000FF00
#define RTLW81_TRANSMIT_AGC_MCS05_SHIFT 8
#define RTLW81_TRANSMIT_AGC_MCS04_MASK  0x000000FF
#define RTLW81_TRANSMIT_AGC_MCS04_SHIFT 0

//
// Define the bits for the transmit AGC MSC 08-11 register.
//

#define RTLW81_TRANSMIT_AGC_MCS11_MASK  0xFF000000
#define RTLW81_TRANSMIT_AGC_MCS11_SHIFT 24
#define RTLW81_TRANSMIT_AGC_MCS10_MASK  0x00FF0000
#define RTLW81_TRANSMIT_AGC_MCS10_SHIFT 16
#define RTLW81_TRANSMIT_AGC_MCS09_MASK  0x0000FF00
#define RTLW81_TRANSMIT_AGC_MCS09_SHIFT 8
#define RTLW81_TRANSMIT_AGC_MCS08_MASK  0x000000FF
#define RTLW81_TRANSMIT_AGC_MCS08_SHIFT 0

//
// Define the bits for the transmit AGC MSC 12-15 register.
//

#define RTLW81_TRANSMIT_AGC_MCS15_MASK  0xFF000000
#define RTLW81_TRANSMIT_AGC_MCS15_SHIFT 24
#define RTLW81_TRANSMIT_AGC_MCS14_MASK  0x00FF0000
#define RTLW81_TRANSMIT_AGC_MCS14_SHIFT 16
#define RTLW81_TRANSMIT_AGC_MCS13_MASK  0x0000FF00
#define RTLW81_TRANSMIT_AGC_MCS13_SHIFT 8
#define RTLW81_TRANSMIT_AGC_MCS12_MASK  0x000000FF
#define RTLW81_TRANSMIT_AGC_MCS12_SHIFT 0

//
// Define the bits for the transmit AGC CCK registers.
//

#define RLTW81_TRANSMIT_AGC_A_CCK1_MCS32_MASK  0x0000FF00
#define RLTW81_TRANSMIT_AGC_A_CCK1_MCS32_SHIFT 8

#define RTLW81_TRANSMIT_AGC_A_CCK11_MASK  0xFF000000
#define RTLW81_TRANSMIT_AGC_A_CCK11_SHIFT 24
#define RTLW81_TRANSMIT_AGC_A_CCK55_MASK  0x00FF0000
#define RTLW81_TRANSMIT_AGC_A_CCK55_SHIFT 16
#define RTLW81_TRANSMIT_AGC_A_CCK2_MASK   0x0000FF00
#define RTLW81_TRANSMIT_AGC_A_CCK2_SHIFT  8
#define RTLW81_TRANSMIT_AGC_B_CCK11_MASK  0x000000FF
#define RTLW81_TRANSMIT_AGC_B_CCK11_SHIFT 0

#define RTLW81_TRANSMIT_AGC_B_CCK55_MASK  0xFF000000
#define RTLW81_TRANSMIT_AGC_B_CCK55_SHIFT 24
#define RTLW81_TRANSMIT_AGC_B_CCK2_MASK   0x00FF0000
#define RTLW81_TRANSMIT_AGC_B_CCK2_SHIFT  16
#define RTLW81_TRANSMIT_AGC_B_CCK1_MASK   0x0000FF00
#define RTLW81_TRANSMIT_AGC_B_CCK1_SHIFT  8

//
// Define the bits for the 1 transmit 2 receive chain register.
//

#define RTLW81_8192C_1T2R_INIT_MASK  0x0C000000
#define RTLW81_8192C_1T2R_INIT_VALUE 0x08000000

//
// Define the default value for the USB enable register.
//

#define RTLW81_USB_ENABLE_DEFAULT 0x19

//
// Define the default values for the USB interference registers.
//

#define RTLW81_USB_INTERFERENCE0_DEFAULT 0xE0
#define RLTW81_USB_INTERFERENCE1_DEFAULT 0x8D
#define RTLW81_USB_INTERFERENCE2_DEFAULT 0x80

//
// Define the bits for the USB special option register.
//

#define RTLW81_USB_SPECIAL_OPTION_INT_BULK_SELECT 0x10
#define RTLW81_USB_SPECIAL_OPTION_AGG_ENABLE      0x08

//
// Define the default values for the USB AGG registers.
//

#define RTLW81_USB_DMA_AGG_TO_DEFAULT 4
#define RTLW81_USB_AGG_TO_DEFAULT 6
#define RTLW81_USB_AGG_TH_DEFAULT 8

//
// Define the bits for the USB endpoint register.
//

#define RTLW81_USB_ENDPOINT_LQ_MASK  0x0F00
#define RTLW81_USB_ENDPOINT_LQ_SHIFT 8
#define RTLW81_USB_ENDPOINT_NQ_MASK  0x00F0
#define RTLW81_USB_ENDPOINT_NQ_SHIFT 4
#define RTLW81_USB_ENDPOINT_HQ_MASK  0x000F
#define RTLW81_USB_ENDPOINT_HQ_SHIFT 0

//
// Define the bits for the RF AC register.
//

#define RTLW81_RF_AC_MODE_MASK    0x70000
#define RTLW81_RF_AC_MODE_SHIFT   16
#define RTLW81_RF_AC_MODE_STANDBY 1

//
// Define the initial values to write to the RF IPA register.
//

#define RTLW81_RF_IPA_INIT0 0x0F406
#define RTLW81_RF_IPA_INIT1 0x4F406
#define RTLW81_RF_IPA_INIT2 0x8F406
#define RTLW81_RF_IPA_INIT3 0xCF406

//
// Define the bits for the RF channel bandwidth register.
//

#define RTLW81_RF_CHANNEL_BANDWIDTH_LC_START      0x08000
#define RTLW81_RF_CHANNEL_BANDWIDTH_8188E_20MHZ   0x00C00
#define RTLW81_RF_CHANNEL_BANDWIDTH_DEFAULT_20MHZ 0x00400
#define RTLW81_RF_CHANNEL_BANDWIDTH_CHANNEL_MASK  0x003FF
#define RTLW81_RF_CHANNEL_BANDWIDTH_CHANNEL_SHIFT 0

//
// Define the default values for the RF receive registers.
//

#define RTLW81_RF_RECEIVE_G1_DEFAULT 0x30255
#define RTLW81_RF_RECEIVE_G2_DEFAULT 0x50A00

//
// Define the minimum and maximum RF register values that trigger a delay when
// programming the RF.
//

#define RTLW81_RF_REGISTER_DELAY_VALUE_MIN 0xF9
#define RTLW81_RF_REGISTER_DELAY_VALUE_MAX 0xFE

//
// Define the bits for the receive packet header length and error value.
//

#define RTLW81_RECEIVE_ICV_ERROR           0x8000
#define RTLW81_RECEIVE_CRC_ERROR           0x4000
#define RTLW81_RECEIVE_PACKET_LENGTH_MASK  0x3FFF
#define RTLW81_RECEIVE_PACKET_LENGTH_SHIFT 0

#define RTLW81_RECEIVE_ERROR_MASK \
    (RTLW81_RECEIVE_ICV_ERROR | RTLW81_RECEIVE_CRC_ERROR)

//
// Define the bits for the receive packet header status value.
//

#define RTLW81_RECEIVE_STATUS_DECRYPTED       0x0800
#define RTLW81_RECEIVE_STATUS_PHY_STATUS      0x0400
#define RTLW81_RECEIVE_STATUS_SHIFT_MASK      0x0300
#define RTLW81_RECEIVE_STATUS_SHIFT_SHIFT     8
#define RTLW81_RECEIVE_STATUS_QOS             0x0080
#define RTLW81_RECEIVE_STATUS_INFO_SIZE_MASK  0x000F
#define RTLW81_RECEIVE_STATUS_INFO_SIZE_SHIFT 0

//
// Define the bits for the receive packet header rate information.
//

#define RTLW81_RECEIVE_RATE_INFORMATION_RATE_MASK         0x0000003F
#define RTLW81_RECEIVE_RATE_INFORMATION_RATE_SHIFT        0
#define RTWL81_RECEIVE_RATE_INFORMATION_HIGH_THROUGHPUT   0x00000040
#define RTLW81_RECEIVE_RATE_INFORMATION_HIGH_THROUGHPUT_C 0x00000400

//
// Define the transmit packet header type flags.
//

#define RTLW81_TRANSMIT_TYPE_FLAG_MULTICAST_BROADCAST 0x01
#define RTLW81_TRANSMIT_TYPE_FLAG_LAST_SEGMENT        0x04
#define RTLW81_TRANSMIT_TYPE_FLAG_FIRST_SEGMENT       0x08
#define RTLW81_TRANSMIT_TYPE_FLAG_OWN                 0x80

//
// Define the transmit packet header identification bits.
//

#define RTLW81_TRANSMIT_IDENTIFICATION_PACKET_OFFSET_MASK  0x7C000000
#define RTLW81_TRANSMIT_IDENTIFICATION_PACKET_OFFSET_SHIFT 26
#define RTLW81_TRANSMIT_IDENTIFICATION_CIPHER_MASK         0x00C00000
#define RTLW81_TRANSMIT_IDENTIFICATION_CIPHER_SHIFT        22
#define RTLW81_TRANSMIT_IDENTIFICATION_CIPHER_NONE         0
#define RTLW81_TRANSMIT_IDENTIFICATION_CIPHER_RC4          1
#define RTLW81_TRANSMIT_IDENTIFICATION_CIPHER_AES          3
#define RTLW81_TRANSMIT_IDENTIFICATION_RAID_MASK           0x000F0000
#define RTLW81_TRANSMIT_IDENTIFICATION_RAID_SHIFT          16
#define RTLW81_TRANSMIT_IDENTIFICATION_RAID_11GN           1
#define RTLW81_TRANSMIT_IDENTIFICATION_RAID_11N            3
#define RTLW81_TRANSMIT_IDENTIFICATION_RAID_11BG           4
#define RTLW81_TRANSMIT_IDENTIFICATION_RAID_11G            5
#define RTLW81_TRANSMIT_IDENTIFICATION_RAID_11B            6
#define RTLW81_TRANSMIT_IDENTIFICATION_QSEL_MASK           0x00001F00
#define RTLW81_TRANSMIT_IDENTIFICATION_QSEL_SHIFT          8
#define RTLW81_TRANSMIT_IDENTIFICATION_QSEL_BE             0x00
#define RTLW81_TRANSMIT_IDENTIFICATION_QSEL_MGMT           0x12
#define RTLW81_TRANSMIT_IDENTIFICATION_AGG_BK              0x00000040
#define RTLW81_TRANSMIT_IDENTIFICATION_AGG_EN              0x00000020
#define RTLW81_TRANSMIT_IDENTIFICATION_MAC_ID_MASK         0x0000001F
#define RTLW81_TRANSMIT_IDENTIFICATION_MAC_ID_SHIFT        0
#define RTLW81_TRANSMIT_IDENTIFICATION_MAC_ID_BSS          0
#define RTLW81_TRANSMIT_IDENTIFICATION_MAC_ID_BROADCAST    4

//
// Define the one bit for the transmit packet header AGG BK value.
//

#define RTLW81_TRANSMIT_AGG_BK_FLAG 0x00010000
#define RTLW81_TRANSMIT_CCX_RPT     0x00080000

//
// Define the rate information bits for the transmit packet header.
//

#define RTLW81_TRANSMIT_RATE_INFORMATION_40MHZ          0x02000000
#define RTLW81_TRANSMIT_RATE_INFORMATION_SCO_MASK       0x00300000
#define RTLW81_TRANSMIT_RATE_INFORMATION_SCO_SHIFT      20
#define RTLW81_TRANSMIT_RATE_INFORMATION_SCO_SCA        1
#define RTLW81_TRANSMIT_RATE_INFORMATION_SCO_SCB        2
#define RTLW81_TRANSMIT_RATE_INFORMATION_HWRTSEN        0x00002000
#define RTLW81_TRANSMIT_RATE_INFORMATION_RTSEN          0x00001000
#define RTLW81_TRANSMIT_RATE_INFORMATION_CTS2SELF       0x00000800
#define RTLW81_TRANSMIT_RATE_INFORMATION_DRVRATE        0x00000100
#define RTLW81_TRANSMIT_RATE_INFORMATION_HWSEQ          0x00000080
#define RTLW81_TRANSMIT_RATE_INFORMATION_QOS            0x00000040
#define RTLW81_TRANSMIT_RATE_INFORMATION_RTSRATE_MASK   0x0000003F
#define RTLW81_TRANSMIT_RATE_INFORMATION_RTSRATE_SHIFT  0
#define RTLW81_TRANSMIT_RATE_INFORMATION_RTSRATE_OFDM24 8

//
// Define the data rate information bits for the transmit packet header.
//

#define RTLW81_TRANSMIT_DATA_RATE_INFORMATION_AGG_NUMBER_MASK  0xFF000000
#define RLTW81_TRANSMIT_DATA_RATE_INFORMATION_AGG_NUMBER_SHIFT 24
#define RTLW81_TRANSMIT_DATA_RATE_INFORMATION_OFDM24           0x0001FF00
#define RTLW81_TRANSMIT_DATA_RATE_INFORMATION_SGI              0x00000040
#define RTLW81_TRANSMIT_DATA_RATE_INFORMATION_DATA_RATE_MASK   0x0000003F
#define RTLW81_TRANSMIT_DATA_RATE_INFORMATION_DATA_RATE_SHIFT  0
#define RTLW81_TRANSMIT_DATA_RATE_INFORMATION_DATA_RATE_OFDM54 11
#define RTLW81_TRANSMIT_DATA_RATE_INFORMATION_DATA_RATE_CCK1   0

//
// Define the sequence bits for the transmit packet header.
//

#define RTLW81_TRANSMIT_SEQUENCE_HARDWARE 0x8000
#define RTLW81_TRANSMIT_SEQUENCE_MASK     0x0FFF

//
// Define the bits for programming the EFUSE registers in order to read the ROM.
//

#define RTLW81_EFUSE_MAX_ADDRESS 512

#define RTLW81_EFUSE_INVALID                      0xFF
#define RTLW81_EFUSE_ENCODING_MASK                0x1F
#define RTLW81_EFUSE_ENCODING_EXTENDED            0x0F
#define RTLW81_EFUSE_DEFAULT_OFFSET_MASK          0xF0
#define RTLW81_EFUSE_DEFAULT_OFFSET_SHIFT         4
#define RTLW81_EFUSE_EXTENDED_FIRST_OFFSET_MASK   0xE0
#define RTLW81_EFUSE_EXTENDED_FIRST_OFFSET_SHIFT  5
#define RTLW81_EFUSE_EXTENDED_ENCODING_MASK       0x0F
#define RTLW81_EFUSE_EXTENDED_ENCODING_NO_OFFSET  0x0F
#define RTLW81_EFUSE_EXTENDED_SECOND_OFFSET_MASK  0xF0
#define RTLW81_EFUSE_EXTENDED_SECOND_OFFSET_SHIFT 1
#define RTLW81_EFUSE_VALID_MASK                   0x0F

//
// Define the number of firmware boxes available.
//

#define RTLW81_FIRMWARE_BOX_COUNT 4

//
// Define the size of a firmware command message.
//

#define RTLW81_FIRMWARE_COMMAND_MAX_MESSAGE_LENGTH 5

//
// Define the maximum length of a firmware command that does not need to set
// the extension flag.
//

#define RTLW81_FIRMWARE_COMMAND_MAX_NO_EXTENSION_LENGTH 3

//
// Define the values for the RTL81xx firmware commands.
//

#define RTLW81_FIRMWARE_COMMAND_FLAG_EXTENSION    0x80
#define RTLW81_FIRMWARE_COMMAND_AP_OFFLOAD        0x00
#define RTLW81_FIRMWARE_COMMAND_SET_POWER_MODE    0x01
#define RTLW81_FIRMWARE_COMMAND_JOIN_BSS_RPT      0x02
#define RTLW81_FIRMWARE_COMMAND_RSVD_PAGE         0x03
#define RTLW81_FIRMWARE_COMMAND_RSSI              0x04
#define RTLW81_FIRMWARE_COMMAND_RSSI_SETTING      0x05
#define RTLW81_FIRMWARE_COMMAND_MAC_ID_CONFIG     0x06
#define RTLW81_FIRMWARE_COMMAND_MAC_ID_PS_MODE    0x07
#define RTLW81_FIRMWARE_COMMAND_P2P_PS_OFFLOAD    0x08
#define RTLW81_FIRMWARE_COMMAND_SELECTIVE_SUSPEND 0x09

//
// Define the MAC ID bits for the MAC ID config firmware command.
//

#define RTLW81_MAC_ID_CONFIG_COMMAND_ID_VALID     0x80
#define RTLW81_MAC_ID_CONFIG_COMMAND_ID_BROADCAST 0x04
#define RTLW81_MAC_ID_CONFIG_COMMAND_ID_BSS       0x00

//
// Define the MAC ID mask bit for the MAC ID config firmware command.
//

#define RTLW81_MAC_ID_CONFIG_COMMAND_MASK_MODE_MASK  0xF0000000
#define RTLW81_MAC_ID_CONFIG_COMMAND_MASK_MODE_SHIFT 28
#define RTLW81_MAC_ID_CONFIG_COMMAND_MASK_RATE_MASK  0x0FFFFFFF
#define RTLW81_MAC_ID_CONFIG_COMMAND_MASK_RATE_SHIFT 0

//
// Define the maximum received packet rate that stores CCK PHY status.
//

#define RTLW81_PHY_STATUS_MAX_CCK_RATE 3

//
// Define the AGC report bits for the RTL8188E CCK PHY status.
//

#define RTLW81_8188E_PHY_CCK_AGC_REPORT_LNA_MASK  0xE0
#define RTLW81_8188E_PHY_CCK_AGC_REPORT_LNA_SHIFT 5
#define RTLW81_8188E_PHY_CCK_AGC_REPORT_VGA_MASK  0x1F
#define RTLW81_8188E_PHY_CCK_AGC_REPORT_VGA_SHIFT 0

//
// Define the AGC report bits for the high powered CCK PHY status.
//

#define RTLW81_DEFAULT_PHY_CCK_HP_AGC_REPORT_INDEX_MASK  0x60
#define RTLW81_DEFAULT_PHY_CCK_HP_AGC_REPORT_INDEX_SHIFT 5
#define RTLW81_DEFAULT_PHY_CCK_HP_AGC_REPORT_VALUE_MASK  0x1F
#define RTLW81_DEFAULT_PHY_CCK_HP_AGC_REPORT_VALUE_SHIFT 0

//
// Define the AGC report bits for the default CCK PHY status.
//

#define RTLW81_DEFAULT_PHY_CCK_AGC_REPORT_INDEX_MASK  0xC0
#define RTLW81_DEFAULT_PHY_CCK_AGC_REPORT_INDEX_SHIFT 6
#define RTLW81_DEFAULT_PHY_CCK_AGC_REPORT_VALUE_MASK  0x3E
#define RTLW81_DEFAULT_PHY_CCK_AGC_REPORT_VALUE_SHIFT 1

//
// Define the AGC report bits for the high throughput OFDM PHY status.
//

#define RTLW81_PHY_OFDM_AGC_REPORT_INDEX 1
#define RTLW81_PHY_OFDM_AGC_REPORT_MASK  0xFE
#define RTLW81_PHY_OFDM_AGC_REPORT_SHIFT 1

//
// Default the value to subtract from the AGC report to get an RSSI value in
// decibels.
//

#define RTLW81_PHY_OFDM_AGC_REPORT_OFFSET 110

//
// ------------------------------------------------------ Data Type Definitions
//

typedef enum _RTLW81_REGISTER {
    Rtlw81RegisterSysIsoControl = 0x000,
    Rtlw81RegisterSysFunctionEnable = 0x002,
    Rtlw81RegisterApsFsmco = 0x004,
    Rtlw81RegisterSysClock = 0x008,
    Rtlw81RegisterAfeMisc = 0x010,
    Rtlw81RegisterSps0Control = 0x011,
    Rtlw81RegisterTemperatureControl = 0x015,
    Rtlw81RegisterPaSetting = 0x016,
    Rtlw81RegisterRsvControl = 0x01C,
    Rtlw81RegisterRfControl = 0x01F,
    Rtlw81RegisterLdov12dControl = 0x021,
    Rtlw81RegisterLdohci12Control = 0x022,
    Rtlw81RegisterLpldoControl = 0x023,
    Rtlw81RegisterAfeXtalControl0 = 0x024,
    Rtlw81RegisterAfeXtalControl1 = 0x025,
    Rtlw81RegisterAfeXtalControl2 = 0x026,
    Rtlw81RegisterAfeXtalControl3 = 0x027,
    Rtlw81RegisterAfePllControl = 0x028,
    Rtlw81RegisterEfuseControl = 0x030,
    Rtlw81RegisterGpioMuxConfig = 0x040,
    Rtlw81RegisterLedConfig0 = 0x04C,
    Rtlw81RegisterLedConfig1 = 0x04D,
    Rtlw81RegisterLedConfig2 = 0x04E,
    Rtlw81RegisterLedConfig3 = 0x04F,
    Rtlw81RegisterMcuFirmwareDownload0 = 0x080,
    Rtlw81RegisterMcuFirmwareDownload1 = 0x081,
    Rtlw81RegisterMcuFirmwareDownload2 = 0x082,
    Rtlw81RegisterMcuFirmwareDownload3 = 0x083,
    Rtlw81RegisterHmeBoxExtension = 0x088,
    Rtlw81Register8188eInterruptMask = 0x0B0,
    Rtlw81Register8188eInterruptStatus = 0x0B4,
    Rtlw81Register8188eInterruptExtraMask = 0x0B8,
    Rtlw81Register8188eInterruptExtraStatus = 0x0BC,
    Rtlw81RegisterEfuseAccess = 0x0CF,
    Rtlw81RegisterHponFsm = 0x0EC,
    Rtlw81RegisterSysConfiguration = 0x0F0,
    Rtlw81RegisterConfiguration = 0x100,
    Rtlw81RegisterPageConfiguration = 0x104,
    Rtlw81RegisterTransmitReceiveDma = 0x10C,
    Rtlw81RegisterTransmitReceiveBoundary0 = 0x114,
    Rtlw81RegisterTransmitReceiveBoundary1 = 0x115,
    Rtlw81RegisterTransmitReceiveBoundary2 = 0x116,
    Rtlw81RegisterTransmitReceiveBoundary3 = 0x117,
    Rtlw81RegisterDefaultInterruptMask = 0x120,
    Rtlw81RegisterDefaultInterruptStatus = 0x124,
    Rtlw81RegisterHmetfr0 = 0x1CC,
    Rtlw81RegisterHmetfr1 = 0x1CD,
    Rtlw81RegisterHmetfr2 = 0x1CE,
    Rtlw81RegisterHmetfr3 = 0x1CF,
    Rtlw81RegisterHmeBox = 0x1D0,
    Rtlw81RegisterLltInit = 0x1E0,
    Rtlw81RegisterQueuePageCount = 0x200,
    Rtlw81RegisterTransmitDescriptorControl0 = 0x208,
    Rtlw81RegisterTransmitDescriptorControl1 = 0x209,
    Rtlw81RegisterTransmitDescriptorControl2 = 0x20A,
    Rtlw81RegisterTransmitDescriptorControl3 = 0x20B,
    Rtlw81RegisterNormalQueuePageCount = 0x214,
    Rtlw81RegisterReceiveDmaAggPgTh0 = 0x280,
    Rtlw81RegisterReceiveDmaAggPgTh1 = 0x281,
    Rtlw81RegisterFirmwareHardwareTransmitQueueControl = 0x420,
    Rtlw81RegisterHardwareSequencingControl = 0x423,
    Rtlw81RegisterTransmitPacketNormalQueueBoundary = 0x424,
    Rtlw81RegisterTransmitPacketQueueBoundary = 0x425,
    Rtlw81RegisterSpecSifs = 0x428,
    Rtlw81RegisterRetryLimit = 0x42A,
    Rtlw81RegisterDarfrc0 = 0x430,
    Rtlw81RegisterDarfrc1 = 0x434,
    Rtlw81RegisterRarfrc0 = 0x438,
    Rtlw81RegisterRarfrc1 = 0x43C,
    Rtlw81RegisterReceiveResponseRate = 0x440,
    Rtlw81RegisterAggregateLengthLimit = 0x458,
    Rtlw81RegisterTransmitPacketWmacLbkBfHd = 0x45d,
    Rtlw81RegisterIniRtsRateSelect = 0x480,
    Rtlw81RegisterIniDataRateSelectBss = 0x484,
    Rtlw81RegisterIniDataRateSelectBroadcast = 0x488,
    Rtlw81RegisterProtModeControl = 0x4C8,
    Rtlw81RegisterMaxAggregationNumber = 0x4CA,
    Rtlw81RegisterBarModeControl = 0x4CC,
    Rtlw81RegisterEdcaVoParam = 0x500,
    Rtlw81RegisterEdcaViParam = 0x504,
    Rtlw81RegisterEdcaBeParam = 0x508,
    Rtlw81RegisterEdcaBkParam = 0x50C,
    Rtlw81RegisterBeaconTcfg = 0x510,
    Rtlw81RegisterPifs = 0x512,
    Rtlw81RegisterSifsCck = 0x514,
    Rtlw81RegisterSifsOfdm = 0x516,
    Rtlw81RegisterAggregateBreakTime = 0x51A,
    Rtlw81RegisterTransmitPause = 0x522,
    Rtlw81RegisterRdControl = 0x524,
    Rtlw81RegisterTbttProhibit = 0x540,
    Rtlw81RegisterNavProtLength = 0x546,
    Rtlw81RegisterBeaconControl = 0x550,
    Rtlw81RegisterTsfReset = 0x553,
    Rtlw81RegisterBeaconInterval = 0x554,
    Rtlw81RegisterDriverEarlyInt = 0x558,
    Rtlw81RegisterBeaconDmaTime = 0x559,
    Rtlw81RegisterTsftr0 = 0x560,
    Rtlw81RegisterTsftr1 = 0x564,
    Rtlw81RegisterAtiwnd = 0x55A,
    Rtlw81RegisterBeaconMaxError = 0x55D,
    Rtlw81RegisterApsdControl = 0x600,
    Rtlw81RegisterBandwidthMode = 0x603,
    Rtlw81RegisterReceiveConfiguration = 0x608,
    Rtlw81RegisterReceiveDriverInformationSize = 0x60F,
    Rtlw81RegisterMacAddress = 0x610,
    Rtlw81RegisterBssid0 = 0x618,
    Rtlw81RegisterBssid1 = 0x61C,
    Rtlw81RegisterMulticast1 = 0x620,
    Rtlw81RegisterMulticast2 = 0x624,
    Rtlw81RegisterMacSpecSifs = 0x63A,
    Rtlw81RegisterR2tSifs = 0x63C,
    Rtlw81RegisterT2tSifs = 0x63E,
    Rtlw81RegisterAckTimeout = 0x640,
    Rtlw81RegisterCamCommand = 0x670,
    Rtlw81RegisterReceiveManagementFilter = 0x6A0,
    Rtlw81RegisterReceiveControlFilter = 0x6A2,
    Rtlw81RegisterReceiveDataFilter = 0x6A4,
    Rtlw81RegisterFpga0Rfmod = 0x800,
    Rtlw81RegisterFpga0TransmitInfo = 0x804,
    Rtlw81RegisterHssiParameter1 = 0x820,
    Rtlw81RegisterHssiParameter2 = 0x824,
    Rtlw81RegisterTransmitAgcRate1806Chain1 = 0x830,
    Rtlw81RegisterTransmitAgcRate5424Chain1 = 0x834,
    Rtlw81RegisterTransmitAgcBCck155Mcs32 = 0x838,
    Rtlw81RegisterTransmitAgcMcs03Mcs00Chain1 = 0x83C,
    Rtlw81RegisterLssiParameter = 0x840,
    Rtlw81RegisterTransmitAgcMcs07Mcs04Chain1 = 0x848,
    Rtlw81RegisterTransmitAgcMcs11Mcs08Chain1 = 0x84C,
    Rtlw81RegisterFpga0RfOeInterface = 0x860,
    Rtlw81RegisterTransmitAgcMcs15Mcs12Chain1 = 0x868,
    Rtlw81RegisterTransmitAgcBCck11ACck211 = 0x86C,
    Rtlw81RegisterFpga0RfSoftwareInterface = 0x870,
    Rtlw81RegisterFpga0AnaParam2 = 0x884,
    Rtlw81RegisterLssiReadback = 0x8A0,
    Rtlw81RegisterHspiReadback = 0x8B8,
    Rtlw81RegisterFpga1Rfmod = 0x900,
    Rtlw81RegisterFpga1TransmitInfo = 0x90C,
    Rtlw81RegisterCck0AfeSetting = 0xA04,
    Rtlw81RegisterOfdm0TransmitPathEnable = 0xC04,
    Rtlw81RegisterOfdm0AgcCore1 = 0xC50,
    Rtlw81RegisterOfdm0AgcParam1 = 0xC70,
    Rtlw81RegisterOfdm0AgcrsstiTable = 0xC78,
    Rtlw81RegisterOfdm1Lstf0 = 0xD00,
    Rtlw81RegisterOfdm1Lstf1 = 0xD01,
    Rtlw81RegisterOfdm1Lstf2 = 0xD02,
    Rtlw81RegisterOfdm1Lstf3 = 0xD03,
    Rtlw81RegisterTransmitAgcRate1806Chain0 = 0xE00,
    Rtlw81RegisterTransmitAgcRate5424Chain0 = 0xE04,
    Rtlw81RegisterTransmitAgcACck1Mcs32 = 0xE08,
    Rtlw81RegisterTransmitAgcMcs03Mcs00Chain0 = 0xE10,
    Rtlw81RegisterTransmitAgcMcs07Mcs04Chain0 = 0xE14,
    Rtlw81RegisterTransmitAgcMcs11Mcs08Chain0 = 0xE18,
    Rtlw81RegisterTransmitAgcMcs15Mcs12Chain0 = 0xE1C,
    Rtlw81Register8192c1T2RInit0 = 0xE74,
    Rtlw81Register8192c1T2RInit1 = 0xE78,
    Rtlw81Register8192c1T2RInit2 = 0xE7C,
    Rtlw81Register8192c1T2RInit3 = 0xE80,
    Rtlw81Register8192c1T2RInit4 = 0xE84,
    Rtlw81Register8192c1T2RInit5 = 0xE88,
    Rtlw81RegisterFirmwareDownload = 0x1000,
    Rtlw81RegisterUsbEnable = 0xFE10,
    Rtlw81RegisterUsbInterference0 = 0xFE40,
    Rtlw81RegisterUsbInterference1 = 0xFE41,
    Rtlw81RegisterUsbInterference2 = 0xFE42,
    Rtlw81RegisterUsbSpecialOption = 0xFE55,
    Rtlw81RegisterUsbDmaAggTo = 0xFE5B,
    Rtlw81RegisterUsbAggTo = 0xFE5C,
    Rtlw81RegisterUsbAggTh = 0xFE5D,
    Rtlw81RegisterUsbEndpoint = 0xFE66,
} RTLW81_REGISTER, *PRTLW81_REGISTER;

typedef enum _RTLW81_RF_REGISTER {
    Rtlw81RfRegisterAc = 0x00,
    Rtlw81RfRegisterIpa = 0x15,
    Rtlw81RfRegisterChannelBandwidth = 0x18,
    Rtlw81RfRegisterReceiveG1 = 0x1A,
    Rtlw81RfRegisterReceiveG2 = 0x1B,
} RTLW81_RF_REGISTER, *PRTLW81_RF_REGISTER;

typedef enum _RTLW81_EFUSE_REGISTER {
    Rtlw81EfuseRegisterPaSetting = 0x1FA,
} RTLW81_EFUSE_REGISTER, *PRTLW81_EFUSE_REGISTER;

/*++

Structure Description:

    This structure defines the wireless RTL81xx firwmare header.

Members:

    Signature - Stores the firmware's signature.

    Category - Stores the firmware's category.

    Function - Stores the firmware's function.

    Version - Stores the firmware's version.

    Subversion - Stores the firmware's subversion.

    Month - Stores the month in which the firmware was created.

    MonthDay - Stores the day of the month on which the firmware was created.

    Hour - Stores the hour in which the firmware was created.

    Minute - Stores the minute in which the firmware was created.

    RamcodeSize - Stores the size of the code.

    Reserved1 - Stores 2 reserved byte.

    SvnIndex - Stores the SVN index of the firwmare.

    Reserved2 - Stores 4 reserved bytes.

    Reserved3 - Stores 4 reserved bytes.

    Reserved4 - Stores 4 reserved bytes.

--*/

typedef struct _RTLW81_FIRMWARE_HEADER {
    USHORT Signature;
    UCHAR Category;
    UCHAR Function;
    USHORT Version;
    USHORT Subversion;
    UCHAR Month;
    UCHAR MonthDay;
    UCHAR Hour;
    UCHAR Minute;
    USHORT RamcodeSize;
    USHORT Reserved1;
    ULONG SvnIndex;
    ULONG Reserved2;
    ULONG Reserved3;
    ULONG Reserved4;
} PACKED RTLW81_FIRMWARE_HEADER, *PRTLW81_FIRMWARE_HEADER;

/*++

Structure Description:

    This structure defines the header of bulk IN receive packets.

Members:

    LengthAndErrorFlags - Stores the length of the packet and the error flags.
        See RTLW81_RECEIVE_* for definitions.

    Status - Stores status information for the received packet. See
        RTLW81_RECEIVE_STATUS_* for definitions.

    Reserved1 - Stores 4 reserved bytes.

    Reserved2 - Stores 2 reserved bytes.

    PacketCount - Stores the total number of packets received by the bulk IN
        transfer that contains this packet.

    Reserved3 - Stores 1 reserved byte.

    RateInformation - Stores rate and high throughput status information. See
        RTLW81_RECEIVE_RATE_INFORMATION_* for definitions.

    Reserved4 - Stores 4 reserved bytes.

    Reserved5 - Stores 4 resreved bytes.

--*/

typedef struct _RTLW81_RECEIVE_HEADER {
    USHORT LengthAndErrorFlags;
    USHORT Status;
    ULONG Reserved1;
    USHORT Reserved2;
    UCHAR PacketCount;
    UCHAR Reserved3;
    ULONG RateInformation;
    ULONG Reserved4;
    ULONG Reserved5;
} PACKED RTLW81_RECEIVE_HEADER, *PRTLW81_RECEIVE_HEADER;

/*++

Structure Description:

    This structure defines the RTL8188E devices CCK PHY status.

Members:

    PathAgc - Stores the path automatic gain control.

    SignalQuality - Stores the signal quality information.

    AgcReport - Stores the automatic gain control report.

    Reserved0 - Stores 1 reserved byte.

    Reserved1 - Stores 1 reserved byte.

    NoisePower - Stores the noise power information.

    PathCfoTail - Stores the path's CFO tail.

    PacketsMask - Stores packet mask information.

    StreamReceiveEvm - Stores EVM status for the receive stream.

    PathReceiveSnr - Stores the SNR status for the receive path.

    NoisePowerDbLsb - Stores the noise power level information.

    Reserved2 - Stores 2 reserved bytes.

    StreamCsi - Stores stream CSI status.

    StreamTargetCsi - Stores the stream's target CSI value.

    SignalEvm - Stores the signal EVM status.

    Reserved3 - Stores 3 reserved bytes.

--*/

typedef struct _RTLW81_8188E_PHY_STATUS_CCK {
    UCHAR PathAgc[2];
    UCHAR SignalQuality;
    UCHAR AgcReport;
    UCHAR Reserved0;
    UCHAR Reserved1;
    UCHAR NoisePower;
    UCHAR PathCfoTail[2];
    UCHAR PacketsMask[2];
    UCHAR StreamReceiveEvm[2];
    UCHAR PathReceiveSnr[2];
    UCHAR NoisePowerDbLsb;
    UCHAR Reserved2[3];
    UCHAR StreamCsi[2];
    UCHAR StreamTargetCsi[2];
    UCHAR SignalEvm;
    UCHAR Reserved3[2];
} PACKED RTLW81_8188E_PHY_STATUS_CCK, *PRTLW81_8188E_PHY_STATUS_CCK;

/*++

Structure Description:

    This structure defines the default RTL81xx wireless CCK PHY status.

Members:

    AdcPowerDb - Stores the ADC power decibel readings.

    SignalQualityReport - Stores the signal quality report.

    AgcReport - Stores the automatic gain control report.

--*/

typedef struct _RTLW81_DEFAULT_PHY_STATUS_CCK {
    UCHAR AdcPowerDb[4];
    UCHAR SignalQualityReport;
    UCHAR AgcReport;
} PACKED RTLW81_DEFAULT_PHY_STATUS_CCK, *PRTLW81_DEFAULT_PHY_STATUS_CCK;

/*++

Structure Description:

    This structure defines the RTL81xx high throughput PHY status.

Members:

    PhyStatus - Stores an array of PHY status information.

--*/

typedef struct _RTLW81_PHY_STATUS_OFDM {
    ULONG PhyStatus[8];
} PACKED RTLW81_PHY_STATUS_OFDM, *PRTLW81_PHY_STATUS_OFDM;

/*++

Structure Description:

    This structure defines the header of bulk OUT transmit packets.

Members:

    PacketLength - Stores the length of the packet to transmit.

    Offset - Stores the offset within the packet to the start of the data.

    TypeFlags - Stores a bitmask of flags describing the type of packet being
        sent. See RTLW81_TRANSMIT_TYPE_FLAGS_* for definitions.

    Identification - Stores identification information as well as other flags.
        See RTLW81_TRANSMIT_IDENTIFICATION_* for details.

    AggBkFlag - Stores a single flag for the aggregation background state. See
        RTLW81_TRANSMIT_AGG_BK_FLAG.

    Reserved1 - Stores 2 reserved bytes.

    Sequence - Stores the sequence number for the 802.11 WLAN.

    RateInformation - Stores rate information and other flags. See
        RTLW81_TRANSMIT_RATE_FLAG_* for definitions.

    DataRateInformation - Stores data rate information and other flags. See
        RTLW81_TRANSMIT_DATA_RATE_FLAG_* for definitions.

    Reserved2 - Stores 4 reserved bytes.

    HeaderChecksum - Stores the 16-bit XOR checksum of the transmit header.

    Reserved3 - Stores 2 reserved bytes.

--*/

typedef struct _RTLW81_TRANSMIT_HEADER {
    USHORT PacketLength;
    UCHAR Offset;
    UCHAR TypeFlags;
    ULONG Identification;
    ULONG AggBkFlag;
    USHORT Reserved1;
    USHORT Sequence;
    ULONG RateInformation;
    ULONG DataRateInformation;
    ULONG Reserved2;
    USHORT HeaderChecksum;
    USHORT Reserved3;
} PACKED RTLW81_TRANSMIT_HEADER, *PRTLW81_TRANSMIT_HEADER;

/*++

Structure Description:

    This structure defines an RTL81xx wireless firmware command.

Members:

    Id - Stores the ID of the firmware command.

    Message - Stores the data contents of the firmware command.

--*/

typedef struct RTLW81_FIRMWARE_COMMAND {
    UCHAR Id;
    UCHAR Message[RTLW81_FIRMWARE_COMMAND_MAX_MESSAGE_LENGTH];
} PACKED RTLW81_FIRMWARE_COMMAND, *PRTLW81_FIRMWARE_COMMAND;

/*++

Structure Description:

    This structure defines a MAC ID firmware command for the RTL81xx wireless
    devices.

Members:

    Mask - Stores the data mask to send to the firmware.

    MacId - Stores the MAC ID the firmware command targets.

--*/

typedef struct _RTLW81_MAC_ID_CONFIG_COMMAND {
    ULONG Mask;
    UCHAR MacId;
} PACKED RTLW81_MAC_ID_CONFIG_COMMAND, *PRTLW81_MAC_ID_CONFIG_COMMAND;

/*++

Structure Description:

    This structure defines the power information captured from the ROM for
    default devices. This information is used to program the power for new
    channels.

Members:

    CckTransmitPower - Stores the CCK transmit power settings for each group in
        each chain.

    Ht40TransmitPower - Stores the high throughput 40MHz transmit power
        settings for each group in each chain.

    Ht40TransmitPowerDiff - Stores the high throughput 40MHz transmit power
        differences for each group.

    Ht40MaxPower - Stores the maximum power setting for each group at 40MHz.

    Ht20TransmitPowerDiff - Store the high throughput 20MHz transmit power
        differences for each group.

    Ht20MaxPower - Stores the maximum power setting for each group at 20MHz.

    OfdmTransmitPowerDiff - Stores the OFDM transmit power differences for each
        group.

--*/

typedef struct _RTLW81_POWER_DEFAULT {
    UCHAR CckTransmitPower[RTLW81_MAX_CHAIN_COUNT][RTLW81_DEFAULT_GROUP_COUNT];
    UCHAR Ht40TransmitPower[RTLW81_MAX_CHAIN_COUNT][RTLW81_DEFAULT_GROUP_COUNT];
    UCHAR Ht40TransmitPowerDiff[RTLW81_DEFAULT_GROUP_COUNT];
    UCHAR Ht40MaxPower[RTLW81_DEFAULT_GROUP_COUNT];
    UCHAR Ht20TransmitPowerDiff[RTLW81_DEFAULT_GROUP_COUNT];
    UCHAR Ht20MaxPower[RTLW81_DEFAULT_GROUP_COUNT];
    UCHAR OfdmTransmitPowerDiff[RTLW81_DEFAULT_GROUP_COUNT];
} RTLW81_POWER_DEFAULT, *PRTLW81_POWER_DEFAULT;

/*++

Structure Description:

    This structure defines the power information captured from the ROM for
    RTL8188E devices. This information is used to program the power for new
    channels.

Members:

    CckTransmitPower - Stores the CCK transmit power settings for each group.

    Ht40TransmitPower - Stores the high throughput 40MHz transmit power
        settings for each group.

    Bw20TransmitPowerDiff - Stores the bandwidth 20MHz power difference.

    OfdmTransmitPowerDiff - Stores the OFDM transmit power difference.

--*/

typedef struct _RTLW81_POWER_8188E {
    UCHAR CckTransmitPower[RTLW81_8188E_GROUP_COUNT];
    UCHAR Ht40TransmitPower[RTLW81_8188E_GROUP_COUNT];
    UCHAR Bw20TransmitPowerDiff;
    UCHAR OfdmTransmitPowerDiff;
} RTLW81_POWER_8188E, *PRTLW81_POWER_8188E;

typedef enum _RTLW81_BULK_OUT_TYPE {
    Rtlw81BulkOutBe,
    Rtlw81BulkOutBk,
    Rtlw81BulkOutVi,
    Rtlw81BulkOutVo,
    Rtlw81BulkOutTypeCount
} RTLW81_BULK_OUT_TYPE, *PRTLW81_BULK_OUT_TYPE;

/*++

Structure Description:

    This structure defines an RTL81xx WIFI device.

Members:

    OsDevice - Stores a pointer to the system device object.

    Net80211Link - Stores a pointer to the 802.11 core networking link.

    UsbCoreHandle - Stores the handle returned by the USB core.

    ReferenceCount - Stores the number of references on the structure.

    Flags - Stores a bitmask of flags that hold device state or type
        information. See RTLW81_FLAG_* for definitions.

    TransmitChainCount - Stores the number of transmit chains on the device.

    ReceiveChainCount - Stores the number of receive chains on the device.

    CurrentChannel - Stores the current channel the device is set to use.

    IoBuffer - Stores a pointer to the I/O buffer used for both the bulk
        receive and the control transfers.

    ControlTransfer - Stores a pointer to the control transfer used for
        register reads and writes.

    BulkInTransfer - Stores an array of pointers to transfers used to receive
        packets.

    BulkOutFreeTransferList - Stores an array of lists of free transfers to
        use to send data.

    BulkOutTransferCount - Stores the number of currently submitted bulk out
        transfers.

    BulkOutListLock - Stores a pointer to a lock that protects the list of free
        bulk OUT transfers.

    InitializationStatus - Stores the accumulated initialization status from
        the register reads and writes.

    InitializationPhase - Stores the current initialization phase. Phase 0 goes
        up to kicking off the firmware load and phase 1 completes the
        initialization process after the firmware is loaded.

    InitializationIrp - Stores a pointer to the IRP that is driving device
        initialization.

    Firmware - Stores a pointer to the loaded firmware binary file.

    FirmwareBox - Store the formware box where the next firmware command should
        be sent.

    InterfaceClaimed - Stores a boolean indicating if the interface has
        already been claimed.

    InterfaceNumber - Stores the number of the interface this device interacts
        on.

    BulkInEndpoint - Stores the endpoint number for the bulk in endpoint.

    BulkOutEndpoint - Stores an array of endpoint numbers for the bulk out
        endpoints.

    BulkOutEndpointCount - Stores the number of bulk out endpoints found during
        initialization.

    BulkOutTypeEndpointIndex - Stores an array of endpoint indices for each of
        the bulk out transfer types.

    MacAddress - Stores the default MAC address of the device.

    BoardType - Stores the board type of the RTL81xx device.

    Regulatory - Stores regulatory information for the RTL81xx device.

    CrystalCapbility - Stores the capability of the crystal for the RTL8188E
        device.

    PaSetting - Stores the PA setting for the RTL81xx device.

    Power - Stores channel power information captured from the ROM.

--*/

typedef struct _RTLW81_DEVICE {
    PDEVICE OsDevice;
    PNET80211_LINK Net80211Link;
    HANDLE UsbCoreHandle;
    volatile ULONG ReferenceCount;
    ULONG Flags;
    ULONG TransmitChainCount;
    ULONG ReceiveChainCount;
    ULONG CurrentChannel;
    PIO_BUFFER IoBuffer;
    PUSB_TRANSFER ControlTransfer;
    PUSB_TRANSFER BulkInTransfer[RTLW81_BULK_IN_TRANSFER_COUNT];
    LIST_ENTRY BulkOutFreeTransferList[RTLW81_MAX_BULK_OUT_ENDPOINT_COUNT];
    volatile ULONG BulkOutTransferCount;
    PQUEUED_LOCK BulkOutListLock;
    KSTATUS InitializationStatus;
    ULONG InitializationPhase;
    PIRP InitializationIrp;
    PLOADED_FILE Firmware;
    UCHAR FirmwareBox;
    BOOL InterfaceClaimed;
    UCHAR InterfaceNumber;
    UCHAR BulkInEndpoint;
    UCHAR BulkOutEndpoint[RTLW81_MAX_BULK_OUT_ENDPOINT_COUNT];
    UCHAR BulkOutEndpointCount;
    UCHAR BulkOutTypeEndpointIndex[Rtlw81BulkOutTypeCount];
    UCHAR MacAddress[NET80211_ADDRESS_SIZE];
    UCHAR BoardType;
    UCHAR Regulatory;
    UCHAR CrystalCapability;
    UCHAR PaSetting;
    union {
        RTLW81_POWER_DEFAULT Default;
        RTLW81_POWER_8188E Rtlw8188e;
    } Power;

} RTLW81_DEVICE, *PRTLW81_DEVICE;

//
// -------------------------------------------------------------------- Globals
//

extern PDRIVER Rtlw81Driver;
extern NET80211_RATE_INFORMATION RtlwDefaultRateInformation;

//
// -------------------------------------------------------- Function Prototypes
//

KSTATUS
Rtlw81Send (
    PVOID DeviceContext,
    PNET_PACKET_LIST PacketList
    );

/*++

Routine Description:

    This routine sends data through the network.

Arguments:

    DeviceContext - Supplies a pointer to the device context associated with
        the link down which this data is to be sent.

    PacketList - Supplies a pointer to a list of network packets to send. Data
        in these packets may be modified by this routine, but must not be used
        once this routine returns.

Return Value:

    STATUS_SUCCESS if all packets were sent.

    STATUS_RESOURCE_IN_USE if some or all of the packets were dropped due to
    the hardware being backed up with too many packets to send.

    Other failure codes indicate that none of the packets were sent.

--*/

KSTATUS
Rtlw81GetSetInformation (
    PVOID DeviceContext,
    NET_LINK_INFORMATION_TYPE InformationType,
    PVOID Data,
    PUINTN DataSize,
    BOOL Set
    );

/*++

Routine Description:

    This routine gets or sets the network device layer's link information.

Arguments:

    DeviceContext - Supplies a pointer to the device context associated with
        the link for which information is being set or queried.

    InformationType - Supplies the type of information being queried or set.

    Data - Supplies a pointer to the data buffer where the data is either
        returned for a get operation or given for a set operation.

    DataSize - Supplies a pointer that on input contains the size of the data
        buffer. On output, contains the required size of the data buffer.

    Set - Supplies a boolean indicating if this is a get operation (FALSE) or a
        set operation (TRUE).

Return Value:

    Status code.

--*/

KSTATUS
Rtlw81SetChannel (
    PVOID DeviceContext,
    ULONG Channel
    );

/*++

Routine Description:

    This routine sets the 802.11 link's channel to the given value.

Arguments:

    DeviceContext - Supplies a pointer to the device context associated with
        the 802.11 link whose channel is to be set.

    Channel - Supplies the channel to which the device should be set.

Return Value:

    Status code.

--*/

KSTATUS
Rtlw81SetState (
    PVOID DeviceContext,
    NET80211_STATE State,
    PNET80211_BSS BssInformation
    );

/*++

Routine Description:

    This routine sets the 802.11 link to the given state. State information is
    provided to communicate the details of the 802.11 core's current state.

Arguments:

    DeviceContext - Supplies a pointer to the device context associated with
        the 802.11 link whose state is to be set.

    State - Supplies the state to which the link is being set.

    BssInformation - Supplies a pointer to the BSS information collected by the
        802.11 core.

Return Value:

    Status code.

--*/

VOID
Rtlw81BulkInTransferCompletion (
    PUSB_TRANSFER Transfer
    );

/*++

Routine Description:

    This routine is called when the bulk in transfer returns. It processes
    the notification from the device.

Arguments:

    Transfer - Supplies a pointer to the transfer that completed.

Return Value:

    None.

--*/

KSTATUS
Rtlw81pInitialize (
    PRTLW81_DEVICE Device,
    PIRP Irp
    );

/*++

Routine Description:

    This routine initializes and enables the RTL81xx wireless device.

Arguments:

    Device - Supplies a pointer to the device.

    Irp - Supplies a pointer to the IRP that is driving the initialization.

Return Value:

    Status code.

--*/

VOID
Rtlw81pDestroyBulkOutTransfers (
    PRTLW81_DEVICE Device
    );

/*++

Routine Description:

    This routine destroys the RTLW815xx device's bulk out tranfers.

Arguments:

    Device - Supplies a pointer to the device.

Return Value:

    None.

--*/

KSTATUS
Rtlw81pAddNetworkDevice (
    PRTLW81_DEVICE Device
    );

/*++

Routine Description:

    This routine adds the device to 802.11 core networking's available links.

Arguments:

    Device - Supplies a pointer to the device to add.

Return Value:

    Status code.

--*/