rtlw81hw.c 186 KB

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  1. /*++
  2. Copyright (c) 2015 Minoca Corp. All Rights Reserved
  3. Module Name:
  4. rtlw81hw.c
  5. Abstract:
  6. This module implements device support for the Realtek RTL81xx family of
  7. wireless internet controllers.
  8. Author:
  9. Chris Stevens 5-Oct-2015
  10. Environment:
  11. Kernel
  12. --*/
  13. //
  14. // ------------------------------------------------------------------- Includes
  15. //
  16. #include <minoca/kernel/driver.h>
  17. #include <minoca/net/netdrv.h>
  18. #include <minoca/net/net80211.h>
  19. #include <minoca/usb/usb.h>
  20. #include "rtlw81.h"
  21. //
  22. // --------------------------------------------------------------------- Macros
  23. //
  24. #define RTLW81_WRITE_REGISTER8(_Device, _Register, _Value) \
  25. Rtlw81pWriteRegister((_Device), (_Register), (_Value), sizeof(UCHAR))
  26. #define RTLW81_WRITE_REGISTER16(_Device, _Register, _Value) \
  27. Rtlw81pWriteRegister((_Device), (_Register), (_Value), sizeof(USHORT))
  28. #define RTLW81_WRITE_REGISTER32(_Device, _Register, _Value) \
  29. Rtlw81pWriteRegister((_Device), (_Register), (_Value), sizeof(ULONG))
  30. #define RTLW81_READ_REGISTER8(_Device, _Register) \
  31. Rtlw81pReadRegister((_Device), (_Register), sizeof(UCHAR))
  32. #define RTLW81_READ_REGISTER16(_Device, _Register) \
  33. Rtlw81pReadRegister((_Device), (_Register), sizeof(USHORT))
  34. #define RTLW81_READ_REGISTER32(_Device, _Register) \
  35. Rtlw81pReadRegister((_Device), (_Register), sizeof(ULONG))
  36. #define RTLW81_ARRAY_COUNT(_Array) (sizeof((_Array)) / sizeof((_Array)[0]))
  37. //
  38. // ---------------------------------------------------------------- Definitions
  39. //
  40. #define RTLW81_DEFAULT_CHANNEL 1
  41. //
  42. // Define the maximum number of bulk out transfers that are allowed to be
  43. // submitted at the same time.
  44. //
  45. #define RTLW81_MAX_BULK_OUT_TRANSFER_COUNT 64
  46. //
  47. // ------------------------------------------------------ Data Type Definitions
  48. //
  49. /*++
  50. Structure Description:
  51. This structure defines an RTLW81xx bulk out transfer. These transfers are
  52. allocated on demand and recycled when complete.
  53. Members:
  54. ListEntry - Stores a pointer to the next and previous bulk out transfer
  55. on the devices free transfer list.
  56. Device - Stores a pointer to the RTLW81 device that owns the transfer.
  57. UsbTransfer - Stores a pointer to the USB transfer that belongs to this
  58. SM95 transfer for the duration of its existence.
  59. Packet - Stores a pointer to the network packet buffer whose data is being
  60. sent by the USB transfer.
  61. EndpointIndex - Stores the index into the device's out endpoint array for
  62. the endpoint to which the transfer belongs.
  63. --*/
  64. typedef struct _RTLW81_BULK_OUT_TRANSFER {
  65. LIST_ENTRY ListEntry;
  66. PRTLW81_DEVICE Device;
  67. PUSB_TRANSFER UsbTransfer;
  68. PNET_PACKET_BUFFER Packet;
  69. UCHAR EndpointIndex;
  70. } RTLW81_BULK_OUT_TRANSFER, *PRTLW81_BULK_OUT_TRANSFER;
  71. /*++
  72. Structure Description:
  73. This structure defines device specific data used to initialize the device
  74. into the correct state.
  75. Members:
  76. BbRegisters - Stores the BB registers to be programed.
  77. BbValues - Stores the BB values to program into the registers.
  78. BbCount - Stores the number of BB registers to program.
  79. AgcValues - Stores the AGC values to program into the device.
  80. AgcCount - Stores the number of AGC values to program.
  81. RfRegisters - Stores an array of RF registers to program for each chain.
  82. RfValues - Stores an array of RF values to set for each chain.
  83. RfCount - Stores the number of RF registers to set for each chain.
  84. --*/
  85. typedef struct _RTLW81_DEVICE_DATA {
  86. PUSHORT BbRegisters;
  87. PULONG BbValues;
  88. ULONG BbCount;
  89. PULONG AgcValues;
  90. ULONG AgcCount;
  91. PUCHAR RfRegisters[RTLW81_MAX_CHAIN_COUNT];
  92. PULONG RfValues[RTLW81_MAX_CHAIN_COUNT];
  93. ULONG RfCount[RTLW81_MAX_CHAIN_COUNT];
  94. } RTLW81_DEVICE_DATA, *PRTLW81_DEVICE_DATA;
  95. /*++
  96. Structure Description:
  97. This structure defines the transmit power data for a default RTLW81xx
  98. device.
  99. Members:
  100. GroupPower - Stores the power data for each group.
  101. --*/
  102. typedef struct _RTLW81_DEFAULT_TRANSMIT_POWER_DATA {
  103. UCHAR GroupPower[RTLW81_DEFAULT_GROUP_COUNT][RTLW81_POWER_STATE_COUNT];
  104. } RTLW81_DEFAULT_TRANSMIT_POWER_DATA, *PRTLW81_DEFAULT_TRANSMIT_POWER_DATA;
  105. /*++
  106. Structure Description:
  107. This structure defines the transmit power data for an RTL8188EU device.
  108. Members:
  109. GroupPower - Stores the power data for each group.
  110. --*/
  111. typedef struct _RTLW81_8188E_TRANSMIT_POWER_DATA {
  112. UCHAR GroupPower[RTLW81_8188E_GROUP_COUNT][RTLW81_POWER_STATE_COUNT];
  113. } RTLW81_8188E_TRANSMIT_POWER_DATA, *PRTLW81_8188E_TRANSMIT_POWER_DATA;
  114. //
  115. // ----------------------------------------------- Internal Function Prototypes
  116. //
  117. KSTATUS
  118. Rtlw81pReadRom (
  119. PRTLW81_DEVICE Device
  120. );
  121. KSTATUS
  122. Rtlw81pDefaultInitialize (
  123. PRTLW81_DEVICE Device
  124. );
  125. KSTATUS
  126. Rtlw81p8188eInitialize (
  127. PRTLW81_DEVICE Device
  128. );
  129. KSTATUS
  130. Rtlw81pInitializeDma (
  131. PRTLW81_DEVICE Device
  132. );
  133. KSTATUS
  134. Rtlw81pInitializeFirmware (
  135. PRTLW81_DEVICE Device,
  136. PIRP Irp
  137. );
  138. VOID
  139. Rtlw81pLoadFirmwareCompletionRoutine (
  140. PVOID Context,
  141. PLOADED_FILE File
  142. );
  143. VOID
  144. Rtlw81pLcCalibration (
  145. PRTLW81_DEVICE Device
  146. );
  147. VOID
  148. Rtlw81pSetChannel (
  149. PRTLW81_DEVICE Device,
  150. ULONG Channel
  151. );
  152. VOID
  153. Rtlw81pEnableChannelTransmitPower (
  154. PRTLW81_DEVICE Device,
  155. ULONG Chain,
  156. ULONG Channel
  157. );
  158. KSTATUS
  159. Rtlw81pWriteLlt (
  160. PRTLW81_DEVICE Device,
  161. ULONG Address,
  162. ULONG Data
  163. );
  164. KSTATUS
  165. Rtlw81pWriteData (
  166. PRTLW81_DEVICE Device,
  167. USHORT Address,
  168. PVOID Data,
  169. ULONG DataLength
  170. );
  171. KSTATUS
  172. Rtlw81pReadData (
  173. PRTLW81_DEVICE Device,
  174. USHORT Address,
  175. PVOID Data,
  176. ULONG DataLength
  177. );
  178. VOID
  179. Rtlw81pWriteRegister (
  180. PRTLW81_DEVICE Device,
  181. USHORT Register,
  182. ULONG Data,
  183. ULONG DataLength
  184. );
  185. ULONG
  186. Rtlw81pReadRegister (
  187. PRTLW81_DEVICE Device,
  188. USHORT Register,
  189. ULONG DataLength
  190. );
  191. UCHAR
  192. Rtlw81pEfuseRead8 (
  193. PRTLW81_DEVICE Device,
  194. USHORT Address
  195. );
  196. VOID
  197. Rtlw81pWriteRfRegister (
  198. PRTLW81_DEVICE Device,
  199. ULONG Chain,
  200. ULONG RfRegister,
  201. ULONG Data
  202. );
  203. ULONG
  204. Rtlw81pReadRfRegister (
  205. PRTLW81_DEVICE Device,
  206. ULONG Chain,
  207. ULONG RfRegister
  208. );
  209. KSTATUS
  210. Rtlw81pSendFirmwareCommand (
  211. PRTLW81_DEVICE Device,
  212. UCHAR CommandId,
  213. PVOID Message,
  214. ULONG MessageLength
  215. );
  216. KSTATUS
  217. Rtlw81pSubmitBulkInTransfers (
  218. PRTLW81_DEVICE Device
  219. );
  220. VOID
  221. Rtlw81pCancelBulkInTransfers (
  222. PRTLW81_DEVICE Device
  223. );
  224. PRTLW81_BULK_OUT_TRANSFER
  225. Rtlw81pAllocateBulkOutTransfer (
  226. PRTLW81_DEVICE Device,
  227. RTLW81_BULK_OUT_TYPE Type
  228. );
  229. VOID
  230. Rtlw81pFreeBulkOutTransfer (
  231. PRTLW81_BULK_OUT_TRANSFER Transfer
  232. );
  233. VOID
  234. Rtlw81pBulkOutTransferCompletion (
  235. PUSB_TRANSFER Transfer
  236. );
  237. VOID
  238. Rtlw81pSetLed (
  239. PRTLW81_DEVICE Device,
  240. BOOL Enable
  241. );
  242. KSTATUS
  243. Rtlw81pGetRssi (
  244. PRTLW81_DEVICE Device,
  245. PVOID PhyStatus,
  246. ULONG PhyStatusSize,
  247. ULONG Rate,
  248. PLONG Rssi
  249. );
  250. //
  251. // -------------------------------------------------------------------- Globals
  252. //
  253. USHORT RtlwDefaultMacRegisters[] = {
  254. 0x420, 0x423, 0x430, 0x431, 0x432, 0x433, 0x434, 0x435, 0x436, 0x437,
  255. 0x438, 0x439, 0x43a, 0x43b, 0x43c, 0x43d, 0x43e, 0x43f, 0x440, 0x441,
  256. 0x442, 0x444, 0x445, 0x446, 0x447, 0x458, 0x459, 0x45a, 0x45b, 0x460,
  257. 0x461, 0x462, 0x463, 0x4c8, 0x4c9, 0x4cc, 0x4cd, 0x4ce, 0x500, 0x501,
  258. 0x502, 0x503, 0x504, 0x505, 0x506, 0x507, 0x508, 0x509, 0x50a, 0x50b,
  259. 0x50c, 0x50d, 0x50e, 0x50f, 0x512, 0x514, 0x515, 0x516, 0x517, 0x51a,
  260. 0x524, 0x525, 0x546, 0x547, 0x550, 0x551, 0x559, 0x55a, 0x55d, 0x605,
  261. 0x608, 0x609, 0x652, 0x63c, 0x63d, 0x63e, 0x63f, 0x66e, 0x700, 0x701,
  262. 0x702, 0x703, 0x708, 0x709, 0x70a, 0x70b
  263. };
  264. UCHAR RtlwDefaultMacValues[] = {
  265. 0x80, 0x00, 0x00, 0x00, 0x00, 0x01, 0x04, 0x05, 0x06, 0x07,
  266. 0x00, 0x00, 0x00, 0x01, 0x04, 0x05, 0x06, 0x07, 0x5d, 0x01,
  267. 0x00, 0x15, 0xf0, 0x0f, 0x00, 0x41, 0xa8, 0x72, 0xb9, 0x66,
  268. 0x66, 0x08, 0x03, 0xff, 0x08, 0xff, 0xff, 0x01, 0x26, 0xa2,
  269. 0x2f, 0x00, 0x28, 0xa3, 0x5e, 0x00, 0x2b, 0xa4, 0x5e, 0x00,
  270. 0x4f, 0xa4, 0x00, 0x00, 0x1c, 0x0a, 0x10, 0x0a, 0x10, 0x16,
  271. 0x0f, 0x4f, 0x40, 0x00, 0x10, 0x10, 0x02, 0x02, 0xff, 0x30,
  272. 0x0e, 0x2a, 0x20, 0x0a, 0x0e, 0x0a, 0x0e, 0x05, 0x21, 0x43,
  273. 0x65, 0x87, 0x21, 0x43, 0x65, 0x87
  274. };
  275. USHORT Rtlw8188eMacRegisters[] = {
  276. 0x026, 0x027, 0x040, 0x428, 0x429, 0x430, 0x431, 0x432, 0x433, 0x434,
  277. 0x435, 0x436, 0x437, 0x438, 0x439, 0x43a, 0x43b, 0x43c, 0x43d, 0x43e,
  278. 0x43f, 0x440, 0x441, 0x442, 0x444, 0x445, 0x446, 0x447, 0x458, 0x459,
  279. 0x45a, 0x45b, 0x460, 0x461, 0x480, 0x4c8, 0x4c9, 0x4cc, 0x4cd, 0x4ce,
  280. 0x4d3, 0x500, 0x501, 0x502, 0x503, 0x504, 0x505, 0x506, 0x507, 0x508,
  281. 0x509, 0x50a, 0x50b, 0x50c, 0x50d, 0x50e, 0x50f, 0x512, 0x514, 0x516,
  282. 0x525, 0x550, 0x551, 0x559, 0x55d, 0x605, 0x608, 0x609, 0x620, 0x621,
  283. 0x622, 0x623, 0x624, 0x625, 0x626, 0x627, 0x652, 0x63c, 0x63d, 0x63e,
  284. 0x63f, 0x640, 0x66e, 0x700, 0x701, 0x702, 0x703, 0x708, 0x709, 0x70a,
  285. 0x70b
  286. };
  287. UCHAR Rtlw8188eMacValues[] = {
  288. 0x41, 0x35, 0x00, 0x0a, 0x10, 0x00, 0x01, 0x02, 0x04, 0x05,
  289. 0x06, 0x07, 0x08, 0x00, 0x00, 0x01, 0x02, 0x04, 0x05, 0x06,
  290. 0x07, 0x5d, 0x01, 0x00, 0x15, 0xf0, 0x0f, 0x00, 0x41, 0xa8,
  291. 0x72, 0xb9, 0x66, 0x66, 0x08, 0xff, 0x08, 0xff, 0xff, 0x01,
  292. 0x01, 0x26, 0xa2, 0x2f, 0x00, 0x28, 0xa3, 0x5e, 0x00, 0x2b,
  293. 0xa4, 0x5e, 0x00, 0x4f, 0xa4, 0x00, 0x00, 0x1c, 0x0a, 0x0a,
  294. 0x4f, 0x10, 0x10, 0x02, 0xff, 0x30, 0x0e, 0x2a, 0xff, 0xff,
  295. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x20, 0x0a, 0x0a, 0x0e,
  296. 0x0e, 0x40, 0x05, 0x21, 0x43, 0x65, 0x87, 0x21, 0x43, 0x65,
  297. 0x87
  298. };
  299. //
  300. // Store the device specific arrays of BB initialization registers.
  301. //
  302. USHORT RtlwDefaultBbRegisters[] = {
  303. 0x024, 0x028, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 0x81c,
  304. 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 0x840, 0x844,
  305. 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 0x860, 0x864, 0x868, 0x86c,
  306. 0x870, 0x874, 0x878, 0x87c, 0x880, 0x884, 0x888, 0x88c, 0x890, 0x894,
  307. 0x898, 0x89c, 0x900, 0x904, 0x908, 0x90c, 0xa00, 0xa04, 0xa08, 0xa0c,
  308. 0xa10, 0xa14, 0xa18, 0xa1c, 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74,
  309. 0xc00, 0xc04, 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20, 0xc24,
  310. 0xc28, 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48, 0xc4c,
  311. 0xc50, 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70, 0xc74,
  312. 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98, 0xc9c,
  313. 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 0xcc0, 0xcc4,
  314. 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 0xce0, 0xce4, 0xce8, 0xcec,
  315. 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 0xd14, 0xd18, 0xd2c, 0xd30, 0xd34,
  316. 0xd38, 0xd3c, 0xd40, 0xd44, 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58, 0xd5c,
  317. 0xd60, 0xd64, 0xd68, 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 0xe04, 0xe08,
  318. 0xe10, 0xe14, 0xe18, 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c, 0xe40,
  319. 0xe44, 0xe48, 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68, 0xe6c,
  320. 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0, 0xed4,
  321. 0xed8, 0xedc, 0xee0, 0xeec, 0xf14, 0xf4c, 0xf00
  322. };
  323. USHORT Rtlw8188euBbRegisters[] = {
  324. 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818, 0x81c, 0x820, 0x824,
  325. 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 0x840, 0x844, 0x848, 0x84c,
  326. 0x850, 0x854, 0x858, 0x85c, 0x860, 0x864, 0x868, 0x86c, 0x870, 0x874,
  327. 0x878, 0x87c, 0x880, 0x884, 0x888, 0x88c, 0x890, 0x894, 0x898, 0x89c,
  328. 0x900, 0x904, 0x908, 0x90c, 0x910, 0x914, 0xa00, 0xa04, 0xa08, 0xa0c,
  329. 0xa10, 0xa14, 0xa18, 0xa1c, 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70, 0xa74,
  330. 0xa78, 0xa7c, 0xa80, 0xb2c, 0xc00, 0xc04, 0xc08, 0xc0c, 0xc10, 0xc14,
  331. 0xc18, 0xc1c, 0xc20, 0xc24, 0xc28, 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c,
  332. 0xc40, 0xc44, 0xc48, 0xc4c, 0xc50, 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64,
  333. 0xc68, 0xc6c, 0xc70, 0xc74, 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c,
  334. 0xc90, 0xc94, 0xc98, 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4,
  335. 0xcb8, 0xcbc, 0xcc0, 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc,
  336. 0xce0, 0xce4, 0xce8, 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 0xd14,
  337. 0xd18, 0xd2c, 0xd30, 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 0xd48, 0xd4c,
  338. 0xd50, 0xd54, 0xd58, 0xd5c, 0xd60, 0xd64, 0xd68, 0xd6c, 0xd70, 0xd74,
  339. 0xd78, 0xe00, 0xe04, 0xe08, 0xe10, 0xe14, 0xe18, 0xe1c, 0xe28, 0xe30,
  340. 0xe34, 0xe38, 0xe3c, 0xe40, 0xe44, 0xe48, 0xe4c, 0xe50, 0xe54, 0xe58,
  341. 0xe5c, 0xe60, 0xe68, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84,
  342. 0xe88, 0xe8c, 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xee8, 0xeec, 0xf14,
  343. 0xf4c, 0xf00
  344. };
  345. USHORT Rtlw8188ruBbRegisters[] = {
  346. 0x024, 0x028, 0x040, 0x800, 0x804, 0x808, 0x80c, 0x810, 0x814, 0x818,
  347. 0x81c, 0x820, 0x824, 0x828, 0x82c, 0x830, 0x834, 0x838, 0x83c, 0x840,
  348. 0x844, 0x848, 0x84c, 0x850, 0x854, 0x858, 0x85c, 0x860, 0x864, 0x868,
  349. 0x86c, 0x870, 0x874, 0x878, 0x87c, 0x880, 0x884, 0x888, 0x88c, 0x890,
  350. 0x894, 0x898, 0x89c, 0x900, 0x904, 0x908, 0x90c, 0xa00, 0xa04, 0xa08,
  351. 0xa0c, 0xa10, 0xa14, 0xa18, 0xa1c, 0xa20, 0xa24, 0xa28, 0xa2c, 0xa70,
  352. 0xa74, 0xc00, 0xc04, 0xc08, 0xc0c, 0xc10, 0xc14, 0xc18, 0xc1c, 0xc20,
  353. 0xc24, 0xc28, 0xc2c, 0xc30, 0xc34, 0xc38, 0xc3c, 0xc40, 0xc44, 0xc48,
  354. 0xc4c, 0xc50, 0xc54, 0xc58, 0xc5c, 0xc60, 0xc64, 0xc68, 0xc6c, 0xc70,
  355. 0xc74, 0xc78, 0xc7c, 0xc80, 0xc84, 0xc88, 0xc8c, 0xc90, 0xc94, 0xc98,
  356. 0xc9c, 0xca0, 0xca4, 0xca8, 0xcac, 0xcb0, 0xcb4, 0xcb8, 0xcbc, 0xcc0,
  357. 0xcc4, 0xcc8, 0xccc, 0xcd0, 0xcd4, 0xcd8, 0xcdc, 0xce0, 0xce4, 0xce8,
  358. 0xcec, 0xd00, 0xd04, 0xd08, 0xd0c, 0xd10, 0xd14, 0xd18, 0xd2c, 0xd30,
  359. 0xd34, 0xd38, 0xd3c, 0xd40, 0xd44, 0xd48, 0xd4c, 0xd50, 0xd54, 0xd58,
  360. 0xd5c, 0xd60, 0xd64, 0xd68, 0xd6c, 0xd70, 0xd74, 0xd78, 0xe00, 0xe04,
  361. 0xe08, 0xe10, 0xe14, 0xe18, 0xe1c, 0xe28, 0xe30, 0xe34, 0xe38, 0xe3c,
  362. 0xe40, 0xe44, 0xe48, 0xe4c, 0xe50, 0xe54, 0xe58, 0xe5c, 0xe60, 0xe68,
  363. 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, 0xed0,
  364. 0xed4, 0xed8, 0xedc, 0xee0, 0xeec, 0xee8, 0xf14, 0xf4c, 0xf00
  365. };
  366. //
  367. // Store the device specific arrays of BB initializationvalues.
  368. //
  369. ULONG Rtlw8188euBbValues[] = {
  370. 0x80040000, 0x00000003, 0x0000fc00, 0x0000000a, 0x10001331,
  371. 0x020c3d10, 0x02200385, 0x00000000, 0x01000100, 0x00390204,
  372. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  373. 0x00000000, 0x00010000, 0x00000000, 0x00000000, 0x00000000,
  374. 0x00000000, 0x00000000, 0x569a11a9, 0x01000014, 0x66f60110,
  375. 0x061f0649, 0x00000000, 0x27272700, 0x07000760, 0x25004000,
  376. 0x00000808, 0x00000000, 0xb0000c1c, 0x00000001, 0x00000000,
  377. 0xccc000c0, 0x00000800, 0xfffffffe, 0x40302010, 0x00706050,
  378. 0x00000000, 0x00000023, 0x00000000, 0x81121111, 0x00000002,
  379. 0x00000201, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e7f120f,
  380. 0x9500bb78, 0x1114d028, 0x00881117, 0x89140f00, 0x1a1b0000,
  381. 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007,
  382. 0x00000900, 0x225b0606, 0x218075b1, 0x80000000, 0x48071d40,
  383. 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000, 0x40000100,
  384. 0x08800000, 0x40000100, 0x00000000, 0x00000000, 0x00000000,
  385. 0x00000000, 0x69e9ac47, 0x469652af, 0x49795994, 0x0a97971c,
  386. 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f, 0x69553420,
  387. 0x43bc0094, 0x00013169, 0x00250492, 0x00000000, 0x7112848b,
  388. 0x47c00bff, 0x00000036, 0x2c7f000d, 0x020610db, 0x0000001f,
  389. 0x00b91612, 0x390000e4, 0x20f60000, 0x40000100, 0x20200000,
  390. 0x00091521, 0x00000000, 0x00121820, 0x00007f7f, 0x00000000,
  391. 0x000300a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  392. 0x00000000, 0x28000000, 0x00000000, 0x00000000, 0x00000000,
  393. 0x00000000, 0x00000000, 0x00000000, 0x64b22427, 0x00766932,
  394. 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c, 0x00000740,
  395. 0x00020401, 0x0000907f, 0x20010201, 0xa0633333, 0x3333bc43,
  396. 0x7a8f5b6f, 0xcc979975, 0x00000000, 0x80608000, 0x00000000,
  397. 0x00127353, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  398. 0x6437140a, 0x00000000, 0x00000282, 0x30032064, 0x4653de68,
  399. 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e, 0x322c2220,
  400. 0x000e3c24, 0x2d2d2d2d, 0x2d2d2d2d, 0x0390272d, 0x2d2d2d2d,
  401. 0x2d2d2d2d, 0x2d2d2d2d, 0x2d2d2d2d, 0x00000000, 0x1000dc1f,
  402. 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00, 0x01004800,
  403. 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f, 0x02140102,
  404. 0x28160d05, 0x00000008, 0x001b25a4, 0x00c00014, 0x00c00014,
  405. 0x01000014, 0x01000014, 0x01000014, 0x01000014, 0x00c00014,
  406. 0x01000014, 0x00c00014, 0x00c00014, 0x00c00014, 0x00c00014,
  407. 0x00000014, 0x00000014, 0x21555448, 0x01c00014, 0x00000003,
  408. 0x00000000, 0x00000300
  409. };
  410. ULONG Rtlw8188ceBbValues[] = {
  411. 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00,
  412. 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000,
  413. 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000,
  414. 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000,
  415. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a,
  416. 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200,
  417. 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070,
  418. 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe,
  419. 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000,
  420. 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f,
  421. 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000,
  422. 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007,
  423. 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000,
  424. 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000,
  425. 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994,
  426. 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f,
  427. 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000,
  428. 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db,
  429. 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100,
  430. 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f,
  431. 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000,
  432. 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000,
  433. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427,
  434. 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c,
  435. 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333,
  436. 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000,
  437. 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000,
  438. 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064,
  439. 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e,
  440. 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a,
  441. 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000,
  442. 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00,
  443. 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f,
  444. 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0,
  445. 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0,
  446. 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0,
  447. 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003,
  448. 0x00000000, 0x00000300
  449. };
  450. ULONG Rtlw8188cuBbValues[] = {
  451. 0x0011800d, 0x00ffdb83, 0x80040000, 0x00000001, 0x0000fc00,
  452. 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000,
  453. 0x01000100, 0x00390004, 0x00000000, 0x00000000, 0x00000000,
  454. 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000,
  455. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x569a569a,
  456. 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000, 0x32323200,
  457. 0x07000700, 0x22004000, 0x00000808, 0x00000000, 0xc0083070,
  458. 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800, 0xfffffffe,
  459. 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000,
  460. 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f,
  461. 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000,
  462. 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007,
  463. 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c, 0x08800000,
  464. 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000,
  465. 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994,
  466. 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f,
  467. 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000,
  468. 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db,
  469. 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100,
  470. 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f,
  471. 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000,
  472. 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000,
  473. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427,
  474. 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c,
  475. 0x00080740, 0x00020401, 0x0000907f, 0x20010201, 0xa0633333,
  476. 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000,
  477. 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000,
  478. 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064,
  479. 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e,
  480. 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a,
  481. 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000,
  482. 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00,
  483. 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f,
  484. 0x02140102, 0x28160d05, 0x00000008, 0x001b25a4, 0x631b25a0,
  485. 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0,
  486. 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0, 0x631b25a0,
  487. 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0, 0x00000003,
  488. 0x00000000, 0x00000300
  489. };
  490. ULONG Rtlw8188ruBbValues[] = {
  491. 0x0011800d, 0x00ffdb83, 0x000c0004, 0x80040000, 0x00000001,
  492. 0x0000fc00, 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385,
  493. 0x00000000, 0x01000100, 0x00390204, 0x00000000, 0x00000000,
  494. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010000,
  495. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  496. 0x569a569a, 0x001b25a4, 0x66e60230, 0x061f0130, 0x00000000,
  497. 0x32323200, 0x03000300, 0x22004000, 0x00000808, 0x00ffc3f1,
  498. 0xc0083070, 0x000004d5, 0x00000000, 0xccc000c0, 0x00000800,
  499. 0xfffffffe, 0x40302010, 0x00706050, 0x00000000, 0x00000023,
  500. 0x00000000, 0x81121111, 0x00d047c8, 0x80ff000c, 0x8c838300,
  501. 0x2e68120f, 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00,
  502. 0x15160000, 0x070b0f12, 0x00000104, 0x00d30000, 0x101fbf00,
  503. 0x00000007, 0x48071d40, 0x03a05611, 0x000000e4, 0x6c6c6c6c,
  504. 0x08800000, 0x40000100, 0x08800000, 0x40000100, 0x00000000,
  505. 0x00000000, 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf,
  506. 0x49795994, 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107,
  507. 0x007f037f, 0x6954342e, 0x43bc0094, 0x6954342f, 0x433c0094,
  508. 0x00000000, 0x5116848b, 0x47c00bff, 0x00000036, 0x2c56000d,
  509. 0x018610db, 0x0000001f, 0x00b91612, 0x24000090, 0x20f60000,
  510. 0x24000090, 0x20200000, 0x00121820, 0x00000000, 0x00121820,
  511. 0x00007f7f, 0x00000000, 0x00000080, 0x00000000, 0x00000000,
  512. 0x00000000, 0x00000000, 0x00000000, 0x28000000, 0x00000000,
  513. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
  514. 0x64b22427, 0x00766932, 0x00222222, 0x00000000, 0x37644302,
  515. 0x2f97d40c, 0x00080740, 0x00020401, 0x0000907f, 0x20010201,
  516. 0xa0633333, 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000,
  517. 0x80608000, 0x00000000, 0x00027293, 0x00000000, 0x00000000,
  518. 0x00000000, 0x00000000, 0x6437140a, 0x00000000, 0x00000000,
  519. 0x30032064, 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16,
  520. 0x1812362e, 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a,
  521. 0x03902a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a,
  522. 0x00000000, 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2,
  523. 0x01007c00, 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f,
  524. 0x10008c1f, 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4,
  525. 0x631b25a0, 0x631b25a0, 0x081b25a0, 0x081b25a0, 0x081b25a0,
  526. 0x081b25a0, 0x631b25a0, 0x081b25a0, 0x631b25a0, 0x631b25a0,
  527. 0x631b25a0, 0x631b25a0, 0x001b25a0, 0x001b25a0, 0x6b1b25a0,
  528. 0x31555448, 0x00000003, 0x00000000, 0x00000300
  529. };
  530. ULONG Rtlw8192ceBbValues[] = {
  531. 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00,
  532. 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000,
  533. 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727,
  534. 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000,
  535. 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a,
  536. 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27,
  537. 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070,
  538. 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe,
  539. 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000,
  540. 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f,
  541. 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000,
  542. 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007,
  543. 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000,
  544. 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000,
  545. 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994,
  546. 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f,
  547. 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000,
  548. 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x018610db,
  549. 0x0000001f, 0x00b91612, 0x40000100, 0x20f60000, 0x40000100,
  550. 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f,
  551. 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000,
  552. 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000,
  553. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427,
  554. 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c,
  555. 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333,
  556. 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000,
  557. 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000,
  558. 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064,
  559. 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e,
  560. 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a,
  561. 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000,
  562. 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00,
  563. 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f,
  564. 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4,
  565. 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4,
  566. 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4,
  567. 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003,
  568. 0x00000000, 0x00000300
  569. };
  570. ULONG Rtlw8192cuBbValues[] = {
  571. 0x0011800d, 0x00ffdb83, 0x80040002, 0x00000003, 0x0000fc00,
  572. 0x0000000a, 0x10005388, 0x020c3d10, 0x02200385, 0x00000000,
  573. 0x01000100, 0x00390004, 0x01000100, 0x00390004, 0x27272727,
  574. 0x27272727, 0x27272727, 0x27272727, 0x00010000, 0x00010000,
  575. 0x27272727, 0x27272727, 0x00000000, 0x00000000, 0x569a569a,
  576. 0x0c1b25a4, 0x66e60230, 0x061f0130, 0x27272727, 0x2b2b2b27,
  577. 0x07000700, 0x22184000, 0x08080808, 0x00000000, 0xc0083070,
  578. 0x000004d5, 0x00000000, 0xcc0000c0, 0x00000800, 0xfffffffe,
  579. 0x40302010, 0x00706050, 0x00000000, 0x00000023, 0x00000000,
  580. 0x81121313, 0x00d047c8, 0x80ff000c, 0x8c838300, 0x2e68120f,
  581. 0x9500bb78, 0x11144028, 0x00881117, 0x89140f00, 0x1a1b0000,
  582. 0x090e1317, 0x00000204, 0x00d30000, 0x101fbf00, 0x00000007,
  583. 0x48071d40, 0x03a05633, 0x000000e4, 0x6c6c6c6c, 0x08800000,
  584. 0x40000100, 0x08800000, 0x40000100, 0x00000000, 0x00000000,
  585. 0x00000000, 0x00000000, 0x69e9ac44, 0x469652cf, 0x49795994,
  586. 0x0a97971c, 0x1f7c403f, 0x000100b7, 0xec020107, 0x007f037f,
  587. 0x6954341e, 0x43bc0094, 0x6954341e, 0x433c0094, 0x00000000,
  588. 0x5116848b, 0x47c00bff, 0x00000036, 0x2c7f000d, 0x0186115b,
  589. 0x0000001f, 0x00b99612, 0x40000100, 0x20f60000, 0x40000100,
  590. 0x20200000, 0x00121820, 0x00000000, 0x00121820, 0x00007f7f,
  591. 0x00000000, 0x00000080, 0x00000000, 0x00000000, 0x00000000,
  592. 0x00000000, 0x00000000, 0x28000000, 0x00000000, 0x00000000,
  593. 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x64b22427,
  594. 0x00766932, 0x00222222, 0x00000000, 0x37644302, 0x2f97d40c,
  595. 0x00080740, 0x00020403, 0x0000907f, 0x20010201, 0xa0633333,
  596. 0x3333bc43, 0x7a8f5b6b, 0xcc979975, 0x00000000, 0x80608000,
  597. 0x00000000, 0x00027293, 0x00000000, 0x00000000, 0x00000000,
  598. 0x00000000, 0x6437140a, 0x00000000, 0x00000000, 0x30032064,
  599. 0x4653de68, 0x04518a3c, 0x00002101, 0x2a201c16, 0x1812362e,
  600. 0x322c2220, 0x000e3c24, 0x2a2a2a2a, 0x2a2a2a2a, 0x03902a2a,
  601. 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x2a2a2a2a, 0x00000000,
  602. 0x1000dc1f, 0x10008c1f, 0x02140102, 0x681604c2, 0x01007c00,
  603. 0x01004800, 0xfb000000, 0x000028d1, 0x1000dc1f, 0x10008c1f,
  604. 0x02140102, 0x28160d05, 0x00000010, 0x001b25a4, 0x63db25a4,
  605. 0x63db25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4, 0x0c1b25a4,
  606. 0x63db25a4, 0x0c1b25a4, 0x63db25a4, 0x63db25a4, 0x63db25a4,
  607. 0x63db25a4, 0x001b25a4, 0x001b25a4, 0x6fdb25a4, 0x00000003,
  608. 0x00000000, 0x00000300
  609. };
  610. //
  611. // Store the device specific arrays of AGC initialization values.
  612. //
  613. ULONG Rtlw8188euAgcValues[] = {
  614. 0xfb000001, 0xfb010001, 0xfb020001, 0xfb030001, 0xfb040001, 0xfb050001,
  615. 0xfa060001, 0xf9070001, 0xf8080001, 0xf7090001, 0xf60a0001, 0xf50b0001,
  616. 0xf40c0001, 0xf30d0001, 0xf20e0001, 0xf10f0001, 0xf0100001, 0xef110001,
  617. 0xee120001, 0xed130001, 0xec140001, 0xeb150001, 0xea160001, 0xe9170001,
  618. 0xe8180001, 0xe7190001, 0xe61a0001, 0xe51b0001, 0xe41c0001, 0xe31d0001,
  619. 0xe21e0001, 0xe11f0001, 0x8a200001, 0x89210001, 0x88220001, 0x87230001,
  620. 0x86240001, 0x85250001, 0x84260001, 0x83270001, 0x82280001, 0x6b290001,
  621. 0x6a2a0001, 0x692b0001, 0x682c0001, 0x672d0001, 0x662e0001, 0x652f0001,
  622. 0x64300001, 0x63310001, 0x62320001, 0x61330001, 0x46340001, 0x45350001,
  623. 0x44360001, 0x43370001, 0x42380001, 0x41390001, 0x403a0001, 0x403b0001,
  624. 0x403c0001, 0x403d0001, 0x403e0001, 0x403f0001, 0xfb400001, 0xfb410001,
  625. 0xfb420001, 0xfb430001, 0xfb440001, 0xfb450001, 0xfb460001, 0xfb470001,
  626. 0xfb480001, 0xfa490001, 0xf94a0001, 0xf84B0001, 0xf74c0001, 0xf64d0001,
  627. 0xf54e0001, 0xf44f0001, 0xf3500001, 0xf2510001, 0xf1520001, 0xf0530001,
  628. 0xef540001, 0xee550001, 0xed560001, 0xec570001, 0xeb580001, 0xea590001,
  629. 0xe95a0001, 0xe85b0001, 0xe75c0001, 0xe65d0001, 0xe55e0001, 0xe45f0001,
  630. 0xe3600001, 0xe2610001, 0xc3620001, 0xc2630001, 0xc1640001, 0x8b650001,
  631. 0x8a660001, 0x89670001, 0x88680001, 0x87690001, 0x866a0001, 0x856b0001,
  632. 0x846c0001, 0x676d0001, 0x666e0001, 0x656f0001, 0x64700001, 0x63710001,
  633. 0x62720001, 0x61730001, 0x60740001, 0x46750001, 0x45760001, 0x44770001,
  634. 0x43780001, 0x42790001, 0x417a0001, 0x407b0001, 0x407c0001, 0x407d0001,
  635. 0x407e0001, 0x407f0001
  636. };
  637. ULONG Rtlw8188ruAgcValues[] = {
  638. 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 0x7b050001,
  639. 0x7b060001, 0x7b070001, 0x7b080001, 0x7a090001, 0x790a0001, 0x780b0001,
  640. 0x770c0001, 0x760d0001, 0x750e0001, 0x740f0001, 0x73100001, 0x72110001,
  641. 0x71120001, 0x70130001, 0x6f140001, 0x6e150001, 0x6d160001, 0x6c170001,
  642. 0x6b180001, 0x6a190001, 0x691a0001, 0x681b0001, 0x671c0001, 0x661d0001,
  643. 0x651e0001, 0x641f0001, 0x63200001, 0x62210001, 0x61220001, 0x60230001,
  644. 0x46240001, 0x45250001, 0x44260001, 0x43270001, 0x42280001, 0x41290001,
  645. 0x402a0001, 0x262b0001, 0x252c0001, 0x242d0001, 0x232e0001, 0x222f0001,
  646. 0x21300001, 0x20310001, 0x06320001, 0x05330001, 0x04340001, 0x03350001,
  647. 0x02360001, 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001,
  648. 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 0x7b410001,
  649. 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 0x7b460001, 0x7b470001,
  650. 0x7b480001, 0x7a490001, 0x794a0001, 0x784b0001, 0x774c0001, 0x764d0001,
  651. 0x754e0001, 0x744f0001, 0x73500001, 0x72510001, 0x71520001, 0x70530001,
  652. 0x6f540001, 0x6e550001, 0x6d560001, 0x6c570001, 0x6b580001, 0x6a590001,
  653. 0x695a0001, 0x685b0001, 0x675c0001, 0x665d0001, 0x655e0001, 0x645f0001,
  654. 0x63600001, 0x62610001, 0x61620001, 0x60630001, 0x46640001, 0x45650001,
  655. 0x44660001, 0x43670001, 0x42680001, 0x41690001, 0x406a0001, 0x266b0001,
  656. 0x256c0001, 0x246d0001, 0x236e0001, 0x226f0001, 0x21700001, 0x20710001,
  657. 0x06720001, 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001,
  658. 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 0x007d0001,
  659. 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 0x3802001e, 0x3803001e,
  660. 0x3804001e, 0x3805001e, 0x3806001e, 0x3807001e, 0x3808001e, 0x3c09001e,
  661. 0x3e0a001e, 0x400b001e, 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e,
  662. 0x5210001e, 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e,
  663. 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 0x621b001e,
  664. 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e
  665. };
  666. ULONG RtlwDefaultAgcValues[] = {
  667. 0x7b000001, 0x7b010001, 0x7b020001, 0x7b030001, 0x7b040001, 0x7b050001,
  668. 0x7a060001, 0x79070001, 0x78080001, 0x77090001, 0x760a0001, 0x750b0001,
  669. 0x740c0001, 0x730d0001, 0x720e0001, 0x710f0001, 0x70100001, 0x6f110001,
  670. 0x6e120001, 0x6d130001, 0x6c140001, 0x6b150001, 0x6a160001, 0x69170001,
  671. 0x68180001, 0x67190001, 0x661a0001, 0x651b0001, 0x641c0001, 0x631d0001,
  672. 0x621e0001, 0x611f0001, 0x60200001, 0x49210001, 0x48220001, 0x47230001,
  673. 0x46240001, 0x45250001, 0x44260001, 0x43270001, 0x42280001, 0x41290001,
  674. 0x402a0001, 0x262b0001, 0x252c0001, 0x242d0001, 0x232e0001, 0x222f0001,
  675. 0x21300001, 0x20310001, 0x06320001, 0x05330001, 0x04340001, 0x03350001,
  676. 0x02360001, 0x01370001, 0x00380001, 0x00390001, 0x003a0001, 0x003b0001,
  677. 0x003c0001, 0x003d0001, 0x003e0001, 0x003f0001, 0x7b400001, 0x7b410001,
  678. 0x7b420001, 0x7b430001, 0x7b440001, 0x7b450001, 0x7a460001, 0x79470001,
  679. 0x78480001, 0x77490001, 0x764a0001, 0x754b0001, 0x744c0001, 0x734d0001,
  680. 0x724e0001, 0x714f0001, 0x70500001, 0x6f510001, 0x6e520001, 0x6d530001,
  681. 0x6c540001, 0x6b550001, 0x6a560001, 0x69570001, 0x68580001, 0x67590001,
  682. 0x665a0001, 0x655b0001, 0x645c0001, 0x635d0001, 0x625e0001, 0x615f0001,
  683. 0x60600001, 0x49610001, 0x48620001, 0x47630001, 0x46640001, 0x45650001,
  684. 0x44660001, 0x43670001, 0x42680001, 0x41690001, 0x406a0001, 0x266b0001,
  685. 0x256c0001, 0x246d0001, 0x236e0001, 0x226f0001, 0x21700001, 0x20710001,
  686. 0x06720001, 0x05730001, 0x04740001, 0x03750001, 0x02760001, 0x01770001,
  687. 0x00780001, 0x00790001, 0x007a0001, 0x007b0001, 0x007c0001, 0x007d0001,
  688. 0x007e0001, 0x007f0001, 0x3800001e, 0x3801001e, 0x3802001e, 0x3803001e,
  689. 0x3804001e, 0x3805001e, 0x3806001e, 0x3807001e, 0x3808001e, 0x3c09001e,
  690. 0x3e0a001e, 0x400b001e, 0x440c001e, 0x480d001e, 0x4c0e001e, 0x500f001e,
  691. 0x5210001e, 0x5611001e, 0x5a12001e, 0x5e13001e, 0x6014001e, 0x6015001e,
  692. 0x6016001e, 0x6217001e, 0x6218001e, 0x6219001e, 0x621a001e, 0x621b001e,
  693. 0x621c001e, 0x621d001e, 0x621e001e, 0x621f001e
  694. };
  695. //
  696. // Store the RF chain 1 registers and values.
  697. //
  698. UCHAR RtlwDefaultRf1Registers[] = {
  699. 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b,
  700. 0x0c, 0x0d, 0x0e, 0x0f, 0x19, 0x1a, 0x1b, 0x1c,
  701. 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 0x24,
  702. 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2a,
  703. 0x2b, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b,
  704. 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b,
  705. 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b,
  706. 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b,
  707. 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b,
  708. 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b,
  709. 0x2c, 0x2a, 0x2b, 0x2b, 0x2c, 0x2a, 0x2b, 0x2b,
  710. 0x2c, 0x2a, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11,
  711. 0x10, 0x11, 0x10, 0x11, 0x10, 0x11, 0x10, 0x11,
  712. 0x12, 0x12, 0x12, 0x12, 0x13, 0x13, 0x13, 0x13,
  713. 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x14,
  714. 0x14, 0x14, 0x14, 0x15, 0x15, 0x15, 0x15, 0x16,
  715. 0x16, 0x16, 0x16, 0x00, 0x18, 0xfe, 0xfe, 0x1f,
  716. 0xfe, 0xfe, 0x1e, 0x1f, 0x00
  717. };
  718. UCHAR Rtlw8188euRf1Registers[] = {
  719. 0x00, 0x08, 0x18, 0x19, 0x1e, 0x1f, 0x2f, 0x3f,
  720. 0x42, 0x57, 0x58, 0x67, 0x83, 0xb0, 0xb1, 0xb2,
  721. 0xb4, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xbb, 0xbf,
  722. 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9,
  723. 0xca, 0xdf, 0xef, 0x51, 0x52, 0x53, 0x56, 0x35,
  724. 0x35, 0x35, 0x36, 0x36, 0x36, 0x36, 0xb6, 0x18,
  725. 0x5a, 0x19, 0x34, 0x34, 0x34, 0x34, 0x34, 0x34,
  726. 0x34, 0x34, 0x34, 0x34, 0x34, 0x00, 0x84, 0x86,
  727. 0x87, 0x8e, 0x8f, 0xef, 0x3b, 0x3b, 0x3b, 0x3b,
  728. 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b,
  729. 0x3b, 0x3b, 0x3b, 0x3b, 0xef, 0x00, 0x18, 0xfe,
  730. 0xfe, 0x1f, 0xfe, 0xfe, 0x1e, 0x1f, 0x00
  731. };
  732. ULONG Rtlw8188ceRf1Values[] = {
  733. 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 0x54867,
  734. 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 0x60a00, 0xfc378,
  735. 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 0x00000, 0x01558, 0x00060,
  736. 0x00483, 0x4f200, 0xec7d9, 0x577c0, 0x04783, 0x00001, 0x21334, 0x00000,
  737. 0x00054, 0x00001, 0x00808, 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333,
  738. 0x0000d, 0x00003, 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333,
  739. 0x0000d, 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333,
  740. 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 0x4b333,
  741. 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 0x0060a, 0x5b333,
  742. 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 0x0000c, 0x0060a, 0x6b333,
  743. 0x0000d, 0x0000d, 0x0060a, 0x73333, 0x0000d, 0x0000e, 0x0050b, 0x66666,
  744. 0x0001a, 0xe0000, 0x4000f, 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9,
  745. 0x3000f, 0xff500, 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100,
  746. 0x32000, 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f,
  747. 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 0x1944c,
  748. 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 0xcf424, 0xe0330,
  749. 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 0x00000, 0x00000, 0x80003,
  750. 0x00000, 0x00000, 0x44457, 0x80000, 0x30159
  751. };
  752. ULONG Rtlw8188cuRf1Values[] = {
  753. 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 0x54867,
  754. 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 0x60a00, 0xfc378,
  755. 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 0x00000, 0x01558, 0x00060,
  756. 0x00483, 0x4f000, 0xec7d9, 0x577c0, 0x04783, 0x00001, 0x21334, 0x00000,
  757. 0x00054, 0x00001, 0x00808, 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333,
  758. 0x0000d, 0x00003, 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333,
  759. 0x0000d, 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333,
  760. 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 0x4b333,
  761. 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 0x0060a, 0x5b333,
  762. 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 0x0000c, 0x0060a, 0x6b333,
  763. 0x0000d, 0x0000d, 0x0060a, 0x73333, 0x0000d, 0x0000e, 0x0050b, 0x66666,
  764. 0x0001a, 0xe0000, 0x4000f, 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9,
  765. 0x3000f, 0xff500, 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100,
  766. 0x32000, 0x71000, 0xb0000, 0xfc000, 0x287b3, 0x244b7, 0x204ab, 0x1c49f,
  767. 0x18493, 0x1429b, 0x10299, 0x0c29c, 0x081a0, 0x040ac, 0x00020, 0x1944c,
  768. 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 0xcf405, 0xe0330,
  769. 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 0x00000, 0x00000, 0x80003,
  770. 0x00000, 0x00000, 0x44457, 0x80000, 0x30159
  771. };
  772. ULONG Rtlw8188euRf1Values[] = {
  773. 0x30000, 0x84000, 0x00407, 0x00012, 0x80009, 0x00880, 0x1a060, 0x00000,
  774. 0x060c0, 0xd0000, 0xbe180, 0x01552, 0x00000, 0xff8fc, 0x54400, 0xccc19,
  775. 0x43003, 0x4953e, 0x1c718, 0x060ff, 0x80001, 0x40000, 0x00400, 0xc0000,
  776. 0x02400, 0x00009, 0x40c91, 0x99999, 0x000a3, 0x88820, 0x76c06, 0x00000,
  777. 0x80000, 0x00180, 0x001a0, 0x6b27d, 0x7e49d, 0x00073, 0x51ff3, 0x00086,
  778. 0x00186, 0x00286, 0x01c25, 0x09c25, 0x11c25, 0x19c25, 0x48538, 0x00c07,
  779. 0x4bd00, 0x739d0, 0x0adf3, 0x09df0, 0x08ded, 0x07dea, 0x06de7, 0x054ee,
  780. 0x044eb, 0x034e8, 0x0246b, 0x01468, 0x0006d, 0x30159, 0x68200, 0x000ce,
  781. 0x48a00, 0x65540, 0x88000, 0x020a0, 0xf02b0, 0xef7b0, 0xd4fb0, 0xcf060,
  782. 0xb0090, 0xa0080, 0x90080, 0x8f780, 0x722b0, 0x6f7b0, 0x54fb0, 0x4f060,
  783. 0x30090, 0x20080, 0x10080, 0x0f780, 0x000a0, 0x10159, 0x0f407, 0x00000,
  784. 0x00000, 0x80003, 0x00000, 0x00000, 0x00001, 0x80000, 0x33e60
  785. };
  786. ULONG Rtlw8188ruRf1Values[] = {
  787. 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb0, 0x54867,
  788. 0x8992e, 0x0e529, 0x39ce7, 0x00451, 0x00000, 0x00255, 0x60a00, 0xfc378,
  789. 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 0x0083c, 0x01558, 0x00060,
  790. 0x00483, 0x4f000, 0xec7d9, 0x977c0, 0x04783, 0x00001, 0x21334, 0x00000,
  791. 0x00054, 0x00001, 0x00808, 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333,
  792. 0x0000d, 0x00003, 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333,
  793. 0x0000d, 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333,
  794. 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 0x4b333,
  795. 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 0x0060a, 0x5b333,
  796. 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 0x0000c, 0x0060a, 0x6b333,
  797. 0x0000d, 0x0000d, 0x0060a, 0x73333, 0x0000d, 0x0000e, 0x0050b, 0x66666,
  798. 0x0001a, 0xe0000, 0x4000f, 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9,
  799. 0x3000f, 0xff500, 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100,
  800. 0xd8000, 0x90000, 0x51000, 0x12000, 0x28fb4, 0x24fa8, 0x207a4, 0x1c798,
  801. 0x183a4, 0x14398, 0x101a4, 0x0c198, 0x080a4, 0x04098, 0x00014, 0x1944c,
  802. 0x59444, 0x9944c, 0xd9444, 0x0f405, 0x4f405, 0x8f405, 0xcf405, 0xe0330,
  803. 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 0x00000, 0x00000, 0x80003,
  804. 0x00000, 0x00000, 0x44457, 0x80000, 0x30159
  805. };
  806. ULONG RtlwDefaultRf1Values[] = {
  807. 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 0x54867,
  808. 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x00000, 0x10255, 0x60a00, 0xfc378,
  809. 0xa1250, 0x4445f, 0x80001, 0x0b614, 0x6c000, 0x00000, 0x01558, 0x00060,
  810. 0x00483, 0x4f000, 0xec7d9, 0x577c0, 0x04783, 0x00001, 0x21334, 0x00000,
  811. 0x00054, 0x00001, 0x00808, 0x53333, 0x0000c, 0x00002, 0x00808, 0x5b333,
  812. 0x0000d, 0x00003, 0x00808, 0x63333, 0x0000d, 0x00004, 0x00808, 0x6b333,
  813. 0x0000d, 0x00005, 0x00808, 0x73333, 0x0000d, 0x00006, 0x00709, 0x5b333,
  814. 0x0000d, 0x00007, 0x00709, 0x63333, 0x0000d, 0x00008, 0x0060a, 0x4b333,
  815. 0x0000d, 0x00009, 0x0060a, 0x53333, 0x0000d, 0x0000a, 0x0060a, 0x5b333,
  816. 0x0000d, 0x0000b, 0x0060a, 0x63333, 0x0000d, 0x0000c, 0x0060a, 0x6b333,
  817. 0x0000d, 0x0000d, 0x0060a, 0x73333, 0x0000d, 0x0000e, 0x0050b, 0x66666,
  818. 0x0001a, 0xe0000, 0x4000f, 0xe31fc, 0x6000f, 0xff9f8, 0x2000f, 0x203f9,
  819. 0x3000f, 0xff500, 0x00000, 0x00000, 0x8000f, 0x3f100, 0x9000f, 0x23100,
  820. 0x32000, 0x71000, 0xb0000, 0xfc000, 0x287af, 0x244b7, 0x204ab, 0x1c49f,
  821. 0x18493, 0x14297, 0x10295, 0x0c298, 0x0819c, 0x040a8, 0x0001c, 0x1944c,
  822. 0x59444, 0x9944c, 0xd9444, 0x0f424, 0x4f424, 0x8f424, 0xcf424, 0xe0330,
  823. 0xa0330, 0x60330, 0x20330, 0x10159, 0x0f401, 0x00000, 0x00000, 0x80003,
  824. 0x00000, 0x00000, 0x44457, 0x80000, 0x30159
  825. };
  826. //
  827. // Store the RF chain 2 registers and values.
  828. //
  829. UCHAR RtlwDefaultRf2Registers[] = {
  830. 0x00, 0x01, 0x02, 0x03, 0x04, 0x09, 0x0a, 0x0b,
  831. 0x0c, 0x0d, 0x0e, 0x0f, 0x12, 0x12, 0x12, 0x12,
  832. 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
  833. 0x13, 0x13, 0x13, 0x14, 0x14, 0x14, 0x14, 0x15,
  834. 0x15, 0x15, 0x15, 0x16, 0x16, 0x16, 0x16
  835. };
  836. ULONG RtlwDefaultRf2Values[] = {
  837. 0x30159, 0x31284, 0x98000, 0x18c63, 0x210e7, 0x2044f, 0x1adb1, 0x54867,
  838. 0x8992e, 0x0e52c, 0x39ce7, 0x00451, 0x32000, 0x71000, 0xb0000, 0xfc000,
  839. 0x287af, 0x244b7, 0x204ab, 0x1c49f, 0x18493, 0x14297, 0x10295, 0x0c298,
  840. 0x0819c, 0x040a8, 0x0001c, 0x1944c, 0x59444, 0x9944c, 0xd9444, 0x0f424,
  841. 0x4f424, 0x8f424, 0xcf424, 0xe0330, 0xa0330, 0x60330, 0x20330
  842. };
  843. RTLW81_DEVICE_DATA Rtlw8188euDeviceData = {
  844. Rtlw8188euBbRegisters,
  845. Rtlw8188euBbValues,
  846. RTLW81_ARRAY_COUNT(Rtlw8188euBbRegisters),
  847. Rtlw8188euAgcValues,
  848. RTLW81_ARRAY_COUNT(Rtlw8188euAgcValues),
  849. {
  850. Rtlw8188euRf1Registers,
  851. NULL
  852. },
  853. {
  854. Rtlw8188euRf1Values,
  855. NULL
  856. },
  857. {
  858. RTLW81_ARRAY_COUNT(Rtlw8188euRf1Registers),
  859. 0
  860. }
  861. };
  862. RTLW81_DEVICE_DATA Rtlw8188ceDeviceData = {
  863. RtlwDefaultBbRegisters,
  864. Rtlw8188ceBbValues,
  865. RTLW81_ARRAY_COUNT(RtlwDefaultBbRegisters),
  866. RtlwDefaultAgcValues,
  867. RTLW81_ARRAY_COUNT(RtlwDefaultAgcValues),
  868. {
  869. RtlwDefaultRf1Registers,
  870. NULL
  871. },
  872. {
  873. Rtlw8188ceRf1Values,
  874. NULL
  875. },
  876. {
  877. RTLW81_ARRAY_COUNT(RtlwDefaultRf1Registers),
  878. 0
  879. }
  880. };
  881. RTLW81_DEVICE_DATA Rtlw8188ruDeviceData = {
  882. Rtlw8188ruBbRegisters,
  883. Rtlw8188ruBbValues,
  884. RTLW81_ARRAY_COUNT(Rtlw8188ruBbRegisters),
  885. Rtlw8188ruAgcValues,
  886. RTLW81_ARRAY_COUNT(Rtlw8188ruAgcValues),
  887. {
  888. RtlwDefaultRf1Registers,
  889. NULL
  890. },
  891. {
  892. Rtlw8188ruRf1Values,
  893. NULL
  894. },
  895. {
  896. RTLW81_ARRAY_COUNT(RtlwDefaultRf1Registers),
  897. 0
  898. }
  899. };
  900. RTLW81_DEVICE_DATA Rtlw8188cuDeviceData = {
  901. RtlwDefaultBbRegisters,
  902. Rtlw8188cuBbValues,
  903. RTLW81_ARRAY_COUNT(RtlwDefaultBbRegisters),
  904. RtlwDefaultAgcValues,
  905. RTLW81_ARRAY_COUNT(RtlwDefaultAgcValues),
  906. {
  907. RtlwDefaultRf1Registers,
  908. NULL
  909. },
  910. {
  911. Rtlw8188cuRf1Values,
  912. NULL
  913. },
  914. {
  915. RTLW81_ARRAY_COUNT(RtlwDefaultRf1Registers),
  916. 0
  917. }
  918. };
  919. RTLW81_DEVICE_DATA Rtlw8192ceDeviceData = {
  920. RtlwDefaultBbRegisters,
  921. Rtlw8192ceBbValues,
  922. RTLW81_ARRAY_COUNT(RtlwDefaultBbRegisters),
  923. RtlwDefaultAgcValues,
  924. RTLW81_ARRAY_COUNT(RtlwDefaultAgcValues),
  925. {
  926. RtlwDefaultRf1Registers,
  927. RtlwDefaultRf2Registers
  928. },
  929. {
  930. RtlwDefaultRf1Values,
  931. RtlwDefaultRf2Values
  932. },
  933. {
  934. RTLW81_ARRAY_COUNT(RtlwDefaultRf1Registers),
  935. RTLW81_ARRAY_COUNT(RtlwDefaultRf2Registers),
  936. }
  937. };
  938. RTLW81_DEVICE_DATA Rtlw8192cuDeviceData = {
  939. RtlwDefaultBbRegisters,
  940. Rtlw8192cuBbValues,
  941. RTLW81_ARRAY_COUNT(RtlwDefaultBbRegisters),
  942. RtlwDefaultAgcValues,
  943. RTLW81_ARRAY_COUNT(RtlwDefaultAgcValues),
  944. {
  945. RtlwDefaultRf1Registers,
  946. RtlwDefaultRf2Registers
  947. },
  948. {
  949. RtlwDefaultRf1Values,
  950. RtlwDefaultRf2Values
  951. },
  952. {
  953. RTLW81_ARRAY_COUNT(RtlwDefaultRf1Registers),
  954. RTLW81_ARRAY_COUNT(RtlwDefaultRf2Registers),
  955. }
  956. };
  957. RTLW81_DEFAULT_TRANSMIT_POWER_DATA Rtlw8188ruTransmitPowerData[] = {
  958. {
  959. {
  960. {
  961. 0x00, 0x00, 0x00, 0x00, 0x08, 0x08, 0x08, 0x06, 0x06, 0x04,
  962. 0x04, 0x00, 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00,
  963. 0x08, 0x06, 0x06, 0x04, 0x04, 0x02, 0x02, 0x00
  964. },
  965. {
  966. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  967. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  968. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  969. },
  970. {
  971. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  972. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  973. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  974. }
  975. }
  976. }
  977. };
  978. RTLW81_DEFAULT_TRANSMIT_POWER_DATA RtlwDefaultTransmitPowerData[] = {
  979. {
  980. {
  981. {
  982. 0x00, 0x00, 0x00, 0x00, 0x0c, 0x0c, 0x0c, 0x0a, 0x08, 0x06,
  983. 0x04, 0x02, 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02,
  984. 0x0e, 0x0d, 0x0c, 0x0a, 0x08, 0x06, 0x04, 0x02
  985. },
  986. {
  987. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  988. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  989. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  990. },
  991. {
  992. 0x00, 0x00, 0x00, 0x00, 0x04, 0x04, 0x04, 0x04, 0x04, 0x02,
  993. 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  994. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  995. }
  996. }
  997. },
  998. {
  999. {
  1000. {
  1001. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  1002. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  1003. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  1004. },
  1005. {
  1006. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  1007. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  1008. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  1009. },
  1010. {
  1011. 0x00, 0x00, 0x00, 0x00, 0x04, 0x04, 0x04, 0x04, 0x04, 0x02,
  1012. 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  1013. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  1014. }
  1015. }
  1016. }
  1017. };
  1018. RTLW81_8188E_TRANSMIT_POWER_DATA Rtlw8188eTransmitPowerData[] = {
  1019. {
  1020. {
  1021. {
  1022. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  1023. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  1024. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  1025. },
  1026. {
  1027. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  1028. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  1029. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  1030. },
  1031. {
  1032. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  1033. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  1034. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  1035. },
  1036. {
  1037. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  1038. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  1039. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  1040. },
  1041. {
  1042. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  1043. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  1044. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  1045. },
  1046. {
  1047. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  1048. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  1049. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  1050. }
  1051. }
  1052. }
  1053. };
  1054. BOOL Rtlw81DisablePacketDropping = FALSE;
  1055. LONG Rtlw81DefaultCckAgcReportOffsets[] = { 16, -12, -26, -46 };
  1056. //
  1057. // ------------------------------------------------------------------ Functions
  1058. //
  1059. KSTATUS
  1060. Rtlw81Send (
  1061. PVOID DeviceContext,
  1062. PNET_PACKET_LIST PacketList
  1063. )
  1064. /*++
  1065. Routine Description:
  1066. This routine sends data through the network.
  1067. Arguments:
  1068. DeviceContext - Supplies a pointer to the device context associated with
  1069. the link down which this data is to be sent.
  1070. PacketList - Supplies a pointer to a list of network packets to send. Data
  1071. in these packets may be modified by this routine, but must not be used
  1072. once this routine returns.
  1073. Return Value:
  1074. STATUS_SUCCESS if all packets were sent.
  1075. STATUS_RESOURCE_IN_USE if some or all of the packets were dropped due to
  1076. the hardware being backed up with too many packets to send.
  1077. Other failure codes indicate that none of the packets were sent.
  1078. --*/
  1079. {
  1080. RTLW81_BULK_OUT_TYPE BulkOutType;
  1081. USHORT Checksum;
  1082. ULONG DataRate;
  1083. ULONG DataSize;
  1084. PRTLW81_DEVICE Device;
  1085. PRTLW81_TRANSMIT_HEADER Header;
  1086. PUSHORT HeaderBuffer;
  1087. ULONG Index;
  1088. ULONG MacId;
  1089. PNET80211_FRAME_HEADER Net80211Header;
  1090. ULONG Net80211Type;
  1091. PNET_PACKET_BUFFER Packet;
  1092. ULONG QueueSelect;
  1093. ULONG Raid;
  1094. PRTLW81_BULK_OUT_TRANSFER Rtlw81Transfer;
  1095. KSTATUS Status;
  1096. PUSB_TRANSFER UsbTransfer;
  1097. Device = (PRTLW81_DEVICE)DeviceContext;
  1098. //
  1099. // If there are more bulk out transfers in transit that allowed, drop all
  1100. // of these packets.
  1101. //
  1102. if ((Device->BulkOutTransferCount >= RTLW81_MAX_BULK_OUT_TRANSFER_COUNT) &&
  1103. (Rtlw81DisablePacketDropping == FALSE)) {
  1104. return STATUS_RESOURCE_IN_USE;
  1105. }
  1106. //
  1107. // Otherwise submit all the packets. This may stretch over the maximum
  1108. // number of bulk out transfers, but it's a flexible line.
  1109. //
  1110. while (NET_PACKET_LIST_EMPTY(PacketList) == FALSE) {
  1111. Packet = LIST_VALUE(PacketList->Head.Next,
  1112. NET_PACKET_BUFFER,
  1113. ListEntry);
  1114. NET_REMOVE_PACKET_FROM_LIST(Packet, PacketList);
  1115. ASSERT(IS_ALIGNED(Packet->BufferSize, MmGetIoBufferAlignment()) !=
  1116. FALSE);
  1117. ASSERT(IS_ALIGNED((UINTN)Packet->Buffer,
  1118. MmGetIoBufferAlignment()) != FALSE);
  1119. ASSERT(IS_ALIGNED((UINTN)Packet->BufferPhysicalAddress,
  1120. MmGetIoBufferAlignment()) != FALSE);
  1121. //
  1122. // There might be legitimate reasons for this assert to be spurious,
  1123. // but most likely this assert fired because something in the
  1124. // networking stack failed to properly allocate the required header
  1125. // space. Go figure out who allocated this packet.
  1126. //
  1127. ASSERT(Packet->DataOffset == RTLW81_TRANSMIT_HEADER_SIZE);
  1128. Net80211Header = Packet->Buffer + Packet->DataOffset;
  1129. DataSize = Packet->FooterOffset - Packet->DataOffset;
  1130. ASSERT(DataSize <= MAX_USHORT);
  1131. Packet->DataOffset -= RTLW81_TRANSMIT_HEADER_SIZE;
  1132. Header = Packet->Buffer + Packet->DataOffset;
  1133. RtlZeroMemory(Header, RTLW81_TRANSMIT_HEADER_SIZE);
  1134. Header->PacketLength = DataSize;
  1135. Header->Offset = RTLW81_TRANSMIT_HEADER_SIZE;
  1136. Header->TypeFlags = RTLW81_TRANSMIT_TYPE_FLAG_FIRST_SEGMENT |
  1137. RTLW81_TRANSMIT_TYPE_FLAG_LAST_SEGMENT |
  1138. RTLW81_TRANSMIT_TYPE_FLAG_OWN;
  1139. //
  1140. // Pick an endpoint based on the 802.11 frame type.
  1141. //
  1142. Net80211Type = NET80211_GET_FRAME_TYPE(Net80211Header);
  1143. if ((Net80211Type == NET80211_FRAME_TYPE_CONTROL) ||
  1144. (Net80211Type == NET80211_FRAME_TYPE_MANAGEMENT)) {
  1145. BulkOutType = Rtlw81BulkOutVo;
  1146. } else {
  1147. BulkOutType = Rtlw81BulkOutBe;
  1148. }
  1149. //
  1150. // Assume the default values for various fields in the header.
  1151. //
  1152. DataRate = RTLW81_TRANSMIT_DATA_RATE_INFORMATION_DATA_RATE_CCK1;
  1153. MacId = RTLW81_TRANSMIT_IDENTIFICATION_MAC_ID_BSS;
  1154. QueueSelect = RTLW81_TRANSMIT_IDENTIFICATION_QSEL_MGMT;
  1155. Raid = RTLW81_TRANSMIT_IDENTIFICATION_RAID_11B;
  1156. //
  1157. // Handle non-multicast requests to send 802.11 data packets.
  1158. //
  1159. if ((NET80211_IS_MULTICAST_BROADCAST(Net80211Header) == FALSE) &&
  1160. (Net80211Type == NET80211_FRAME_TYPE_DATA)) {
  1161. //
  1162. // TODO: Get the current IEEE802.11 mode.
  1163. //
  1164. Raid = RTLW81_TRANSMIT_IDENTIFICATION_RAID_11BG;
  1165. QueueSelect = RTLW81_TRANSMIT_IDENTIFICATION_QSEL_BE;
  1166. if ((Device->Flags & RTLW81_FLAG_8188E) != 0) {
  1167. Header->AggBkFlag |= RTLW81_TRANSMIT_AGG_BK_FLAG |
  1168. RTLW81_TRANSMIT_CCX_RPT;
  1169. } else {
  1170. Header->Identification |= RTLW81_TRANSMIT_IDENTIFICATION_AGG_BK;
  1171. }
  1172. //
  1173. // TODO: Modify the rate information based on 802.11 protocol.
  1174. //
  1175. Header->RateInformation |=
  1176. (RTLW81_TRANSMIT_RATE_INFORMATION_RTSRATE_OFDM24 <<
  1177. RTLW81_TRANSMIT_RATE_INFORMATION_RTSRATE_SHIFT) &
  1178. RTLW81_TRANSMIT_RATE_INFORMATION_RTSRATE_MASK;
  1179. Header->DataRateInformation |=
  1180. RTLW81_TRANSMIT_DATA_RATE_INFORMATION_OFDM24;
  1181. DataRate = RTLW81_TRANSMIT_DATA_RATE_INFORMATION_DATA_RATE_OFDM54;
  1182. //
  1183. // Handle multicast packets.
  1184. //
  1185. } else if (NET80211_IS_MULTICAST_BROADCAST(Net80211Header) != FALSE) {
  1186. Header->TypeFlags |= RTLW81_TRANSMIT_TYPE_FLAG_MULTICAST_BROADCAST;
  1187. MacId = RTLW81_TRANSMIT_IDENTIFICATION_MAC_ID_BROADCAST;
  1188. }
  1189. Header->Identification |=
  1190. (MacId << RTLW81_TRANSMIT_IDENTIFICATION_MAC_ID_SHIFT) &
  1191. RTLW81_TRANSMIT_IDENTIFICATION_MAC_ID_MASK;
  1192. Header->Identification |=
  1193. (QueueSelect << RTLW81_TRANSMIT_IDENTIFICATION_QSEL_SHIFT) &
  1194. RTLW81_TRANSMIT_IDENTIFICATION_QSEL_MASK;
  1195. Header->Identification |=
  1196. (Raid << RTLW81_TRANSMIT_IDENTIFICATION_RAID_SHIFT) &
  1197. RTLW81_TRANSMIT_IDENTIFICATION_RAID_MASK;
  1198. Header->DataRateInformation |=
  1199. (DataRate <<
  1200. RTLW81_TRANSMIT_DATA_RATE_INFORMATION_DATA_RATE_SHIFT) &
  1201. RTLW81_TRANSMIT_DATA_RATE_INFORMATION_DATA_RATE_MASK;
  1202. if (DataRate == RTLW81_TRANSMIT_DATA_RATE_INFORMATION_DATA_RATE_CCK1) {
  1203. Header->RateInformation |= RTLW81_TRANSMIT_RATE_INFORMATION_DRVRATE;
  1204. }
  1205. //
  1206. // Unless it is a QOS Data packet, use hardware sequence numbering.
  1207. //
  1208. if ((Net80211Type != NET80211_FRAME_TYPE_DATA) ||
  1209. (NET80211_GET_FRAME_SUBTYPE(Net80211Header) !=
  1210. NET80211_DATA_FRAME_SUBTYPE_QOS_DATA)) {
  1211. if ((Device->Flags & RTLW81_FLAG_8188E) != 0) {
  1212. Header->Sequence |= RTLW81_TRANSMIT_SEQUENCE_HARDWARE;
  1213. } else {
  1214. Header->RateInformation |=
  1215. RTLW81_TRANSMIT_RATE_INFORMATION_HWSEQ;
  1216. }
  1217. } else {
  1218. Header->Sequence = NET80211_GET_SEQUENCE_NUMBER(Net80211Header);
  1219. }
  1220. //
  1221. // Compute the 16-bit XOR checksum of the header.
  1222. //
  1223. Checksum = 0;
  1224. HeaderBuffer = (PUSHORT)Header;
  1225. Header->HeaderChecksum = 0;
  1226. for (Index = 0;
  1227. Index < (RTLW81_TRANSMIT_HEADER_SIZE / sizeof(USHORT));
  1228. Index += 1) {
  1229. Checksum ^= HeaderBuffer[Index];
  1230. }
  1231. Header->HeaderChecksum = Checksum;
  1232. //
  1233. // Allocate a transfer for this packet. All packets need to be dealt
  1234. // with, so if the allocation or submission fails then free the buffer.
  1235. //
  1236. Rtlw81Transfer = Rtlw81pAllocateBulkOutTransfer(Device, BulkOutType);
  1237. if (Rtlw81Transfer == NULL) {
  1238. Status = STATUS_INSUFFICIENT_RESOURCES;
  1239. RtlDebugPrint("RTLW81: Failed to allocate transfer.\n");
  1240. NetFreeBuffer(Packet);
  1241. break;
  1242. }
  1243. Rtlw81Transfer->Packet = Packet;
  1244. UsbTransfer = Rtlw81Transfer->UsbTransfer;
  1245. UsbTransfer->Length = Packet->FooterOffset;
  1246. UsbTransfer->BufferActualLength = Packet->BufferSize;
  1247. UsbTransfer->Buffer = Header;
  1248. UsbTransfer->BufferPhysicalAddress = Packet->BufferPhysicalAddress;
  1249. RtlAtomicAdd32(&(Device->BulkOutTransferCount), 1);
  1250. Status = UsbSubmitTransfer(UsbTransfer);
  1251. if (!KSUCCESS(Status)) {
  1252. RtlDebugPrint("RTLW81: Failed to submit transmit packet: %d\n",
  1253. Status);
  1254. Rtlw81Transfer->Packet = NULL;
  1255. Rtlw81pFreeBulkOutTransfer(Rtlw81Transfer);
  1256. NetFreeBuffer(Packet);
  1257. RtlAtomicAdd32(&(Device->BulkOutTransferCount), -1);
  1258. break;
  1259. }
  1260. }
  1261. return Status;
  1262. }
  1263. KSTATUS
  1264. Rtlw81GetSetInformation (
  1265. PVOID DeviceContext,
  1266. NET_LINK_INFORMATION_TYPE InformationType,
  1267. PVOID Data,
  1268. PUINTN DataSize,
  1269. BOOL Set
  1270. )
  1271. /*++
  1272. Routine Description:
  1273. This routine gets or sets the network device layer's link information.
  1274. Arguments:
  1275. DeviceContext - Supplies a pointer to the device context associated with
  1276. the link for which information is being set or queried.
  1277. InformationType - Supplies the type of information being queried or set.
  1278. Data - Supplies a pointer to the data buffer where the data is either
  1279. returned for a get operation or given for a set operation.
  1280. DataSize - Supplies a pointer that on input contains the size of the data
  1281. buffer. On output, contains the required size of the data buffer.
  1282. Set - Supplies a boolean indicating if this is a get operation (FALSE) or a
  1283. set operation (TRUE).
  1284. Return Value:
  1285. Status code.
  1286. --*/
  1287. {
  1288. PULONG Flags;
  1289. KSTATUS Status;
  1290. switch (InformationType) {
  1291. case NetLinkInformationChecksumOffload:
  1292. if (*DataSize != sizeof(ULONG)) {
  1293. return STATUS_INVALID_PARAMETER;
  1294. }
  1295. if (Set != FALSE) {
  1296. return STATUS_NOT_SUPPORTED;
  1297. }
  1298. Flags = (PULONG)Data;
  1299. *Flags = 0;
  1300. break;
  1301. default:
  1302. Status = STATUS_NOT_SUPPORTED;
  1303. break;
  1304. }
  1305. return Status;
  1306. }
  1307. KSTATUS
  1308. Rtlw81SetChannel (
  1309. PVOID DeviceContext,
  1310. ULONG Channel
  1311. )
  1312. /*++
  1313. Routine Description:
  1314. This routine sets the 802.11 link's channel to the given value.
  1315. Arguments:
  1316. DeviceContext - Supplies a pointer to the device context associated with
  1317. the 802.11 link whose channel is to be set.
  1318. Channel - Supplies the channel to which the device should be set.
  1319. Return Value:
  1320. Status code.
  1321. --*/
  1322. {
  1323. PRTLW81_DEVICE Device;
  1324. Device = (PRTLW81_DEVICE)DeviceContext;
  1325. Rtlw81pSetChannel(Device, Channel);
  1326. return STATUS_SUCCESS;
  1327. }
  1328. KSTATUS
  1329. Rtlw81SetState (
  1330. PVOID DeviceContext,
  1331. NET80211_STATE State,
  1332. PNET80211_BSS Bss
  1333. )
  1334. /*++
  1335. Routine Description:
  1336. This routine sets the 802.11 link to the given state. BSS information is
  1337. provided to communicate the 802.11 core's current connection status.
  1338. Arguments:
  1339. DeviceContext - Supplies a pointer to the device context associated with
  1340. the 802.11 link whose state is to be set.
  1341. State - Supplies the state to which the link is being set.
  1342. Bss - Supplies an optional pointer to information on the BSS with which the
  1343. link is authenticating or associating.
  1344. Return Value:
  1345. Status code.
  1346. --*/
  1347. {
  1348. ULONG BasicRates;
  1349. ULONG BeaconInterval;
  1350. ULONG BssIndex;
  1351. UCHAR BssRate;
  1352. PRTLW81_DEVICE Device;
  1353. ULONG LocalIndex;
  1354. UCHAR LocalRate;
  1355. RTLW81_MAC_ID_CONFIG_COMMAND MacIdCommand;
  1356. ULONG MaxBasicRateIndex;
  1357. ULONG MaxRateIndex;
  1358. ULONG Mode;
  1359. ULONG Rates;
  1360. USHORT Register;
  1361. KSTATUS Status;
  1362. ULONGLONG Timestamp;
  1363. ULONG Value;
  1364. Device = DeviceContext;
  1365. Status = STATUS_SUCCESS;
  1366. switch (State) {
  1367. case Net80211StateProbing:
  1368. //
  1369. // Receive frames from all BSSIDs during the probing state.
  1370. //
  1371. Value = RTLW81_READ_REGISTER32(Device,
  1372. Rtlw81RegisterReceiveConfiguration);
  1373. Value &= ~(RTLW81_RECEIVE_CONFIGURATION_CBSSID_DATA |
  1374. RTLW81_RECEIVE_CONFIGURATION_CBSSID_BCN);
  1375. RTLW81_WRITE_REGISTER32(Device,
  1376. Rtlw81RegisterReceiveConfiguration,
  1377. Value);
  1378. //
  1379. // Set the gain used in the probing state.
  1380. //
  1381. Value = RTLW81_READ_REGISTER32(Device, Rtlw81RegisterOfdm0AgcCore1);
  1382. Value &= ~RTLW81_OFDM0_AGC_CORE1_GAIN_MASK;
  1383. Value |= RTLW81_OFDM0_AGC_CORE1_GAIN_PROBE_VALUE;
  1384. RTLW81_WRITE_REGISTER32(Device, Rtlw81RegisterOfdm0AgcCore1, Value);
  1385. if ((Device->Flags & RTLW81_FLAG_8188E) == 0) {
  1386. Register = Rtlw81RegisterOfdm0AgcCore1 + 8;
  1387. Value = RTLW81_READ_REGISTER32(Device, Register);
  1388. Value &= ~RTLW81_OFDM0_AGC_CORE1_GAIN_MASK;
  1389. Value |= RTLW81_OFDM0_AGC_CORE1_GAIN_PROBE_VALUE;
  1390. RTLW81_WRITE_REGISTER32(Device, Register, Value);
  1391. }
  1392. break;
  1393. case Net80211StateAuthenticating:
  1394. //
  1395. // Set the gain used in the authenticating state.
  1396. //
  1397. Value = RTLW81_READ_REGISTER32(Device, Rtlw81RegisterOfdm0AgcCore1);
  1398. Value &= ~RTLW81_OFDM0_AGC_CORE1_GAIN_MASK;
  1399. Value |= RTLW81_OFDM0_AGC_CORE1_GAIN_AUTHENTICATE_VALUE;
  1400. RTLW81_WRITE_REGISTER32(Device, Rtlw81RegisterOfdm0AgcCore1, Value);
  1401. if ((Device->Flags & RTLW81_FLAG_8188E) == 0) {
  1402. Register = Rtlw81RegisterOfdm0AgcCore1 + 8;
  1403. Value = RTLW81_READ_REGISTER32(Device, Register);
  1404. Value &= ~RTLW81_OFDM0_AGC_CORE1_GAIN_MASK;
  1405. Value |= RTLW81_OFDM0_AGC_CORE1_GAIN_AUTHENTICATE_VALUE;
  1406. RTLW81_WRITE_REGISTER32(Device, Register, Value);
  1407. }
  1408. break;
  1409. case Net80211StateAssociated:
  1410. if (Bss == NULL) {
  1411. Status = STATUS_INVALID_PARAMETER;
  1412. break;
  1413. }
  1414. //
  1415. // Set the network type to associated.
  1416. //
  1417. Value = RTLW81_READ_REGISTER32(Device, Rtlw81RegisterConfiguration);
  1418. Value &= ~RTLW81_CONFIGURATION_NETWORK_TYPE_MASK;
  1419. Value |= (RTLW81_CONFIGURATION_NETWORK_TYPE_INFRA <<
  1420. RTLW81_CONFIGURATION_NETWORK_TYPE_SHIFT);
  1421. RTLW81_WRITE_REGISTER32(Device, Rtlw81RegisterConfiguration, Value);
  1422. //
  1423. // Filter out traffic that is not coming from the BSSID.
  1424. //
  1425. Value = *((PULONG)&(Bss->Bssid[0]));
  1426. RTLW81_WRITE_REGISTER32(Device, Rtlw81RegisterBssid0, Value);
  1427. Value = *((PUSHORT)&(Bss->Bssid[4]));
  1428. RTLW81_WRITE_REGISTER32(Device, Rtlw81RegisterBssid1, Value);
  1429. //
  1430. // Set the rate based on the mode. Only 11b and 11b/g are currently
  1431. // supported.
  1432. //
  1433. if (Bss->Mode == Net80211ModeB) {
  1434. RTLW81_WRITE_REGISTER8(Device,
  1435. Rtlw81RegisterIniRtsRateSelect,
  1436. RTLW81_INI_RTS_RATE_SELECT_11B);
  1437. } else {
  1438. RTLW81_WRITE_REGISTER8(Device,
  1439. Rtlw81RegisterIniRtsRateSelect,
  1440. RTLW81_INI_RTS_RATE_SELECT_11BG);
  1441. }
  1442. //
  1443. // Flush all access control queues and enable transmit.
  1444. //
  1445. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterTransmitPause, 0);
  1446. //
  1447. // Set the beacon interval.
  1448. //
  1449. RTLW81_WRITE_REGISTER16(Device,
  1450. Rtlw81RegisterBeaconInterval,
  1451. Bss->BeaconInterval);
  1452. //
  1453. // Enable filtering based on the BSSID.
  1454. //
  1455. Value = RTLW81_READ_REGISTER32(Device,
  1456. Rtlw81RegisterReceiveConfiguration);
  1457. Value |= RTLW81_RECEIVE_CONFIGURATION_CBSSID_BCN |
  1458. RTLW81_RECEIVE_CONFIGURATION_CBSSID_DATA;
  1459. RTLW81_WRITE_REGISTER32(Device,
  1460. Rtlw81RegisterReceiveConfiguration,
  1461. Value);
  1462. //
  1463. // Accept all data frames.
  1464. //
  1465. RTLW81_WRITE_REGISTER16(Device,
  1466. Rtlw81RegisterReceiveDataFilter,
  1467. 0xFFFF);
  1468. //
  1469. // Initialize TSF for the device. This keeps it in sync with the rest
  1470. // of the BSS.
  1471. //
  1472. Value = RTLW81_READ_REGISTER8(Device, Rtlw81RegisterBeaconControl);
  1473. Value &= ~RTLW81_BEACON_CONTROL_DISABLE_TSF_UDT0;
  1474. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterBeaconControl, Value);
  1475. Value = RTLW81_READ_REGISTER8(Device, Rtlw81RegisterBeaconControl);
  1476. Value &= ~RTLW81_BEACON_CONTROL_ENABLE_BEACON;
  1477. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterBeaconControl, Value);
  1478. Timestamp = Bss->Timestamp;
  1479. BeaconInterval = Bss->BeaconInterval * NET80211_TIME_UNIT;
  1480. Timestamp -= Timestamp % BeaconInterval;
  1481. Timestamp -= NET80211_TIME_UNIT;
  1482. RTLW81_WRITE_REGISTER32(Device, Rtlw81RegisterTsftr0, (ULONG)Timestamp);
  1483. RTLW81_WRITE_REGISTER32(Device,
  1484. Rtlw81RegisterTsftr1,
  1485. (ULONG)(Timestamp >> 32));
  1486. Value = RTLW81_READ_REGISTER8(Device, Rtlw81RegisterBeaconControl);
  1487. Value |= RTLW81_BEACON_CONTROL_ENABLE_BEACON;
  1488. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterBeaconControl, Value);
  1489. //
  1490. // Update the SIFS registers.
  1491. //
  1492. RTLW81_WRITE_REGISTER16(Device,
  1493. Rtlw81RegisterSifsCck,
  1494. RTLW81_SIFS_CCK_ASSOCIATED);
  1495. RTLW81_WRITE_REGISTER16(Device,
  1496. Rtlw81RegisterSifsOfdm,
  1497. RTLW81_SIFS_OFDM_ASSOCIATED);
  1498. RTLW81_WRITE_REGISTER16(Device,
  1499. Rtlw81RegisterSpecSifs,
  1500. RTLW81_SPEC_SIFS_ASSOCIATED);
  1501. RTLW81_WRITE_REGISTER16(Device,
  1502. Rtlw81RegisterMacSpecSifs,
  1503. RTLW81_MAC_SPEC_SIFS_ASSOCIATED);
  1504. RTLW81_WRITE_REGISTER16(Device,
  1505. Rtlw81RegisterT2tSifs,
  1506. RTLW81_T2T_SIFS_ASSOCIATED);
  1507. RTLW81_WRITE_REGISTER16(Device,
  1508. Rtlw81RegisterR2tSifs,
  1509. RTLW81_R2T_SIFS_ASSOCIATED);
  1510. //
  1511. // Initialize rate adaptation.
  1512. //
  1513. if ((Device->Flags & RTLW81_FLAG_8188E) == 0) {
  1514. //
  1515. // Find the set of rates that are supported by both the local
  1516. // device and the BSS.
  1517. //
  1518. Rates = 0;
  1519. BasicRates = 0;
  1520. MaxRateIndex = 0;
  1521. MaxBasicRateIndex = 0;
  1522. for (BssIndex = 0;
  1523. BssIndex < Bss->Rates.Count;
  1524. BssIndex += 1) {
  1525. BssRate = Bss->Rates.Rate[BssIndex];
  1526. BssRate &= NET80211_RATE_VALUE_MASK;
  1527. for (LocalIndex = 0;
  1528. LocalIndex < RtlwDefaultRateInformation.Count;
  1529. LocalIndex += 1) {
  1530. LocalRate = RtlwDefaultRateInformation.Rate[LocalIndex];
  1531. LocalRate &= NET80211_RATE_VALUE_MASK;
  1532. if (LocalRate == BssRate) {
  1533. break;
  1534. }
  1535. }
  1536. if (LocalIndex == RtlwDefaultRateInformation.Count) {
  1537. continue;
  1538. }
  1539. Rates |= (1 << LocalIndex);
  1540. if (LocalIndex > MaxRateIndex) {
  1541. MaxRateIndex = LocalIndex;
  1542. }
  1543. BssRate = Bss->Rates.Rate[BssIndex];
  1544. if ((BssRate & NET80211_RATE_BASIC) != 0) {
  1545. BasicRates |= (1 << LocalIndex);
  1546. if (LocalIndex > MaxBasicRateIndex) {
  1547. MaxBasicRateIndex = LocalIndex;
  1548. }
  1549. }
  1550. }
  1551. //
  1552. // Set the basic rate information.
  1553. //
  1554. if (Bss->Mode == Net80211ModeB) {
  1555. Mode = RTLW81_TRANSMIT_IDENTIFICATION_RAID_11B;
  1556. } else {
  1557. Mode = RTLW81_TRANSMIT_IDENTIFICATION_RAID_11BG;
  1558. }
  1559. MacIdCommand.MacId = RTLW81_MAC_ID_CONFIG_COMMAND_ID_BROADCAST |
  1560. RTLW81_MAC_ID_CONFIG_COMMAND_ID_VALID;
  1561. MacIdCommand.Mask =
  1562. (Mode << RTLW81_MAC_ID_CONFIG_COMMAND_MASK_MODE_SHIFT) |
  1563. BasicRates;
  1564. Status = Rtlw81pSendFirmwareCommand(
  1565. Device,
  1566. RTLW81_FIRMWARE_COMMAND_MAC_ID_CONFIG,
  1567. &MacIdCommand,
  1568. sizeof(RTLW81_MAC_ID_CONFIG_COMMAND));
  1569. if (!KSUCCESS(Status)) {
  1570. break;
  1571. }
  1572. RTLW81_WRITE_REGISTER8(Device,
  1573. Rtlw81RegisterIniDataRateSelectBroadcast,
  1574. MaxBasicRateIndex);
  1575. //
  1576. // Set the overall rate information.
  1577. //
  1578. MacIdCommand.MacId = RTLW81_MAC_ID_CONFIG_COMMAND_ID_BSS |
  1579. RTLW81_MAC_ID_CONFIG_COMMAND_ID_VALID;
  1580. MacIdCommand.Mask =
  1581. (Mode << RTLW81_MAC_ID_CONFIG_COMMAND_MASK_MODE_SHIFT) |
  1582. Rates;
  1583. Status = Rtlw81pSendFirmwareCommand(
  1584. Device,
  1585. RTLW81_FIRMWARE_COMMAND_MAC_ID_CONFIG,
  1586. &MacIdCommand,
  1587. sizeof(RTLW81_MAC_ID_CONFIG_COMMAND));
  1588. if (!KSUCCESS(Status)) {
  1589. break;
  1590. }
  1591. RTLW81_WRITE_REGISTER8(Device,
  1592. Rtlw81RegisterIniDataRateSelectBss,
  1593. MaxRateIndex);
  1594. }
  1595. Rtlw81pSetLed(Device, TRUE);
  1596. break;
  1597. default:
  1598. Status = STATUS_SUCCESS;
  1599. break;
  1600. }
  1601. return Status;
  1602. }
  1603. VOID
  1604. Rtlw81BulkInTransferCompletion (
  1605. PUSB_TRANSFER Transfer
  1606. )
  1607. /*++
  1608. Routine Description:
  1609. This routine is called when the bulk in transfer returns. It processes
  1610. the notification from the device.
  1611. Arguments:
  1612. Transfer - Supplies a pointer to the transfer that completed.
  1613. Return Value:
  1614. None.
  1615. --*/
  1616. {
  1617. PUCHAR Data;
  1618. PRTLW81_DEVICE Device;
  1619. PRTLW81_RECEIVE_HEADER Header;
  1620. ULONG InfoSize;
  1621. ULONG Length;
  1622. NET_PACKET_BUFFER NetPacket;
  1623. ULONG PacketCount;
  1624. ULONG PacketLength;
  1625. PHYSICAL_ADDRESS PhysicalAddress;
  1626. PVOID PhyStatus;
  1627. ULONG Rate;
  1628. NET80211_RECEIVE_PACKET ReceivePacket;
  1629. LONG Rssi;
  1630. KSTATUS Status;
  1631. ULONG TotalLength;
  1632. Device = Transfer->UserData;
  1633. Status = STATUS_SUCCESS;
  1634. //
  1635. // If the transfer failed, don't bother with the data.
  1636. //
  1637. if (!KSUCCESS(Transfer->Status)) {
  1638. //
  1639. // If the transfer stalled, attempt to clear the HALT feature from the
  1640. // endpoint.
  1641. //
  1642. if (Transfer->Error == UsbErrorTransferStalled) {
  1643. Status = UsbClearFeature(Device->UsbCoreHandle,
  1644. USB_SETUP_REQUEST_ENDPOINT_RECIPIENT,
  1645. USB_FEATURE_ENDPOINT_HALT,
  1646. Device->BulkInEndpoint);
  1647. }
  1648. goto BulkInTransferCompletionEnd;
  1649. }
  1650. Data = Transfer->Buffer;
  1651. PhysicalAddress = Transfer->BufferPhysicalAddress;
  1652. Length = Transfer->LengthTransferred;
  1653. if (Length < sizeof(RTLW81_RECEIVE_HEADER)) {
  1654. RtlDebugPrint("RTLW81: Received odd sized data (%d).\n", Length);
  1655. goto BulkInTransferCompletionEnd;
  1656. }
  1657. Header = (PRTLW81_RECEIVE_HEADER)Data;
  1658. PacketCount = Header->PacketCount;
  1659. ReceivePacket.Version = NET80211_RECEIVE_PACKET_VERSION;
  1660. ReceivePacket.NetPacket = &NetPacket;
  1661. NetPacket.IoBuffer = NULL;
  1662. NetPacket.Flags = 0;
  1663. while (PacketCount != 0) {
  1664. if (Length < sizeof(RTLW81_RECEIVE_HEADER)) {
  1665. RtlDebugPrint("RTLW81: Received odd sized data (%d).\n", Length);
  1666. break;
  1667. }
  1668. Header = (PRTLW81_RECEIVE_HEADER)Data;
  1669. if ((Header->LengthAndErrorFlags & RTLW81_RECEIVE_ERROR_MASK) != 0) {
  1670. RtlDebugPrint("RTLW81: Receive error 0x%x\n",
  1671. Header->LengthAndErrorFlags);
  1672. break;
  1673. }
  1674. PacketLength = (Header->LengthAndErrorFlags &
  1675. RTLW81_RECEIVE_PACKET_LENGTH_MASK) >>
  1676. RTLW81_RECEIVE_PACKET_LENGTH_SHIFT;
  1677. if (PacketLength == 0) {
  1678. break;
  1679. }
  1680. InfoSize = ((Header->Status & RTLW81_RECEIVE_STATUS_INFO_SIZE_MASK) >>
  1681. RTLW81_RECEIVE_STATUS_INFO_SIZE_SHIFT) * 8;
  1682. TotalLength = PacketLength + InfoSize + sizeof(RTLW81_RECEIVE_HEADER);
  1683. if (TotalLength > Length) {
  1684. RtlDebugPrint("RTLW81: Got packet purported to be size %d, but "
  1685. "only %d bytes remaining in the transfer.\n",
  1686. TotalLength,
  1687. Length);
  1688. break;
  1689. }
  1690. //
  1691. // Get the received signal strength indicator (RSSI), if present.
  1692. //
  1693. ReceivePacket.Rssi = 0;
  1694. if ((InfoSize != 0) &&
  1695. ((Header->Status & RTLW81_RECEIVE_STATUS_PHY_STATUS) != 0)) {
  1696. PhyStatus = (PVOID)(Header + 1);
  1697. Rate = (Header->RateInformation &
  1698. RTLW81_RECEIVE_RATE_INFORMATION_RATE_MASK) >>
  1699. RTLW81_RECEIVE_RATE_INFORMATION_RATE_SHIFT;
  1700. Status = Rtlw81pGetRssi(Device, PhyStatus, InfoSize, Rate, &Rssi);
  1701. if (!KSUCCESS(Status)) {
  1702. RtlDebugPrint("RTLW81: Failed to get RSSI information from "
  1703. "packet with status %d\n",
  1704. Status);
  1705. break;
  1706. }
  1707. ReceivePacket.Rssi = Rssi;
  1708. }
  1709. NetPacket.Buffer = Data + sizeof(RTLW81_RECEIVE_HEADER) + InfoSize;
  1710. NetPacket.BufferPhysicalAddress = PhysicalAddress +
  1711. sizeof(RTLW81_RECEIVE_HEADER) +
  1712. InfoSize;
  1713. NetPacket.BufferSize = PacketLength;
  1714. NetPacket.DataSize = NetPacket.BufferSize;
  1715. NetPacket.DataOffset = 0;
  1716. NetPacket.FooterOffset = NetPacket.DataSize;
  1717. Net80211ProcessReceivedPacket(Device->Net80211Link, &ReceivePacket);
  1718. //
  1719. // Advance to the next packet, adding an extra 4 and aligning the total
  1720. // offset to 4.
  1721. //
  1722. TotalLength = ALIGN_RANGE_UP(TotalLength,
  1723. RTLW81_BULK_IN_PACKET_ALIGNMENT);
  1724. if (TotalLength >= Length) {
  1725. break;
  1726. }
  1727. Length -= TotalLength;
  1728. Data += TotalLength;
  1729. PhysicalAddress += TotalLength;
  1730. }
  1731. BulkInTransferCompletionEnd:
  1732. Status = UsbSubmitTransfer(Transfer);
  1733. if (!KSUCCESS(Status)) {
  1734. RtlDebugPrint("RTLW81: Failed to resubmit bulk IN transfer.\n");
  1735. }
  1736. return;
  1737. }
  1738. KSTATUS
  1739. Rtlw81pInitialize (
  1740. PRTLW81_DEVICE Device,
  1741. PIRP Irp
  1742. )
  1743. /*++
  1744. Routine Description:
  1745. This routine initializes and enables the RTL81xx wireless device.
  1746. Arguments:
  1747. Device - Supplies a pointer to the device.
  1748. Irp - Supplies a pointer to the IRP that is driving the initialization.
  1749. Return Value:
  1750. Status code.
  1751. --*/
  1752. {
  1753. ULONG Chain;
  1754. PRTLW81_DEVICE_DATA DeviceData;
  1755. ULONG Index;
  1756. ULONG MacRegisterCount;
  1757. UCHAR PaSetting;
  1758. RTLW81_REGISTER Register;
  1759. UCHAR RfRegister;
  1760. ULONG Shift;
  1761. KSTATUS Status;
  1762. ULONG Type;
  1763. ULONG Value;
  1764. Status = STATUS_SUCCESS;
  1765. //
  1766. // Start phase 0 initialization. This goes up until the asynchronous load
  1767. // of the firmware.
  1768. //
  1769. if (Device->InitializationPhase == 0) {
  1770. Device->InitializationStatus = STATUS_SUCCESS;
  1771. //
  1772. // Figure out the device type and set the appropriate flags.
  1773. //
  1774. if ((Device->Flags & RTLW81_FLAG_8188E) == 0) {
  1775. Value = RTLW81_READ_REGISTER32(Device,
  1776. Rtlw81RegisterSysConfiguration);
  1777. if ((Value & RTLW81_SYS_CONFIGURATION_TRP_VAUX_ENABLE) != 0) {
  1778. Status = STATUS_INVALID_CONFIGURATION;
  1779. goto InitializeEnd;
  1780. }
  1781. if ((Value & RTLW81_SYS_CONFIGURATION_TYPE_8192C) != 0) {
  1782. Device->Flags |= RTLW81_FLAG_8192C;
  1783. Value = RTLW81_READ_REGISTER32(Device, Rtlw81RegisterHponFsm);
  1784. Value &= RTLW81_HPON_FSM_CHIP_BONDING_ID_MASK;
  1785. Value >>= RTLW81_HPON_FSM_CHIP_BONDING_ID_SHIFT;
  1786. if (Value == RTLW81_HPON_FSM_CHIP_BONDING_ID_8192C_1T2R) {
  1787. Device->Flags |= RTLW81_FLAG_8192C_1T2R;
  1788. }
  1789. }
  1790. if ((Value & RTLW81_SYS_CONFIGURATION_VENDOR_UMC) != 0) {
  1791. Device->Flags |= RTLW81_FLAG_UMC;
  1792. if ((Value & RTLW81_SYS_CONFIGURATION_VERSION_MASK) == 0) {
  1793. Device->Flags |= RTLW81_FLAG_UMC_A_CUT;
  1794. }
  1795. }
  1796. }
  1797. //
  1798. // Record the number of transmit and receive chains.
  1799. //
  1800. if ((Device->Flags & RTLW81_FLAG_8192C) != 0) {
  1801. if ((Device->Flags & RTLW81_FLAG_8192C_1T2R) != 0) {
  1802. Device->TransmitChainCount =
  1803. RTLW81_8192C_1T2R_TRANSMIT_CHAIN_COUNT;
  1804. } else {
  1805. Device->TransmitChainCount = RTLW81_8192C_TRANSMIT_CHAIN_COUNT;
  1806. }
  1807. Device->ReceiveChainCount = RTLW81_8192C_RECEIVE_CHAIN_COUNT;
  1808. } else {
  1809. Device->TransmitChainCount = RTLW81_DEFAULT_TRANSMIT_CHAIN_COUNT;
  1810. Device->ReceiveChainCount = RTLW81_DEFAULT_RECEIVE_CHAIN_COUNT;
  1811. }
  1812. //
  1813. // Read the device ROM. This caches information needed later, like the
  1814. // MAC address, in the device structure.
  1815. //
  1816. Status = Rtlw81pReadRom(Device);
  1817. if (!KSUCCESS(Status)) {
  1818. goto InitializeEnd;
  1819. }
  1820. //
  1821. // Perform device specific initialization steps to power on the device
  1822. // and enable transmit and receive.
  1823. //
  1824. if ((Device->Flags & RTLW81_FLAG_8188E) != 0) {
  1825. Status = Rtlw81p8188eInitialize(Device);
  1826. if (!KSUCCESS(Status)) {
  1827. goto InitializeEnd;
  1828. }
  1829. } else {
  1830. Status = Rtlw81pDefaultInitialize(Device);
  1831. if (!KSUCCESS(Status)) {
  1832. goto InitializeEnd;
  1833. }
  1834. }
  1835. //
  1836. // Initialize the device's DMA queues.
  1837. //
  1838. Status = Rtlw81pInitializeDma(Device);
  1839. if (!KSUCCESS(Status)) {
  1840. RtlDebugPrint("RTWL: DMA init failed: %d\n", Status);
  1841. goto InitializeEnd;
  1842. }
  1843. //
  1844. // Set the driver information size.
  1845. //
  1846. RTLW81_WRITE_REGISTER8(Device,
  1847. Rtlw81RegisterReceiveDriverInformationSize,
  1848. RTLW81_DRIVER_INFORMATION_SIZE_DEFAULT);
  1849. //
  1850. // Turn on the interrupts.
  1851. //
  1852. if ((Device->Flags & RTLW81_FLAG_8188E) != 0) {
  1853. RTLW81_WRITE_REGISTER32(Device,
  1854. Rtlw81Register8188eInterruptStatus,
  1855. 0xFFFFFFFF);
  1856. Value = (RTLW81_8188E_INTERRUPT_MASK_CPWM |
  1857. RTLW81_8188E_INTERRUPT_MASK_CPWM2 |
  1858. RTLW81_8188E_INTERRUPT_MASK_TBDER |
  1859. RTLW81_8188E_INTERRUPT_MASK_PS_TIMEOUT);
  1860. RTLW81_WRITE_REGISTER32(Device,
  1861. Rtlw81Register8188eInterruptMask,
  1862. Value);
  1863. Value = (RTLW81_8188E_INTERRUPT_EXTRA_MASK_RECEIVE_FOVM |
  1864. RTLW81_8188E_INTERRUPT_EXTRA_MASK_TRANSMIT_FOVM |
  1865. RTLW81_8188E_INTERRUPT_EXTRA_MASK_RECEIVE_ERROR |
  1866. RTLW81_8188E_INTERRUPT_EXTRA_MASK_TRANSMIT_ERROR);
  1867. RTLW81_WRITE_REGISTER32(Device,
  1868. Rtlw81Register8188eInterruptExtraMask,
  1869. Value);
  1870. Value = RTLW81_READ_REGISTER8(Device,
  1871. Rtlw81RegisterUsbSpecialOption);
  1872. Value |= RTLW81_USB_SPECIAL_OPTION_INT_BULK_SELECT;
  1873. RTLW81_WRITE_REGISTER8(Device,
  1874. Rtlw81RegisterUsbSpecialOption,
  1875. Value);
  1876. } else {
  1877. RTLW81_WRITE_REGISTER32(Device,
  1878. Rtlw81RegisterDefaultInterruptStatus,
  1879. 0xFFFFFFFF);
  1880. RTLW81_WRITE_REGISTER32(Device,
  1881. Rtlw81RegisterDefaultInterruptMask,
  1882. 0xFFFFFFFF);
  1883. }
  1884. //
  1885. // Set the MAC address.
  1886. //
  1887. Rtlw81pWriteData(Device,
  1888. Rtlw81RegisterMacAddress,
  1889. Device->MacAddress,
  1890. NET80211_ADDRESS_SIZE);
  1891. //
  1892. // Set the network type.
  1893. //
  1894. Value = RTLW81_READ_REGISTER32(Device, Rtlw81RegisterConfiguration);
  1895. Value &= ~RTLW81_CONFIGURATION_NETWORK_TYPE_MASK;
  1896. Value |= (RTLW81_CONFIGURATION_NETWORK_TYPE_INFRA <<
  1897. RTLW81_CONFIGURATION_NETWORK_TYPE_SHIFT);
  1898. RTLW81_WRITE_REGISTER32(Device, Rtlw81RegisterConfiguration, Value);
  1899. //
  1900. // Initialize the receive filters.
  1901. //
  1902. Value = RTLW81_RECEIVE_CONFIGURATION_AAP |
  1903. RTLW81_RECEIVE_CONFIGURATION_APM |
  1904. RTLW81_RECEIVE_CONFIGURATION_AM |
  1905. RTLW81_RECEIVE_CONFIGURATION_AB |
  1906. RTLW81_RECEIVE_CONFIGURATION_APP_ICV |
  1907. RTLW81_RECEIVE_CONFIGURATION_AMF |
  1908. RTLW81_RECEIVE_CONFIGURATION_HTC_LOC_CTRL |
  1909. RTLW81_RECEIVE_CONFIGURATION_APP_MIC |
  1910. RTLW81_RECEIVE_CONFIGURATION_APP_PHYSTS;
  1911. RTLW81_WRITE_REGISTER32(Device,
  1912. Rtlw81RegisterReceiveConfiguration,
  1913. Value);
  1914. //
  1915. // Accept all multicast frames.
  1916. //
  1917. RTLW81_WRITE_REGISTER32(Device, Rtlw81RegisterMulticast1, 0xFFFFFFFF);
  1918. RTLW81_WRITE_REGISTER32(Device, Rtlw81RegisterMulticast2, 0xFFFFFFFF);
  1919. //
  1920. // Accept all management frames.
  1921. //
  1922. RTLW81_WRITE_REGISTER16(Device,
  1923. Rtlw81RegisterReceiveManagementFilter,
  1924. 0xFFFF);
  1925. //
  1926. // Reject all control frames.
  1927. //
  1928. RTLW81_WRITE_REGISTER16(Device,
  1929. Rtlw81RegisterReceiveControlFilter,
  1930. 0x0000);
  1931. //
  1932. // Reject all data frames.
  1933. //
  1934. RTLW81_WRITE_REGISTER16(Device,
  1935. Rtlw81RegisterReceiveDataFilter,
  1936. 0x0000);
  1937. //
  1938. // Set the response rate.
  1939. //
  1940. Value = RTLW81_READ_REGISTER32(Device,
  1941. Rtlw81RegisterReceiveResponseRate);
  1942. Value &= ~RTLW81_RECEIVE_RESPONSE_RATE_BITMAP_MASK;
  1943. Value |= (RTLW81_RECEIVE_RESPONSE_RATE_CCK_ONLY_1M <<
  1944. RTLW81_RECEIVE_RESPONSE_RATE_BITMAP_SHIFT);
  1945. RTLW81_WRITE_REGISTER32(Device,
  1946. Rtlw81RegisterReceiveResponseRate,
  1947. Value);
  1948. //
  1949. // Set the retry limits.
  1950. //
  1951. RTLW81_WRITE_REGISTER16(Device,
  1952. Rtlw81RegisterRetryLimit,
  1953. RTLW81_RETRY_LIMIT_DEFAULT);
  1954. //
  1955. // Initialize the short interfame space (SIFS).
  1956. //
  1957. RTLW81_WRITE_REGISTER16(Device,
  1958. Rtlw81RegisterSpecSifs,
  1959. RTLW81_SPEC_SIFS_DEFAULT);
  1960. RTLW81_WRITE_REGISTER16(Device,
  1961. Rtlw81RegisterMacSpecSifs,
  1962. RTLW81_MAC_SPEC_SIFS_DEFAULT);
  1963. RTLW81_WRITE_REGISTER16(Device,
  1964. Rtlw81RegisterSifsCck,
  1965. RTLW81_SIFS_CCK_DEFAULT);
  1966. RTLW81_WRITE_REGISTER16(Device,
  1967. Rtlw81RegisterSifsOfdm,
  1968. RTLW81_SIFS_OFDM_DEFAULT);
  1969. //
  1970. // Initialize the EDCA parameters for the four access categories.
  1971. //
  1972. RTLW81_WRITE_REGISTER32(Device,
  1973. Rtlw81RegisterEdcaBeParam,
  1974. RTLW81_EDCA_BE_PARAM_DEFAULT);
  1975. RTLW81_WRITE_REGISTER32(Device,
  1976. Rtlw81RegisterEdcaBkParam,
  1977. RTLW81_EDCA_BK_PARAM_DEFAULT);
  1978. RTLW81_WRITE_REGISTER32(Device,
  1979. Rtlw81RegisterEdcaViParam,
  1980. RTLW81_EDCA_VI_PARAM_DEFAULT);
  1981. RTLW81_WRITE_REGISTER32(Device,
  1982. Rtlw81RegisterEdcaVoParam,
  1983. RTLW81_EDCA_VO_PARAM_DEFAULT);
  1984. //
  1985. // Setup rate fallback. This is not necessary on the RTL8188EU.
  1986. //
  1987. if ((Device->Flags & RTLW81_FLAG_8188E) == 0) {
  1988. RTLW81_WRITE_REGISTER32(Device,
  1989. Rtlw81RegisterDarfrc0,
  1990. RTLW81_DARFRC0_DEFAULT);
  1991. RTLW81_WRITE_REGISTER32(Device,
  1992. Rtlw81RegisterDarfrc1,
  1993. RTLW81_DARFRC1_DEFAULT);
  1994. RTLW81_WRITE_REGISTER32(Device,
  1995. Rtlw81RegisterRarfrc0,
  1996. RTLW81_RARFRC0_DEFAULT);
  1997. RTLW81_WRITE_REGISTER32(Device,
  1998. Rtlw81RegisterRarfrc1,
  1999. RTLW81_RARFRC1_DEFAULT);
  2000. }
  2001. Register = Rtlw81RegisterFirmwareHardwareTransmitQueueControl;
  2002. Value = RTLW81_READ_REGISTER8(Device, Register);
  2003. Value |=
  2004. RTLW81_FIRMWARE_HARDWARE_TRANSMIT_QUEUE_CONTROL_AMPDU_RETRY_NEW;
  2005. RTLW81_WRITE_REGISTER8(Device, Register, Value);
  2006. RTLW81_WRITE_REGISTER8(Device,
  2007. Rtlw81RegisterAckTimeout,
  2008. RTLW81_ACK_TIMEOUT_DEFAULT);
  2009. //
  2010. // Set up USB aggregation.
  2011. //
  2012. Value = RTLW81_READ_REGISTER32(
  2013. Device,
  2014. Rtlw81RegisterTransmitDescriptorControl0);
  2015. Value &= ~RTLW81_TRANSMIT_DESCRIPTOR_CONTROL_BLOCK_COUNT_MASK;
  2016. Value |= (RTLW81_TRANSMIT_DESCRIPTOR_CONTROL_BLOCK_COUNT_DEFAULT <<
  2017. RTLW81_TRANSMIT_DESCRIPTOR_CONTROL_BLOCK_COUNT_SHIFT) &
  2018. RTLW81_TRANSMIT_DESCRIPTOR_CONTROL_BLOCK_COUNT_MASK;
  2019. RTLW81_WRITE_REGISTER32(Device,
  2020. Rtlw81RegisterTransmitDescriptorControl0,
  2021. Value);
  2022. Value = RTLW81_READ_REGISTER8(Device, Rtlw81RegisterTransmitReceiveDma);
  2023. Value |= RTLW81_TRANSMIT_RECEIVE_DMA_AGG_ENABLE;
  2024. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterTransmitReceiveDma, Value);
  2025. RTLW81_WRITE_REGISTER8(Device,
  2026. Rtlw81RegisterReceiveDmaAggPgTh0,
  2027. RTLW81_RECEIVE_DMA_AGG_PG_TH0_DEFAULT);
  2028. if ((Device->Flags & RTLW81_FLAG_8188E) != 0) {
  2029. RTLW81_WRITE_REGISTER8(Device,
  2030. Rtlw81RegisterReceiveDmaAggPgTh1,
  2031. RTLW81_RECEIVE_DMA_AGG_PG_TH1_DEFAULT);
  2032. } else {
  2033. RTLW81_WRITE_REGISTER8(Device,
  2034. Rtlw81RegisterUsbDmaAggTo,
  2035. RTLW81_USB_DMA_AGG_TO_DEFAULT);
  2036. Value = RTLW81_READ_REGISTER8(Device,
  2037. Rtlw81RegisterUsbSpecialOption);
  2038. Value |= RTLW81_USB_SPECIAL_OPTION_AGG_ENABLE;
  2039. RTLW81_WRITE_REGISTER8(Device,
  2040. Rtlw81RegisterUsbSpecialOption,
  2041. Value);
  2042. RTLW81_WRITE_REGISTER8(Device,
  2043. Rtlw81RegisterUsbAggTh,
  2044. RTLW81_USB_AGG_TH_DEFAULT);
  2045. RTLW81_WRITE_REGISTER8(Device,
  2046. Rtlw81RegisterUsbAggTo,
  2047. RTLW81_USB_AGG_TO_DEFAULT);
  2048. }
  2049. //
  2050. // Initialize the beacon parameters.
  2051. //
  2052. RTLW81_WRITE_REGISTER16(Device,
  2053. Rtlw81RegisterBeaconControl,
  2054. RTLW81_BEACON_CONTROL_DEFAULT);
  2055. RTLW81_WRITE_REGISTER16(Device,
  2056. Rtlw81RegisterTbttProhibit,
  2057. RTLW81_TBTT_PROHIBIT_DEFAULT);
  2058. RTLW81_WRITE_REGISTER8(Device,
  2059. Rtlw81RegisterDriverEarlyInt,
  2060. RTLW81_DRIVER_EARLY_INIT_DEFAULT);
  2061. RTLW81_WRITE_REGISTER8(Device,
  2062. Rtlw81RegisterBeaconDmaTime,
  2063. RTLW81_BEACON_DMA_TIME_DEFAULT);
  2064. RTLW81_WRITE_REGISTER16(Device,
  2065. Rtlw81RegisterBeaconTcfg,
  2066. RTLW81_BEACON_TCFG_DEFAULT);
  2067. //
  2068. // Initialize the AMPDU aggregation.
  2069. //
  2070. if ((Device->Flags & RTLW81_FLAG_8188E) == 0) {
  2071. RTLW81_WRITE_REGISTER32(Device,
  2072. Rtlw81RegisterAggregateLengthLimit,
  2073. RTLW81_AGGREGATE_LENGTH_LIMIT_DEFAULT);
  2074. RTLW81_WRITE_REGISTER8(Device,
  2075. Rtlw81RegisterAggregateBreakTime,
  2076. RTLW81_AGGREGATE_BREAK_TIME_DEFAULT);
  2077. RTLW81_WRITE_REGISTER16(Device,
  2078. Rtlw81RegisterMaxAggregationNumber,
  2079. RTLW81_MAX_AGGREGATION_NUMBER_DEFAULT);
  2080. RTLW81_WRITE_REGISTER8(Device,
  2081. Rtlw81RegisterBeaconMaxError,
  2082. RTLW81_BEACON_MAX_ERROR_DEFAULT);
  2083. }
  2084. //
  2085. // Load the device firmware.
  2086. //
  2087. Status = Rtlw81pInitializeFirmware(Device, Irp);
  2088. if (!KSUCCESS(Status)) {
  2089. goto InitializeEnd;
  2090. }
  2091. Device->InitializationPhase = 1;
  2092. //
  2093. // Phase 1 kicks off where phase 0 left off by finishing the firmware load.
  2094. //
  2095. } else {
  2096. ASSERT(Device->InitializationPhase == 1);
  2097. //
  2098. // Finish loading the device firmware.
  2099. //
  2100. Status = Rtlw81pInitializeFirmware(Device, Irp);
  2101. if (!KSUCCESS(Status)) {
  2102. goto InitializeEnd;
  2103. }
  2104. //
  2105. // Initialize the MAC.
  2106. //
  2107. if ((Device->Flags & RTLW81_FLAG_8188E) != 0) {
  2108. MacRegisterCount = RTLW81_ARRAY_COUNT(Rtlw8188eMacRegisters);
  2109. for (Index = 0; Index < MacRegisterCount; Index += 1) {
  2110. RTLW81_WRITE_REGISTER8(Device,
  2111. Rtlw8188eMacRegisters[Index],
  2112. Rtlw8188eMacValues[Index]);
  2113. }
  2114. RTLW81_WRITE_REGISTER8(Device,
  2115. Rtlw81RegisterMaxAggregationNumber,
  2116. RTLW81_MAX_AGGREGATION_NUMBER_8188E_DEFAULT);
  2117. } else {
  2118. MacRegisterCount = RTLW81_ARRAY_COUNT(RtlwDefaultMacRegisters);
  2119. for (Index = 0; Index < MacRegisterCount; Index += 1) {
  2120. RTLW81_WRITE_REGISTER8(Device,
  2121. RtlwDefaultMacRegisters[Index],
  2122. RtlwDefaultMacValues[Index]);
  2123. }
  2124. }
  2125. //
  2126. // Enable BB and RF.
  2127. //
  2128. Value = RTLW81_READ_REGISTER16(Device, Rtlw81RegisterSysFunctionEnable);
  2129. Value |= RTLW81_SYS_FUNCTION_ENABLE_BBRSTB |
  2130. RTLW81_SYS_FUNCTION_ENABLE_BB_GLB_RST |
  2131. RTLW81_SYS_FUNCTION_ENABLE_DIO_RF;
  2132. RTLW81_WRITE_REGISTER16(Device, Rtlw81RegisterSysFunctionEnable, Value);
  2133. if ((Device->Flags & RTLW81_FLAG_8188E) == 0) {
  2134. RTLW81_WRITE_REGISTER16(Device,
  2135. Rtlw81RegisterAfePllControl,
  2136. RTLW81_AFE_PLL_CONTROL_DEFAULT);
  2137. }
  2138. Value = RTLW81_RF_CONTROL_ENABLE |
  2139. RTLW81_RF_CONTROL_RSTB |
  2140. RTLW81_RF_CONTROL_SDMRSTB;
  2141. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterRfControl, Value);
  2142. Value = RTLW81_SYS_FUNCTION_ENABLE_BBRSTB |
  2143. RTLW81_SYS_FUNCTION_ENABLE_BB_GLB_RST |
  2144. RTLW81_SYS_FUNCTION_ENABLE_USBA |
  2145. RTLW81_SYS_FUNCTION_ENABLE_USBD;
  2146. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterSysFunctionEnable, Value);
  2147. if ((Device->Flags & RTLW81_FLAG_8188E) == 0) {
  2148. RTLW81_WRITE_REGISTER8(Device,
  2149. Rtlw81RegisterLdohci12Control,
  2150. RTLW81_LDOHCI_12_CONTROL_DEFAULT);
  2151. RTLW81_WRITE_REGISTER8(Device,
  2152. Rtlw81RegisterTemperatureControl,
  2153. RTLW81_TEMPERATURE_CONTROL_DEFAULT);
  2154. RTLW81_WRITE_REGISTER8(Device,
  2155. Rtlw81RegisterAfeXtalControl1,
  2156. RTLW81_AFE_XTAL_CONTROL1_DEFAULT);
  2157. }
  2158. //
  2159. // Determine which values to use for BB and RF initialization,
  2160. // overriding the defaults where necessary.
  2161. //
  2162. if ((Device->Flags & RTLW81_FLAG_8188E) != 0) {
  2163. DeviceData = &Rtlw8188euDeviceData;
  2164. } else if ((Device->Flags & RTLW81_FLAG_8192C) == 0) {
  2165. if (Device->BoardType == RTLW81_ROM_RF_OPT1_BOARD_TYPE_MINICARD) {
  2166. DeviceData = &Rtlw8188ceDeviceData;
  2167. } else if (Device->BoardType ==
  2168. RTLW81_ROM_RF_OPT1_BOARD_TYPE_HIGHPA) {
  2169. DeviceData = &Rtlw8188ruDeviceData;
  2170. } else {
  2171. DeviceData = &Rtlw8188cuDeviceData;
  2172. }
  2173. } else {
  2174. if (Device->BoardType == RTLW81_ROM_RF_OPT1_BOARD_TYPE_MINICARD) {
  2175. DeviceData = &Rtlw8192ceDeviceData;
  2176. } else {
  2177. DeviceData = &Rtlw8192cuDeviceData;
  2178. }
  2179. }
  2180. //
  2181. // Program the BB.
  2182. //
  2183. for (Index = 0; Index < DeviceData->BbCount; Index += 1) {
  2184. RTLW81_WRITE_REGISTER32(Device,
  2185. DeviceData->BbRegisters[Index],
  2186. DeviceData->BbValues[Index]);
  2187. HlBusySpin(1000);
  2188. }
  2189. //
  2190. // Handle special initialization for an 8192C chip that only has 1
  2191. // transmit chain.
  2192. //
  2193. if ((Device->Flags & RTLW81_FLAG_8192C_1T2R) != 0) {
  2194. Value = RTLW81_READ_REGISTER32(Device,
  2195. Rtlw81RegisterFpga0TransmitInfo);
  2196. Value &= ~RTLW81_FPGA0_TRANSMIT_INFO_INIT1_MASK;
  2197. Value |= RTLW81_FPGA0_TRANSMIT_INFO_INIT1_VALUE;
  2198. RTLW81_WRITE_REGISTER32(Device,
  2199. Rtlw81RegisterFpga0TransmitInfo,
  2200. Value);
  2201. Value = RTLW81_READ_REGISTER32(Device,
  2202. Rtlw81RegisterFpga1TransmitInfo);
  2203. Value &= ~RTLW81_FPGA0_TRANSMIT_INFO_INIT2_MASK;
  2204. Value |= RTLW81_FPGA0_TRANSMIT_INFO_INIT2_VALUE;
  2205. RTLW81_WRITE_REGISTER32(Device,
  2206. Rtlw81RegisterFpga1TransmitInfo,
  2207. Value);
  2208. Value = RTLW81_READ_REGISTER32(Device,
  2209. Rtlw81RegisterCck0AfeSetting);
  2210. Value &= ~RTLW81_CCK0_AFE_SETTING_INIT_MASK;
  2211. Value |= RTLW81_CCK0_AFE_SETTING_INIT_VALUE;
  2212. RTLW81_WRITE_REGISTER32(Device,
  2213. Rtlw81RegisterCck0AfeSetting,
  2214. Value);
  2215. Value = RTLW81_READ_REGISTER32(
  2216. Device,
  2217. Rtlw81RegisterOfdm0TransmitPathEnable);
  2218. Value &= ~RTLW81_OFDM0_TRANSMIT_PATH_ENABLE_INIT_MASK;
  2219. Value |= RTLW81_OFDM0_TRANSMIT_PATH_ENABLE_INIT_VALUE;
  2220. RTLW81_WRITE_REGISTER32(Device,
  2221. Rtlw81RegisterOfdm0TransmitPathEnable,
  2222. Value);
  2223. Value = RTLW81_READ_REGISTER32(Device,
  2224. Rtlw81RegisterOfdm0AgcParam1);
  2225. Value &= ~RTLW81_OFDM0_AGC_PARAM1_INIT_MASK;
  2226. Value |= RTLW81_OFDM0_AGC_PARAM1_INIT_VALUE;
  2227. RTLW81_WRITE_REGISTER32(Device,
  2228. Rtlw81RegisterOfdm0AgcParam1,
  2229. Value);
  2230. Value = RTLW81_READ_REGISTER32(Device,
  2231. Rtlw81Register8192c1T2RInit0);
  2232. Value &= ~RTLW81_8192C_1T2R_INIT_MASK;
  2233. Value |= RTLW81_8192C_1T2R_INIT_VALUE;
  2234. RTLW81_WRITE_REGISTER32(Device,
  2235. Rtlw81Register8192c1T2RInit0,
  2236. Value);
  2237. Value = RTLW81_READ_REGISTER32(Device,
  2238. Rtlw81Register8192c1T2RInit1);
  2239. Value &= ~RTLW81_8192C_1T2R_INIT_MASK;
  2240. Value |= RTLW81_8192C_1T2R_INIT_VALUE;
  2241. RTLW81_WRITE_REGISTER32(Device,
  2242. Rtlw81Register8192c1T2RInit1,
  2243. Value);
  2244. Value = RTLW81_READ_REGISTER32(Device,
  2245. Rtlw81Register8192c1T2RInit2);
  2246. Value &= ~RTLW81_8192C_1T2R_INIT_MASK;
  2247. Value |= RTLW81_8192C_1T2R_INIT_VALUE;
  2248. RTLW81_WRITE_REGISTER32(Device,
  2249. Rtlw81Register8192c1T2RInit2,
  2250. Value);
  2251. Value = RTLW81_READ_REGISTER32(Device,
  2252. Rtlw81Register8192c1T2RInit3);
  2253. Value &= ~RTLW81_8192C_1T2R_INIT_MASK;
  2254. Value |= RTLW81_8192C_1T2R_INIT_VALUE;
  2255. RTLW81_WRITE_REGISTER32(Device,
  2256. Rtlw81Register8192c1T2RInit3,
  2257. Value);
  2258. Value = RTLW81_READ_REGISTER32(Device,
  2259. Rtlw81Register8192c1T2RInit5);
  2260. Value &= ~RTLW81_8192C_1T2R_INIT_MASK;
  2261. Value |= RTLW81_8192C_1T2R_INIT_VALUE;
  2262. RTLW81_WRITE_REGISTER32(Device,
  2263. Rtlw81Register8192c1T2RInit5,
  2264. Value);
  2265. }
  2266. //
  2267. // Set the AGC initialization values.
  2268. //
  2269. for (Index = 0; Index < DeviceData->AgcCount; Index += 1) {
  2270. RTLW81_WRITE_REGISTER32(Device,
  2271. Rtlw81RegisterOfdm0AgcrsstiTable,
  2272. DeviceData->AgcValues[Index]);
  2273. HlBusySpin(1000);
  2274. }
  2275. if ((Device->Flags & RTLW81_FLAG_8188E) != 0) {
  2276. RTLW81_WRITE_REGISTER32(Device,
  2277. Rtlw81RegisterOfdm0AgcCore1,
  2278. RTLW81_OFDM0_AGC_CORE1_INIT1);
  2279. HlBusySpin(1000);
  2280. RTLW81_WRITE_REGISTER32(Device,
  2281. Rtlw81RegisterOfdm0AgcCore1,
  2282. RTLW81_OFDM0_AGC_CORE1_INIT2);
  2283. HlBusySpin(1000);
  2284. Value = RTLW81_READ_REGISTER32(Device,
  2285. Rtlw81RegisterAfeXtalControl0);
  2286. Value &= ~(RTLW81_AFE_XTAL_CONTROL_ADDRESS1_MASK |
  2287. RTLW81_AFE_XTAL_CONTROL_ADDRESS2_MASK);
  2288. Value |= (Device->CrystalCapability <<
  2289. RTLW81_AFE_XTAL_CONTROL_ADDRESS1_SHIFT);
  2290. Value |= (Device->CrystalCapability <<
  2291. RTLW81_AFE_XTAL_CONTROL_ADDRESS2_SHIFT);
  2292. RTLW81_WRITE_REGISTER32(Device,
  2293. Rtlw81RegisterAfeXtalControl0,
  2294. Value);
  2295. } else {
  2296. Value = RTLW81_READ_REGISTER32(Device,
  2297. Rtlw81RegisterHssiParameter2);
  2298. if ((Value & RTLW81_HSSI_PARAMETER2_CCK_HIGH_POWER) != 0) {
  2299. Device->Flags |= RTLW81_FLAG_CCK_HIGH_POWER;
  2300. }
  2301. }
  2302. //
  2303. // Program the RF.
  2304. //
  2305. for (Chain = 0; Chain < Device->ReceiveChainCount; Chain += 1) {
  2306. //
  2307. // Prepare the chain for the programming of the RF values.
  2308. //
  2309. Shift = (Chain % 2) * 16;
  2310. Register = Rtlw81RegisterFpga0RfSoftwareInterface +
  2311. ((Chain / 2) * 4);
  2312. Value = RTLW81_READ_REGISTER32(Device, Register);
  2313. Type = (Value >> Shift) & RTLW81_FPGA0_RF_SOFTWARE_INTERFACE_TYPE;
  2314. //
  2315. // Enable the RF environment.
  2316. //
  2317. Register = Rtlw81RegisterFpga0RfOeInterface + (Chain * 4);
  2318. Value = RTLW81_READ_REGISTER32(Device, Register);
  2319. Value |= RTLW81_FPGA0_RF_OE_INTERFACE_ENABLE;
  2320. RTLW81_WRITE_REGISTER32(Device, Register, Value);
  2321. HlBusySpin(1000);
  2322. Value = RTLW81_READ_REGISTER32(Device, Register);
  2323. Value |= RTLW81_FPGA0_RF_OE_INTERFACE_HIGH_OUTPUT;
  2324. RTLW81_WRITE_REGISTER32(Device, Register, Value);
  2325. HlBusySpin(1000);
  2326. //
  2327. // Set the RF register address and data lengths.
  2328. //
  2329. Register = Rtlw81RegisterHssiParameter2 + (Chain * 8);
  2330. Value = RTLW81_READ_REGISTER32(Device, Register);
  2331. Value &= ~RTLW81_HSSI_PARAMETER2_ADDRESS_LENGTH;
  2332. RTLW81_WRITE_REGISTER32(Device, Register, Value);
  2333. HlBusySpin(1000);
  2334. Value = RTLW81_READ_REGISTER32(Device, Register);
  2335. Value &= ~RTLW81_HSSI_PARAMETER2_DATA_LENGTH;
  2336. RTLW81_WRITE_REGISTER32(Device, Register, Value);
  2337. HlBusySpin(1000);
  2338. //
  2339. // Program the RF values to this chain.
  2340. //
  2341. for (Index = 0; Index < DeviceData->RfCount[Chain]; Index += 1) {
  2342. RfRegister = DeviceData->RfRegisters[Chain][Index];
  2343. if ((RfRegister >= RTLW81_RF_REGISTER_DELAY_VALUE_MIN) &&
  2344. (RfRegister <= RTLW81_RF_REGISTER_DELAY_VALUE_MAX)) {
  2345. HlBusySpin(50 * MICROSECONDS_PER_MILLISECOND);
  2346. continue;
  2347. }
  2348. Rtlw81pWriteRfRegister(Device,
  2349. Chain,
  2350. RfRegister,
  2351. DeviceData->RfValues[Chain][Index]);
  2352. HlBusySpin(1000);
  2353. }
  2354. Register = Rtlw81RegisterFpga0RfSoftwareInterface +
  2355. ((Chain / 2) * 4);
  2356. Value = RTLW81_READ_REGISTER32(Device, Register);
  2357. Value &= ~(RTLW81_FPGA0_RF_SOFTWARE_INTERFACE_TYPE << Shift);
  2358. Value |= Type << Shift;
  2359. RTLW81_WRITE_REGISTER32(Device, Register, Value);
  2360. }
  2361. //
  2362. // Program RF receive state on 8188 UMC-A chips.
  2363. //
  2364. if ((Device->Flags & (RTLW81_FLAG_8192C | RTLW81_FLAG_UMC_A_CUT)) ==
  2365. RTLW81_FLAG_UMC_A_CUT) {
  2366. Rtlw81pWriteRfRegister(Device,
  2367. 0,
  2368. Rtlw81RfRegisterReceiveG1,
  2369. RTLW81_RF_RECEIVE_G1_DEFAULT);
  2370. Rtlw81pWriteRfRegister(Device,
  2371. 0,
  2372. Rtlw81RfRegisterReceiveG2,
  2373. RTLW81_RF_RECEIVE_G2_DEFAULT);
  2374. }
  2375. //
  2376. // Enable MAC transmit and receive on RTL8188E devices.
  2377. //
  2378. if ((Device->Flags & RTLW81_FLAG_8188E) != 0) {
  2379. Value = RTLW81_READ_REGISTER16(Device, Rtlw81RegisterConfiguration);
  2380. Value |= RTLW81_CONFIGURATION_MAC_TRANSMIT_ENABLE |
  2381. RTLW81_CONFIGURATION_MAC_RECEIVE_ENABLE;
  2382. RTLW81_WRITE_REGISTER16(Device, Rtlw81RegisterConfiguration, Value);
  2383. }
  2384. //
  2385. // Turn CCK and OFDM blocks on.
  2386. //
  2387. Value = RTLW81_READ_REGISTER32(Device, Rtlw81RegisterFpga0Rfmod);
  2388. Value |= RTLW81_RFMOD_CCK_ENABLE;
  2389. RTLW81_WRITE_REGISTER32(Device, Rtlw81RegisterFpga0Rfmod, Value);
  2390. Value = RTLW81_READ_REGISTER32(Device, Rtlw81RegisterFpga0Rfmod);
  2391. Value |= RTLW81_RFMOD_OFDM_ENABLE;
  2392. RTLW81_WRITE_REGISTER32(Device, Rtlw81RegisterFpga0Rfmod, Value);
  2393. //
  2394. // Clear per-station keys table.
  2395. //
  2396. Value = RTLW81_CAM_COMMAND_CLEAR | RTLW81_CAM_COMMAND_POLLING;
  2397. RTLW81_WRITE_REGISTER32(Device, Rtlw81RegisterCamCommand, Value);
  2398. //
  2399. // Enable hardware sequencing numbering.
  2400. //
  2401. RTLW81_WRITE_REGISTER8(Device,
  2402. Rtlw81RegisterHardwareSequencingControl,
  2403. RTW81_HARDWARE_SEQUENCING_CONTROL_DEFAULT);
  2404. //
  2405. // LC Calibration.
  2406. //
  2407. Rtlw81pLcCalibration(Device);
  2408. //
  2409. // Fix USB interface issues.
  2410. //
  2411. if ((Device->Flags & RTLW81_FLAG_8188E) == 0) {
  2412. RTLW81_WRITE_REGISTER8(Device,
  2413. Rtlw81RegisterUsbInterference0,
  2414. RTLW81_USB_INTERFERENCE0_DEFAULT);
  2415. RTLW81_WRITE_REGISTER8(Device,
  2416. Rtlw81RegisterUsbInterference1,
  2417. RLTW81_USB_INTERFERENCE1_DEFAULT);
  2418. RTLW81_WRITE_REGISTER8(Device,
  2419. Rtlw81RegisterUsbInterference2,
  2420. RTLW81_USB_INTERFERENCE2_DEFAULT);
  2421. //
  2422. // PA Bias init.
  2423. //
  2424. PaSetting = Device->PaSetting;
  2425. for (Index = 0; Index < Device->ReceiveChainCount; Index += 1) {
  2426. if ((PaSetting & (1 << Index)) != 0) {
  2427. continue;
  2428. }
  2429. Rtlw81pWriteRfRegister(Device,
  2430. Index,
  2431. Rtlw81RfRegisterIpa,
  2432. RTLW81_RF_IPA_INIT0);
  2433. Rtlw81pWriteRfRegister(Device,
  2434. Index,
  2435. Rtlw81RfRegisterIpa,
  2436. RTLW81_RF_IPA_INIT1);
  2437. Rtlw81pWriteRfRegister(Device,
  2438. Index,
  2439. Rtlw81RfRegisterIpa,
  2440. RTLW81_RF_IPA_INIT2);
  2441. Rtlw81pWriteRfRegister(Device,
  2442. Index,
  2443. Rtlw81RfRegisterIpa,
  2444. RTLW81_RF_IPA_INIT3);
  2445. }
  2446. if ((PaSetting & RTLW81_PA_SETTING_INIT_BIT) == 0) {
  2447. Value = RTLW81_READ_REGISTER8(Device, Rtlw81RegisterPaSetting);
  2448. Value &= ~RTLW81_PA_SETTING_INIT_MASK;
  2449. Value |= RTLW81_PA_SETTING_INIT_VALUE;
  2450. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterPaSetting, Value);
  2451. }
  2452. }
  2453. //
  2454. // Intialize GPIO settings.
  2455. //
  2456. Value = RTLW81_READ_REGISTER8(Device, Rtlw81RegisterGpioMuxConfig);
  2457. Value &= ~RTLW81_GPIO_MUX_CONFIG_ENABLE_BT;
  2458. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterGpioMuxConfig, Value);
  2459. //
  2460. // Fix for lower temperature.
  2461. //
  2462. if ((Device->Flags & RTLW81_FLAG_8188E) == 0) {
  2463. RTLW81_WRITE_REGISTER8(Device,
  2464. Rtlw81RegisterTemperatureControl,
  2465. RTLW81_TEMPERATURE_CONTROL_DEFAULT);
  2466. }
  2467. //
  2468. // Set the default channel to start.
  2469. //
  2470. Rtlw81pSetChannel(Device, RTLW81_DEFAULT_CHANNEL);
  2471. //
  2472. // Start the Bulk Receive USB transfers.
  2473. //
  2474. if (KSUCCESS(Device->InitializationStatus)) {
  2475. Rtlw81pSetLed(Device, TRUE);
  2476. //
  2477. // Create the core networking device.
  2478. //
  2479. Status = Rtlw81pAddNetworkDevice(Device);
  2480. if (!KSUCCESS(Status)) {
  2481. goto InitializeEnd;
  2482. }
  2483. Status = Rtlw81pSubmitBulkInTransfers(Device);
  2484. if (!KSUCCESS(Status)) {
  2485. goto InitializeEnd;
  2486. }
  2487. }
  2488. }
  2489. InitializeEnd:
  2490. if (KSUCCESS(Status)) {
  2491. Status = Device->InitializationStatus;
  2492. }
  2493. return Status;
  2494. }
  2495. VOID
  2496. Rtlw81pDestroyBulkOutTransfers (
  2497. PRTLW81_DEVICE Device
  2498. )
  2499. /*++
  2500. Routine Description:
  2501. This routine destroys the RTLW815xx device's bulk out tranfers.
  2502. Arguments:
  2503. Device - Supplies a pointer to the device.
  2504. Return Value:
  2505. None.
  2506. --*/
  2507. {
  2508. PLIST_ENTRY FreeList;
  2509. ULONG Index;
  2510. PRTLW81_BULK_OUT_TRANSFER Rtlw81Transfer;
  2511. for (Index = 0; Index < RTLW81_MAX_BULK_OUT_ENDPOINT_COUNT; Index += 1) {
  2512. FreeList = &(Device->BulkOutFreeTransferList[Index]);
  2513. while (LIST_EMPTY(FreeList) == FALSE) {
  2514. Rtlw81Transfer = LIST_VALUE(FreeList->Next,
  2515. RTLW81_BULK_OUT_TRANSFER,
  2516. ListEntry);
  2517. ASSERT(Rtlw81Transfer->Packet == NULL);
  2518. LIST_REMOVE(&(Rtlw81Transfer->ListEntry));
  2519. UsbDestroyTransfer(Rtlw81Transfer->UsbTransfer);
  2520. MmFreePagedPool(Rtlw81Transfer);
  2521. }
  2522. }
  2523. return;
  2524. }
  2525. //
  2526. // --------------------------------------------------------- Internal Functions
  2527. //
  2528. KSTATUS
  2529. Rtlw81pReadRom (
  2530. PRTLW81_DEVICE Device
  2531. )
  2532. /*++
  2533. Routine Description:
  2534. This routine reads and saves the RTLW81xx device's ROM.
  2535. Arguments:
  2536. Device - Supplies a pointer to the RTLW81 device.
  2537. Return Value:
  2538. Status code.
  2539. --*/
  2540. {
  2541. ULONG Address;
  2542. PRTLW81_POWER_DEFAULT DefaultPower;
  2543. UCHAR Diff;
  2544. UCHAR EfuseValue;
  2545. ULONG Index;
  2546. ULONG Mask;
  2547. ULONG Offset;
  2548. PUCHAR Rom;
  2549. ULONG RomSize;
  2550. PRTLW81_POWER_8188E Rtlw8188ePower;
  2551. ULONG Value;
  2552. //
  2553. // Allocate a buffer to hold the ROM data.
  2554. //
  2555. RomSize = RTLW81_DEFAULT_ROM_SIZE;
  2556. if ((Device->Flags & RTLW81_FLAG_8188E) != 0) {
  2557. RomSize = RTLW81_8188E_ROM_SIZE;
  2558. }
  2559. Rom = MmAllocatePagedPool(RomSize, RTLW81_ALLOCATION_TAG);
  2560. if (Rom == NULL) {
  2561. return STATUS_INSUFFICIENT_RESOURCES;
  2562. }
  2563. //
  2564. // Enable EFUSE access.
  2565. //
  2566. RTLW81_WRITE_REGISTER8(Device,
  2567. Rtlw81RegisterEfuseAccess,
  2568. RTLW81_EFUSE_ACCESS_ON);
  2569. Value = RTLW81_READ_REGISTER16(Device, Rtlw81RegisterSysIsoControl);
  2570. if ((Value & RTLW81_SYS_ISO_CONTROL_PWC_EV12V) == 0) {
  2571. Value |= RTLW81_SYS_ISO_CONTROL_PWC_EV12V;
  2572. RTLW81_WRITE_REGISTER16(Device, Rtlw81RegisterSysIsoControl, Value);
  2573. }
  2574. Value = RTLW81_READ_REGISTER16(Device, Rtlw81RegisterSysFunctionEnable);
  2575. if ((Value & RTLW81_SYS_FUNCTION_ENABLE_ELDR) == 0) {
  2576. Value |= RTLW81_SYS_FUNCTION_ENABLE_ELDR;
  2577. RTLW81_WRITE_REGISTER16(Device, Rtlw81RegisterSysFunctionEnable, Value);
  2578. }
  2579. Mask = RTLW81_SYS_CLOCK_LOADER_ENABLE | RTLW81_SYS_CLOCK_ANA8M;
  2580. Value = RTLW81_READ_REGISTER16(Device, Rtlw81RegisterSysClock);
  2581. if ((Value & Mask) != Mask) {
  2582. Value |= Mask;
  2583. RTLW81_WRITE_REGISTER16(Device, Rtlw81RegisterSysClock, Value);
  2584. }
  2585. //
  2586. // Read the entire ROM.
  2587. //
  2588. Address = 0;
  2589. RtlSetMemory(Rom, RTLW81_EFUSE_INVALID, RomSize);
  2590. while (Address < RTLW81_EFUSE_MAX_ADDRESS) {
  2591. EfuseValue = Rtlw81pEfuseRead8(Device, Address);
  2592. if (EfuseValue == RTLW81_EFUSE_INVALID) {
  2593. break;
  2594. }
  2595. Address += 1;
  2596. if ((EfuseValue & RTLW81_EFUSE_ENCODING_MASK) ==
  2597. RTLW81_EFUSE_ENCODING_EXTENDED) {
  2598. Offset = (EfuseValue & RTLW81_EFUSE_EXTENDED_FIRST_OFFSET_MASK) >>
  2599. RTLW81_EFUSE_EXTENDED_FIRST_OFFSET_SHIFT;
  2600. EfuseValue = Rtlw81pEfuseRead8(Device, Address);
  2601. if ((EfuseValue & RTLW81_EFUSE_EXTENDED_ENCODING_MASK) !=
  2602. RTLW81_EFUSE_EXTENDED_ENCODING_NO_OFFSET) {
  2603. Offset |= (EfuseValue &
  2604. RTLW81_EFUSE_EXTENDED_SECOND_OFFSET_MASK) >>
  2605. RTLW81_EFUSE_EXTENDED_SECOND_OFFSET_SHIFT;
  2606. }
  2607. Address += 1;
  2608. } else {
  2609. Offset = (EfuseValue & RTLW81_EFUSE_DEFAULT_OFFSET_MASK) >>
  2610. RTLW81_EFUSE_DEFAULT_OFFSET_SHIFT;
  2611. }
  2612. Mask = EfuseValue & RTLW81_EFUSE_VALID_MASK;
  2613. for (Index = 0; Index < 4; Index += 1) {
  2614. if ((Mask & 0x1) == 0) {
  2615. EfuseValue = Rtlw81pEfuseRead8(Device, Address);
  2616. Rom[Offset * 8 + Index * 2] = EfuseValue;
  2617. Address += 1;
  2618. EfuseValue = Rtlw81pEfuseRead8(Device, Address);
  2619. Rom[Offset * 8 + Index * 2 + 1] = EfuseValue;
  2620. Address += 1;
  2621. }
  2622. Mask >>= 1;
  2623. }
  2624. }
  2625. //
  2626. // Store the PA setting for non-8188E devices. It is beyond the end of the
  2627. // rest of the ROM.
  2628. //
  2629. if ((Device->Flags & RTLW81_FLAG_8188E) == 0) {
  2630. EfuseValue = Rtlw81pEfuseRead8(Device, Rtlw81EfuseRegisterPaSetting);
  2631. Device->PaSetting = EfuseValue;
  2632. }
  2633. //
  2634. // Disable EFUSE access.
  2635. //
  2636. RTLW81_WRITE_REGISTER8(Device,
  2637. Rtlw81RegisterEfuseAccess,
  2638. RTLW81_EFUSE_ACCESS_OFF);
  2639. //
  2640. // Cache any values based on the device type as the ROMs are formatted a
  2641. // little differently.
  2642. //
  2643. if ((Device->Flags & RTLW81_FLAG_8188E) != 0) {
  2644. Rtlw8188ePower = &(Device->Power.Rtlw8188e);
  2645. RtlCopyMemory(Rtlw8188ePower->CckTransmitPower,
  2646. &(Rom[RTLW81_8188E_ROM_CCK_TRANSMIT_POWER_OFFSET]),
  2647. sizeof(Rtlw8188ePower->CckTransmitPower));
  2648. RtlCopyMemory(Rtlw8188ePower->Ht40TransmitPower,
  2649. &(Rom[RTLW81_8188E_ROM_HT_40_TRANSMIT_POWER_OFFSET]),
  2650. sizeof(Rtlw8188ePower->Ht40TransmitPower));
  2651. Diff = Rom[RTLW81_8188E_ROM_POWER_OPTION_OFFSET];
  2652. Diff &= RTLW81_8188E_ROM_POWER_OPTION_BW_20_MASK;
  2653. Diff >>= RTLW81_8188E_ROM_POWER_OPTION_BW_20_SHIFT;
  2654. if ((Diff & RTLW81_8188E_ROM_POWER_OPTION_HIGH_BITS_SET) != 0) {
  2655. Diff |= RTLW81_8188E_ROM_POWER_OPTION_HIGH_BITS;
  2656. }
  2657. Rtlw8188ePower->Bw20TransmitPowerDiff = Diff;
  2658. Diff = Rom[RTLW81_8188E_ROM_POWER_OPTION_OFFSET];
  2659. Diff &= RTLW81_8188E_ROM_POWER_OPTION_OFDM_MASK;
  2660. Diff >>= RTLW81_8188E_ROM_POWER_OPTION_OFDM_SHIFT;
  2661. if ((Diff & RTLW81_8188E_ROM_POWER_OPTION_HIGH_BITS_SET) != 0) {
  2662. Diff |= RTLW81_8188E_ROM_POWER_OPTION_HIGH_BITS;
  2663. }
  2664. Rtlw8188ePower->OfdmTransmitPowerDiff = Diff;
  2665. Device->BoardType = Rom[RTLW81_8188E_ROM_RF_OPT1_OFFSET];
  2666. Device->Regulatory = Rom[RTLW81_8188E_ROM_RF_OPT1_OFFSET];
  2667. Device->CrystalCapability =
  2668. Rom[RTLW81_8188E_ROM_CRYSTAL_CAPABILITY_OFFSET];
  2669. if (Device->CrystalCapability ==
  2670. RTLW81_8188E_ROM_CRYSTAL_CAPABILITY_INVALID) {
  2671. Device->CrystalCapability =
  2672. RTLW81_8188E_ROM_CRYSTAL_CAPABILITY_DEFAULT;
  2673. }
  2674. Device->CrystalCapability &= RTLW81_8188E_ROM_CRYSTAL_CAPABILITY_MASK;
  2675. RtlCopyMemory(Device->MacAddress,
  2676. &(Rom[RTLW81_8188E_ROM_MAC_ADDRESS_OFFSET]),
  2677. sizeof(Device->MacAddress));
  2678. } else {
  2679. DefaultPower = &(Device->Power.Default);
  2680. RtlCopyMemory(DefaultPower->CckTransmitPower,
  2681. &(Rom[RTLW81_DEFAULT_ROM_CCK_TRANSMIT_POWER_OFFSET]),
  2682. sizeof(DefaultPower->CckTransmitPower));
  2683. RtlCopyMemory(DefaultPower->Ht40TransmitPower,
  2684. &(Rom[RTLW81_DEFAULT_ROM_HT_40_TRANSMIT_POWER_OFFSET]),
  2685. sizeof(DefaultPower->Ht40TransmitPower));
  2686. RtlCopyMemory(
  2687. DefaultPower->Ht40TransmitPowerDiff,
  2688. &(Rom[RTLW81_DEFAULT_ROM_HT_40_TRANSMIT_POWER_DIFF_OFFSET]),
  2689. sizeof(DefaultPower->Ht40TransmitPowerDiff));
  2690. RtlCopyMemory(DefaultPower->Ht40MaxPower,
  2691. &(Rom[RTLW81_DEFAULT_ROM_HT_40_MAX_POWER_OFFSET]),
  2692. sizeof(DefaultPower->Ht40MaxPower));
  2693. RtlCopyMemory(
  2694. DefaultPower->Ht20TransmitPowerDiff,
  2695. &(Rom[RTLW81_DEFAULT_ROM_HT_20_TRANSMIT_POWER_DIFF_OFFSET]),
  2696. sizeof(DefaultPower->Ht20TransmitPowerDiff));
  2697. RtlCopyMemory(DefaultPower->Ht20MaxPower,
  2698. &(Rom[RTLW81_DEFAULT_ROM_HT_20_MAX_POWER_OFFSET]),
  2699. sizeof(DefaultPower->Ht20MaxPower));
  2700. RtlCopyMemory(
  2701. DefaultPower->OfdmTransmitPowerDiff,
  2702. &(Rom[RTLW81_DEFAULT_ROM_OFDM_TRANSMIT_POWER_DIFF_OFFSET]),
  2703. sizeof(DefaultPower->OfdmTransmitPowerDiff));
  2704. RtlCopyMemory(Device->MacAddress,
  2705. &(Rom[RTLW81_DEFAULT_ROM_MAC_ADDRESS_OFFSET]),
  2706. sizeof(Device->MacAddress));
  2707. Device->BoardType = Rom[RTLW81_DEFAULT_ROM_RF_OPT1_OFFSET];
  2708. Device->Regulatory = Rom[RTLW81_DEFAULT_ROM_RF_OPT1_OFFSET];
  2709. }
  2710. Device->BoardType &= RTLW81_ROM_RF_OPT1_BOARD_TYPE_MASK;
  2711. Device->BoardType >>= RTLW81_ROM_RF_OPT1_BOARD_TYPE_SHIFT;
  2712. Device->Regulatory &= RTLW81_ROM_RF_OPT1_REGULATORY_MASK;
  2713. Device->Regulatory >>= RTLW81_ROM_RF_OPT1_REGULATORY_SHIFT;
  2714. MmFreePagedPool(Rom);
  2715. return STATUS_SUCCESS;
  2716. }
  2717. KSTATUS
  2718. Rtlw81pDefaultInitialize (
  2719. PRTLW81_DEVICE Device
  2720. )
  2721. /*++
  2722. Routine Description:
  2723. This routine initializes and enables a default RTL81xx wireless device.
  2724. Arguments:
  2725. Device - Supplies a pointer to the device.
  2726. Return Value:
  2727. Status code.
  2728. --*/
  2729. {
  2730. ULONGLONG CurrentTime;
  2731. KSTATUS Status;
  2732. ULONGLONG Timeout;
  2733. ULONGLONG TimeoutTicks;
  2734. ULONG Value;
  2735. TimeoutTicks = HlQueryTimeCounterFrequency() * RTLW81_DEVICE_TIMEOUT;
  2736. //
  2737. // Wait for the autoload done bit to be set.
  2738. //
  2739. CurrentTime = KeGetRecentTimeCounter();
  2740. Timeout = CurrentTime + TimeoutTicks;
  2741. do {
  2742. Value = RTLW81_READ_REGISTER8(Device, Rtlw81RegisterApsFsmco);
  2743. if ((Value & RTLW81_APS_FSMCO_PFM_AUTOLOAD_DONE) != 0) {
  2744. break;
  2745. }
  2746. CurrentTime = KeGetRecentTimeCounter();
  2747. } while (CurrentTime <= Timeout);
  2748. if (CurrentTime > Timeout) {
  2749. Status = STATUS_TIMEOUT;
  2750. goto DefaultInitializeEnd;
  2751. }
  2752. //
  2753. // Unlock the ISO, Power, and Clock control register.
  2754. //
  2755. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterRsvControl, 0);
  2756. //
  2757. // Move SPS into PWM mode.
  2758. //
  2759. RTLW81_WRITE_REGISTER8(Device,
  2760. Rtlw81RegisterSps0Control,
  2761. RTLW81_SPS0_CONTROL_DEFAULT);
  2762. HlBusySpin(1000);
  2763. //
  2764. // Make sure LDV12 is enabled.
  2765. //
  2766. Value = RTLW81_READ_REGISTER8(Device, Rtlw81RegisterLdov12dControl);
  2767. if ((Value & RTLW81_LDOV12D_CONTROL_LDV12_ENABLE) == 0) {
  2768. Value |= RTLW81_LDOV12D_CONTROL_LDV12_ENABLE;
  2769. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterLdov12dControl, Value);
  2770. HlBusySpin(1000);
  2771. Value = RTLW81_READ_REGISTER8(Device, Rtlw81RegisterSysIsoControl);
  2772. Value &= ~RTLW81_SYS_ISO_CONTROL_MD2PP;
  2773. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterSysIsoControl, Value);
  2774. }
  2775. //
  2776. // Auto-enable WLAN.
  2777. //
  2778. Value = RTLW81_READ_REGISTER16(Device, Rtlw81RegisterApsFsmco);
  2779. Value |= RTLW81_APS_FSMCO_APFM_ONMAC;
  2780. RTLW81_WRITE_REGISTER16(Device, Rtlw81RegisterApsFsmco, Value);
  2781. CurrentTime = KeGetRecentTimeCounter();
  2782. Timeout = CurrentTime + TimeoutTicks;
  2783. do {
  2784. Value = RTLW81_READ_REGISTER16(Device, Rtlw81RegisterApsFsmco);
  2785. if ((Value & RTLW81_APS_FSMCO_APFM_ONMAC) == 0) {
  2786. break;
  2787. }
  2788. CurrentTime = KeGetRecentTimeCounter();
  2789. } while (CurrentTime <= Timeout);
  2790. if (CurrentTime > Timeout) {
  2791. Status = STATUS_TIMEOUT;
  2792. goto DefaultInitializeEnd;
  2793. }
  2794. //
  2795. // Enable radio, GPIO, and LED functions.
  2796. //
  2797. Value = RTLW81_APS_FSMCO_AFSM_HSUS |
  2798. RTLW81_APS_FSMCO_PDN_EN |
  2799. RTLW81_APS_FSMCO_PFM_AUTOLOAD_DONE;
  2800. RTLW81_WRITE_REGISTER16(Device, Rtlw81RegisterApsFsmco, Value);
  2801. //
  2802. // Release RF digital isolation.
  2803. //
  2804. Value = RTLW81_READ_REGISTER16(Device, Rtlw81RegisterSysIsoControl);
  2805. Value &= ~RTLW81_SYS_ISO_CONTROL_DIOR;
  2806. RTLW81_WRITE_REGISTER16(Device, Rtlw81RegisterSysIsoControl, Value);
  2807. //
  2808. // Initialize the MAC.
  2809. //
  2810. Value = RTLW81_READ_REGISTER8(Device, Rtlw81RegisterApsdControl);
  2811. Value &= ~RTLW81_APSD_CONTROL_OFF;
  2812. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterApsdControl, Value);
  2813. CurrentTime = KeGetRecentTimeCounter();
  2814. Timeout = CurrentTime + TimeoutTicks;
  2815. do {
  2816. Value = RTLW81_READ_REGISTER8(Device, Rtlw81RegisterApsdControl);
  2817. if ((Value & RTLW81_APSD_CONTROL_STATUS_OFF) == 0) {
  2818. break;
  2819. }
  2820. CurrentTime = KeGetRecentTimeCounter();
  2821. } while (CurrentTime <= Timeout);
  2822. if (CurrentTime > Timeout) {
  2823. Status = STATUS_TIMEOUT;
  2824. goto DefaultInitializeEnd;
  2825. }
  2826. //
  2827. // Enable MAC DMA/WMAC/Schedule/SEC blocks.
  2828. //
  2829. Value = RTLW81_READ_REGISTER16(Device, Rtlw81RegisterConfiguration);
  2830. Value |= RTLW81_CONFIGURATION_HCI_TRANSMIT_DMA_ENABLE |
  2831. RTLW81_CONFIGURATION_HCI_RECEIVE_DMA_ENABLE |
  2832. RTLW81_CONFIGURATION_TRANSMIT_DMA_ENABLE |
  2833. RTLW81_CONFIGURATION_RECEIVE_DMA_ENABLE |
  2834. RTLW81_CONFIGURATION_PROTOCOL_ENABLE |
  2835. RTLW81_CONFIGURATION_SCHEDULE_ENABLE |
  2836. RTLW81_CONFIGURATION_MAC_TRANSMIT_ENABLE |
  2837. RTLW81_CONFIGURATION_MAC_RECEIVE_ENABLE |
  2838. RTLW81_CONFIGURATION_SEC_ENABLE;
  2839. RTLW81_WRITE_REGISTER16(Device, Rtlw81RegisterConfiguration, Value);
  2840. //
  2841. // This magic only shows up in FreeBSD. Not Linux.
  2842. //
  2843. RTLW81_WRITE_REGISTER8(Device,
  2844. Rtlw81RegisterUsbEnable,
  2845. RTLW81_USB_ENABLE_DEFAULT);
  2846. Status = STATUS_SUCCESS;
  2847. DefaultInitializeEnd:
  2848. return Status;
  2849. }
  2850. KSTATUS
  2851. Rtlw81p8188eInitialize (
  2852. PRTLW81_DEVICE Device
  2853. )
  2854. /*++
  2855. Routine Description:
  2856. This routine initializes and enables an 8188E RTL81xx wireless device.
  2857. Arguments:
  2858. Device - Supplies a pointer to the device.
  2859. Return Value:
  2860. Status code.
  2861. --*/
  2862. {
  2863. ULONGLONG CurrentTime;
  2864. KSTATUS Status;
  2865. ULONGLONG Timeout;
  2866. ULONGLONG TimeoutTicks;
  2867. ULONG Value;
  2868. TimeoutTicks = HlQueryTimeCounterFrequency() * RTLW81_DEVICE_TIMEOUT;
  2869. //
  2870. // Wait for the autoload done bit to be set.
  2871. //
  2872. CurrentTime = KeGetRecentTimeCounter();
  2873. Timeout = CurrentTime + TimeoutTicks;
  2874. do {
  2875. Value = RTLW81_READ_REGISTER32(Device, Rtlw81RegisterApsFsmco);
  2876. if ((Value & RTLW81_APS_FSMCO_SUS_HOST) != 0) {
  2877. break;
  2878. }
  2879. CurrentTime = KeGetRecentTimeCounter();
  2880. } while (CurrentTime <= Timeout);
  2881. if (CurrentTime > Timeout) {
  2882. Status = STATUS_TIMEOUT;
  2883. goto DefaultInitializeEnd;
  2884. }
  2885. //
  2886. // Reset the BB.
  2887. //
  2888. Value = RTLW81_READ_REGISTER8(Device, Rtlw81RegisterSysFunctionEnable);
  2889. Value &= ~(RTLW81_SYS_FUNCTION_ENABLE_BBRSTB |
  2890. RTLW81_SYS_FUNCTION_ENABLE_BB_GLB_RST);
  2891. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterSysFunctionEnable, Value);
  2892. Value = RTLW81_READ_REGISTER8(Device, Rtlw81RegisterAfeXtalControl2);
  2893. Value |= RTLW81_AFE_XTAL_CONTROL2_ENABLE;
  2894. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterAfeXtalControl2, Value);
  2895. //
  2896. // Disable hardware power down.
  2897. //
  2898. Value = RTLW81_READ_REGISTER16(Device, Rtlw81RegisterApsFsmco);
  2899. Value &= ~RTLW81_APS_FSMCO_APDM_HPDN;
  2900. RTLW81_WRITE_REGISTER16(Device, Rtlw81RegisterApsFsmco, Value);
  2901. //
  2902. // Disable WLAN suspend.
  2903. //
  2904. Value = RTLW81_READ_REGISTER16(Device, Rtlw81RegisterApsFsmco);
  2905. Value &= ~(RTLW81_APS_FSMCO_AFSM_HSUS | RTLW81_APS_FSMCO_AFSM_PCIE);
  2906. RTLW81_WRITE_REGISTER16(Device, Rtlw81RegisterApsFsmco, Value);
  2907. //
  2908. // Auto-enable WLAN.
  2909. //
  2910. Value = RTLW81_READ_REGISTER16(Device, Rtlw81RegisterApsFsmco);
  2911. Value |= RTLW81_APS_FSMCO_APFM_ONMAC;
  2912. RTLW81_WRITE_REGISTER16(Device, Rtlw81RegisterApsFsmco, Value);
  2913. CurrentTime = KeGetRecentTimeCounter();
  2914. Timeout = CurrentTime + TimeoutTicks;
  2915. do {
  2916. Value = RTLW81_READ_REGISTER16(Device, Rtlw81RegisterApsFsmco);
  2917. if ((Value & RTLW81_APS_FSMCO_APFM_ONMAC) == 0) {
  2918. break;
  2919. }
  2920. CurrentTime = KeGetRecentTimeCounter();
  2921. } while (CurrentTime <= Timeout);
  2922. if (CurrentTime > Timeout) {
  2923. Status = STATUS_TIMEOUT;
  2924. goto DefaultInitializeEnd;
  2925. }
  2926. //
  2927. // Enable LDO in normal mode.
  2928. //
  2929. Value = RTLW81_READ_REGISTER8(Device, Rtlw81RegisterLpldoControl);
  2930. Value &= ~RTLW81_LPLDO_CONTROL_DISABLE;
  2931. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterLpldoControl, Value);
  2932. //
  2933. // Enable MAC DMA/WMAC/Schedule/SEC blocks.
  2934. //
  2935. RTLW81_WRITE_REGISTER16(Device, Rtlw81RegisterConfiguration, 0);
  2936. Value = RTLW81_READ_REGISTER16(Device, Rtlw81RegisterConfiguration);
  2937. Value |= RTLW81_CONFIGURATION_HCI_TRANSMIT_DMA_ENABLE |
  2938. RTLW81_CONFIGURATION_HCI_RECEIVE_DMA_ENABLE |
  2939. RTLW81_CONFIGURATION_TRANSMIT_DMA_ENABLE |
  2940. RTLW81_CONFIGURATION_RECEIVE_DMA_ENABLE |
  2941. RTLW81_CONFIGURATION_PROTOCOL_ENABLE |
  2942. RTLW81_CONFIGURATION_SCHEDULE_ENABLE |
  2943. RTLW81_CONFIGURATION_SEC_ENABLE |
  2944. RTLW81_CONFIGURATION_CALTMR_ENABLE;
  2945. RTLW81_WRITE_REGISTER16(Device, Rtlw81RegisterConfiguration, Value);
  2946. Status = STATUS_SUCCESS;
  2947. DefaultInitializeEnd:
  2948. return Status;
  2949. }
  2950. KSTATUS
  2951. Rtlw81pInitializeDma (
  2952. PRTLW81_DEVICE Device
  2953. )
  2954. /*++
  2955. Routine Description:
  2956. This routine initialize the DMA queues for the RTL81xx wireless device.
  2957. Arguments:
  2958. Device - Supplies a pointer to the device.
  2959. Return Value:
  2960. Status code.
  2961. --*/
  2962. {
  2963. ULONG HighQueuePageCount;
  2964. BOOL HighQueuePresent;
  2965. ULONG Index;
  2966. ULONG LowQueuePageCount;
  2967. BOOL LowQueuePresent;
  2968. ULONG NormalQueuePageCount;
  2969. BOOL NormalQueuePresent;
  2970. ULONG PacketCount;
  2971. ULONG PageBoundary;
  2972. ULONG PageCount;
  2973. ULONG PagesPerQueue;
  2974. ULONG PublicQueuePageCount;
  2975. ULONG QueueCount;
  2976. ULONG QueueMask;
  2977. ULONG ReceiveBoundary2;
  2978. ULONG RemainingPages;
  2979. KSTATUS Status;
  2980. ULONG Value;
  2981. if ((Device->Flags & RTLW81_FLAG_8188E) != 0) {
  2982. PageBoundary = RTLW81_8188E_TRANSMIT_PAGE_BOUNDARY;
  2983. PageCount = RTLW81_8188E_TRANSMIT_PAGE_COUNT;
  2984. PacketCount = RTLW81_8188E_TRANSMIT_PACKET_COUNT;
  2985. } else {
  2986. PageBoundary = RTLW81_DEFAULT_TRANSMIT_PAGE_BOUNDARY;
  2987. PageCount = RTLW81_DEFAULT_TRANSMIT_PAGE_COUNT;
  2988. PacketCount = RTLW81_DEFAULT_TRANSMIT_PACKET_COUNT;
  2989. }
  2990. //
  2991. // Initialize the LLT.
  2992. //
  2993. for (Index = 0; Index < PageCount; Index += 1) {
  2994. Status = Rtlw81pWriteLlt(Device, Index, Index + 1);
  2995. if (!KSUCCESS(Status)) {
  2996. goto InitializeDmaEnd;
  2997. }
  2998. }
  2999. Status = Rtlw81pWriteLlt(Device, Index, 0xff);
  3000. if (!KSUCCESS(Status)) {
  3001. goto InitializeDmaEnd;
  3002. }
  3003. for (Index = PageBoundary; Index < (PacketCount - 1); Index += 1) {
  3004. Status = Rtlw81pWriteLlt(Device, Index, Index + 1);
  3005. if (!KSUCCESS(Status)) {
  3006. goto InitializeDmaEnd;
  3007. }
  3008. }
  3009. Status = Rtlw81pWriteLlt(Device, Index, PageBoundary);
  3010. if (!KSUCCESS(Status)) {
  3011. goto InitializeDmaEnd;
  3012. }
  3013. //
  3014. // Figure out the initialization values based on the device type and
  3015. // perform device specific DMA initialization steps.
  3016. //
  3017. HighQueuePresent = FALSE;
  3018. NormalQueuePresent = FALSE;
  3019. LowQueuePresent = FALSE;
  3020. if ((Device->Flags & RTLW81_FLAG_8188E) != 0) {
  3021. PublicQueuePageCount = RTLW81_8188E_PUBLIC_QUEUE_PAGE_COUNT;
  3022. NormalQueuePageCount = RTLW81_8188E_NORMAL_QUEUE_PAGE_COUNT;
  3023. LowQueuePageCount = RTLW81_8188E_LOW_QUEUE_PAGE_COUNT;
  3024. HighQueuePageCount = RTLW81_8188E_HIGH_QUEUE_PAGE_COUNT;
  3025. ReceiveBoundary2 = RTLW81_8188E_RECEIVE_BOUNDARY2;
  3026. RTLW81_WRITE_REGISTER16(Device,
  3027. Rtlw81RegisterNormalQueuePageCount,
  3028. NormalQueuePageCount);
  3029. QueueCount = Device->BulkOutEndpointCount;
  3030. if (QueueCount == 1) {
  3031. LowQueuePresent = TRUE;
  3032. } else if (QueueCount == 2) {
  3033. HighQueuePresent = TRUE;
  3034. NormalQueuePresent = TRUE;
  3035. } else {
  3036. HighQueuePresent = TRUE;
  3037. NormalQueuePresent = TRUE;
  3038. LowQueuePresent = TRUE;
  3039. }
  3040. } else {
  3041. PublicQueuePageCount = RTLW81_DEFAULT_PUBLIC_QUEUE_PAGE_COUNT;
  3042. ReceiveBoundary2 = RTLW81_DEFAULT_RECEIVE_BOUNDARY2;
  3043. //
  3044. // Set the number of pages per queue.
  3045. //
  3046. QueueMask = RTLW81_READ_REGISTER16(Device, Rtlw81RegisterUsbEndpoint);
  3047. QueueCount = 0;
  3048. if ((QueueMask & RTLW81_USB_ENDPOINT_HQ_MASK) != 0) {
  3049. HighQueuePresent = TRUE;
  3050. QueueCount += 1;
  3051. }
  3052. if ((QueueMask & RTLW81_USB_ENDPOINT_NQ_MASK) != 0) {
  3053. NormalQueuePresent = TRUE;
  3054. QueueCount += 1;
  3055. }
  3056. if ((QueueMask & RTLW81_USB_ENDPOINT_LQ_MASK) != 0) {
  3057. LowQueuePresent = TRUE;
  3058. QueueCount += 1;
  3059. }
  3060. PageCount = RTLW81_DEFAULT_TRANSMIT_PAGE_COUNT -
  3061. RTLW81_DEFAULT_PUBLIC_QUEUE_PAGE_COUNT;
  3062. PagesPerQueue = PageCount / QueueCount;
  3063. RemainingPages = PageCount % QueueCount;
  3064. NormalQueuePageCount = PagesPerQueue;
  3065. if ((QueueMask & RTLW81_USB_ENDPOINT_NQ_MASK) == 0) {
  3066. NormalQueuePageCount = 0;
  3067. }
  3068. RTLW81_WRITE_REGISTER8(Device,
  3069. Rtlw81RegisterNormalQueuePageCount,
  3070. NormalQueuePageCount);
  3071. HighQueuePageCount = 0;
  3072. if ((QueueMask & RTLW81_USB_ENDPOINT_HQ_MASK) != 0) {
  3073. HighQueuePageCount = PagesPerQueue + RemainingPages;
  3074. }
  3075. LowQueuePageCount = 0;
  3076. if ((QueueMask & RTLW81_USB_ENDPOINT_LQ_MASK) != 0) {
  3077. LowQueuePageCount = PagesPerQueue;
  3078. }
  3079. }
  3080. Value = (PublicQueuePageCount << RTLW81_QUEUE_PAGE_COUNT_PUBLIC_SHIFT) &
  3081. RTLW81_QUEUE_PAGE_COUNT_PUBLIC_MASK;
  3082. Value |= (HighQueuePageCount << RTLW81_QUEUE_PAGE_COUNT_HIGH_SHIFT) &
  3083. RTLW81_QUEUE_PAGE_COUNT_HIGH_MASK;
  3084. Value |= (LowQueuePageCount << RTLW81_QUEUE_PAGE_COUNT_LOW_SHIFT) &
  3085. RTLW81_QUEUE_PAGE_COUNT_LOW_MASK;
  3086. Value |= RTLW81_QUEUE_PAGE_COUNT_LOAD;
  3087. RTLW81_WRITE_REGISTER32(Device, Rtlw81RegisterQueuePageCount, Value);
  3088. //
  3089. // Initialize the queue boundaries.
  3090. //
  3091. RTLW81_WRITE_REGISTER8(Device,
  3092. Rtlw81RegisterTransmitPacketNormalQueueBoundary,
  3093. PageBoundary);
  3094. RTLW81_WRITE_REGISTER8(Device,
  3095. Rtlw81RegisterTransmitPacketQueueBoundary,
  3096. PageBoundary);
  3097. RTLW81_WRITE_REGISTER8(Device,
  3098. Rtlw81RegisterTransmitPacketWmacLbkBfHd,
  3099. PageBoundary);
  3100. RTLW81_WRITE_REGISTER8(Device,
  3101. Rtlw81RegisterTransmitReceiveBoundary0,
  3102. PageBoundary);
  3103. RTLW81_WRITE_REGISTER8(Device,
  3104. Rtlw81RegisterTransmitDescriptorControl1,
  3105. PageBoundary);
  3106. //
  3107. // Set the queue to USB endpoint mappings.
  3108. //
  3109. Value = RTLW81_READ_REGISTER16(Device, Rtlw81RegisterTransmitReceiveDma);
  3110. Value &= ~RTLW81_TRANSMIT_RECEIVE_DMA_QMAP_MASK;
  3111. if (QueueCount == 1) {
  3112. if (HighQueuePresent != FALSE) {
  3113. Value |= RTLW81_TRANSMIT_RECEIVE_DMA_QMAP_HIGH;
  3114. } else if (NormalQueuePresent != FALSE) {
  3115. Value |= RTLW81_TRANSMIT_RECEIVE_DMA_QMAP_NORMAL;
  3116. } else {
  3117. ASSERT(LowQueuePresent != FALSE);
  3118. Value |= RTLW81_TRANSMIT_RECEIVE_DMA_QMAP_LOW;
  3119. }
  3120. } else if (QueueCount == 2) {
  3121. if (HighQueuePresent == FALSE) {
  3122. Status = STATUS_INVALID_CONFIGURATION;
  3123. goto InitializeDmaEnd;
  3124. }
  3125. if (NormalQueuePresent != FALSE) {
  3126. Value |= RTLW81_TRANSMIT_RECEIVE_DMA_QMAP_HIGH_NORMAL;
  3127. } else {
  3128. ASSERT(LowQueuePresent != FALSE);
  3129. Value |= RTLW81_TRANSMIT_RECEIVE_DMA_QMAP_HIGH_LOW;
  3130. }
  3131. } else {
  3132. Value |= RTLW81_TRANSMIT_RECEIVE_DMA_QMAP_HIGH_NORMAL_LOW;
  3133. }
  3134. RTLW81_WRITE_REGISTER16(Device, Rtlw81RegisterTransmitReceiveDma, Value);
  3135. RTLW81_WRITE_REGISTER16(Device,
  3136. Rtlw81RegisterTransmitReceiveBoundary2,
  3137. ReceiveBoundary2);
  3138. //
  3139. // Set the transmit and receive page sizes.
  3140. //
  3141. Value = ((RTLW81_PAGE_CONFIGURATION_PAGE_SIZE_128 <<
  3142. RTLW81_PAGE_CONFIGURATION_TRANSMIT_PAGE_SIZE_SHIFT) &
  3143. RTLW81_PAGE_CONFIGURATION_TRANSMIT_PAGE_SIZE_MASK) |
  3144. ((RTLW81_PAGE_CONFIGURATION_PAGE_SIZE_128 <<
  3145. RTLW81_PAGE_CONFIGURATION_RECEIVE_PAGE_SIZE_SHIFT) &
  3146. RTLW81_PAGE_CONFIGURATION_RECEIVE_PAGE_SIZE_MASK);
  3147. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterPageConfiguration, Value);
  3148. InitializeDmaEnd:
  3149. return Status;
  3150. }
  3151. VOID
  3152. Rtlw81pFirmwareReset (
  3153. PRTLW81_DEVICE Device
  3154. )
  3155. /*++
  3156. Routine Description:
  3157. This routine issues a firmware reset for the RTLW81xx device.
  3158. Arguments:
  3159. Device - Supplies a pointer to the RTLW81xx device to reset.
  3160. Return Value:
  3161. None.
  3162. --*/
  3163. {
  3164. ULONGLONG CurrentTime;
  3165. ULONGLONG Timeout;
  3166. ULONGLONG TimeoutTicks;
  3167. ULONG Value;
  3168. if ((Device->Flags & RTLW81_FLAG_8188E) != 0) {
  3169. Value = RTLW81_READ_REGISTER16(Device, Rtlw81RegisterSysFunctionEnable);
  3170. Value &= ~RTLW81_SYS_FUNCTION_ENABLE_CPUEN;
  3171. RTLW81_WRITE_REGISTER16(Device, Rtlw81RegisterSysFunctionEnable, Value);
  3172. Value |= RTLW81_SYS_FUNCTION_ENABLE_CPUEN;
  3173. RTLW81_WRITE_REGISTER16(Device, Rtlw81RegisterSysFunctionEnable, Value);
  3174. } else {
  3175. //
  3176. // Issue a reset to the 8051.
  3177. //
  3178. RTLW81_WRITE_REGISTER8(Device,
  3179. Rtlw81RegisterHmetfr3,
  3180. RTLW81_HMENTFR3_RESET);
  3181. //
  3182. // Wait for the reset to clear itself.
  3183. //
  3184. CurrentTime = KeGetRecentTimeCounter();
  3185. TimeoutTicks = HlQueryTimeCounterFrequency() * RTLW81_DEVICE_TIMEOUT;
  3186. Timeout = CurrentTime + TimeoutTicks;
  3187. do {
  3188. Value = RTLW81_READ_REGISTER16(Device,
  3189. Rtlw81RegisterSysFunctionEnable);
  3190. if ((Value & RTLW81_SYS_FUNCTION_ENABLE_CPUEN) == 0) {
  3191. goto FirmwareResetEnd;
  3192. }
  3193. CurrentTime = KeGetRecentTimeCounter();
  3194. } while (CurrentTime <= Timeout);
  3195. //
  3196. // Just force the reset if it didn't clear above.
  3197. //
  3198. Value &= ~RTLW81_SYS_FUNCTION_ENABLE_CPUEN;
  3199. RTLW81_WRITE_REGISTER16(Device, Rtlw81RegisterSysFunctionEnable, Value);
  3200. }
  3201. FirmwareResetEnd:
  3202. return;
  3203. }
  3204. KSTATUS
  3205. Rtlw81pInitializeFirmware (
  3206. PRTLW81_DEVICE Device,
  3207. PIRP Irp
  3208. )
  3209. /*++
  3210. Routine Description:
  3211. This routine initializes the device firmware. It loads the firmware binary
  3212. file and write it into the device.
  3213. Arguments:
  3214. Device - Supplies a pointer to the RTLW81xx device.
  3215. Irp - Supplies a pointer to the IRP that is driving the initialization.
  3216. Return Value:
  3217. Status code.
  3218. --*/
  3219. {
  3220. ULONG BytesRemaining;
  3221. ULONG BytesThisRound;
  3222. ULONGLONG CurrentTime;
  3223. USHORT DownloadAddress;
  3224. PLOADED_FILE Firmware;
  3225. PUCHAR FirmwareData;
  3226. PRTLW81_FIRMWARE_HEADER FirmwareHeader;
  3227. UINTN FirmwareLength;
  3228. ULONG PageIndex;
  3229. PSTR Path;
  3230. ULONG PathLength;
  3231. KSTATUS Status;
  3232. ULONGLONG Timeout;
  3233. ULONGLONG TimeoutTicks;
  3234. ULONG Value;
  3235. Firmware = NULL;
  3236. if (Device->InitializationPhase == 0) {
  3237. if ((Device->Flags & RTLW81_FLAG_8188E) != 0) {
  3238. Path = RTLW81_8188E_FIRMWARE_PATH;
  3239. } else if ((Device->Flags &
  3240. (RTLW81_FLAG_UMC_A_CUT | RTLW81_FLAG_8192C)) ==
  3241. RTLW81_FLAG_UMC_A_CUT) {
  3242. Path = RTLW81_8188C_UMC_FIRMWARE_PATH;
  3243. } else {
  3244. Path = RTLW81_DEFAULT_FIRMWARE_PATH;
  3245. }
  3246. //
  3247. // Pend the IRP before starting the asynchronous load of the firmware.
  3248. //
  3249. IoPendIrp(Rtlw81Driver, Irp);
  3250. Device->InitializationIrp = Irp;
  3251. PathLength = RtlStringLength(Path) + 1;
  3252. Status = IoLoadFile(Path,
  3253. PathLength,
  3254. Rtlw81pLoadFirmwareCompletionRoutine,
  3255. Device);
  3256. if (!KSUCCESS(Status)) {
  3257. IoContinueIrp(Rtlw81Driver, Irp);
  3258. }
  3259. goto InitializeFirmwareEnd;
  3260. }
  3261. ASSERT(Device->InitializationPhase == 1);
  3262. ASSERT(Device->InitializationIrp == Irp);
  3263. ASSERT(Device->Firmware != NULL);
  3264. TimeoutTicks = HlQueryTimeCounterFrequency() * RTLW81_DEVICE_TIMEOUT;
  3265. Firmware = Device->Firmware;
  3266. //
  3267. // Make sure the I/O buffer is mapped contiguously.
  3268. //
  3269. Status = MmMapIoBuffer(Firmware->IoBuffer, FALSE, FALSE, TRUE);
  3270. if (!KSUCCESS(Status)) {
  3271. goto InitializeFirmwareEnd;
  3272. }
  3273. //
  3274. // Check for a valid header and skip it.
  3275. //
  3276. FirmwareLength = Firmware->Length;
  3277. if (FirmwareLength < sizeof(RTLW81_FIRMWARE_HEADER)) {
  3278. Status = STATUS_INVALID_CONFIGURATION;
  3279. goto InitializeFirmwareEnd;
  3280. }
  3281. FirmwareData = Firmware->IoBuffer->Fragment[0].VirtualAddress;
  3282. FirmwareHeader = (PRTLW81_FIRMWARE_HEADER)FirmwareData;
  3283. if (((FirmwareHeader->Signature >> 4) != RTLW81_88E_FIRMWARE_SIGNATURE) &&
  3284. ((FirmwareHeader->Signature >> 4) != RTLW81_88C_FIRMWARE_SIGNATURE) &&
  3285. ((FirmwareHeader->Signature >> 4) != RTLW81_92C_FIRMWARE_SIGNATURE)) {
  3286. RtlDebugPrint("RTLW Unsupported FW signature 0x%04x\n",
  3287. FirmwareHeader->Signature);
  3288. Status = STATUS_NOT_SUPPORTED;
  3289. goto InitializeFirmwareEnd;
  3290. }
  3291. RtlDebugPrint("RTLW Firmware Version %d.%d %02d/%02d %02d:%02d\n",
  3292. FirmwareHeader->Version,
  3293. FirmwareHeader->Subversion,
  3294. FirmwareHeader->Month,
  3295. FirmwareHeader->MonthDay,
  3296. FirmwareHeader->Hour,
  3297. FirmwareHeader->Minute);
  3298. FirmwareData += sizeof(RTLW81_FIRMWARE_HEADER);
  3299. FirmwareLength -= sizeof(RTLW81_FIRMWARE_HEADER);
  3300. //
  3301. // Perform a firmware reset if necessary.
  3302. //
  3303. Value = RTLW81_READ_REGISTER8(Device, Rtlw81RegisterMcuFirmwareDownload0);
  3304. if ((Value & RTLW81_MCU_FIRMWARE_DOWNLOAD_RAM_DL_SELECT) != 0) {
  3305. Rtlw81pFirmwareReset(Device);
  3306. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterMcuFirmwareDownload0, 0);
  3307. }
  3308. if ((Device->Flags & RTLW81_FLAG_8188E) == 0) {
  3309. Value = RTLW81_READ_REGISTER16(Device, Rtlw81RegisterSysFunctionEnable);
  3310. Value |= RTLW81_SYS_FUNCTION_ENABLE_CPUEN;
  3311. RTLW81_WRITE_REGISTER16(Device, Rtlw81RegisterSysFunctionEnable, Value);
  3312. }
  3313. //
  3314. // Enable firmware download.
  3315. //
  3316. Value = RTLW81_READ_REGISTER8(Device, Rtlw81RegisterMcuFirmwareDownload0);
  3317. Value |= RTLW81_MCU_FIRMWARE_DOWNLOAD_ENABLE;
  3318. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterMcuFirmwareDownload0, Value);
  3319. Value = RTLW81_READ_REGISTER8(Device, Rtlw81RegisterMcuFirmwareDownload2);
  3320. Value &= ~(RTLW81_MCU_FIRMWARE_DOWNLOAD_CLEAR >> 16);
  3321. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterMcuFirmwareDownload2, Value);
  3322. //
  3323. // Reset the checksum.
  3324. //
  3325. Value = RTLW81_READ_REGISTER8(Device, Rtlw81RegisterMcuFirmwareDownload0);
  3326. Value |= RTLW81_MCU_FIRMWARE_DOWNLOAD_CHECKSUM_REPORT;
  3327. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterMcuFirmwareDownload0, Value);
  3328. //
  3329. // Load the firmware into the chip one page at a time.
  3330. //
  3331. PageIndex = 0;
  3332. while (FirmwareLength != 0) {
  3333. BytesThisRound = FirmwareLength;
  3334. if (BytesThisRound > RTLW81_FIRMWARE_PAGE_SIZE) {
  3335. BytesThisRound = RTLW81_FIRMWARE_PAGE_SIZE;
  3336. }
  3337. FirmwareLength -= BytesThisRound;
  3338. //
  3339. // Set the current page.
  3340. //
  3341. Value = RTLW81_READ_REGISTER32(Device,
  3342. Rtlw81RegisterMcuFirmwareDownload0);
  3343. Value &= ~RTLW81_MCU_FIRMWARE_DOWNLOAD_PAGE_MASK;
  3344. Value |= (PageIndex << RTLW81_MCU_FIRMWARE_DOWNLOAD_PAGE_SHIFT) &
  3345. RTLW81_MCU_FIRMWARE_DOWNLOAD_PAGE_MASK;
  3346. RTLW81_WRITE_REGISTER32(Device,
  3347. Rtlw81RegisterMcuFirmwareDownload0,
  3348. Value);
  3349. //
  3350. // Write the bytes to the current page.
  3351. //
  3352. DownloadAddress = Rtlw81RegisterFirmwareDownload;
  3353. BytesRemaining = BytesThisRound;
  3354. while (BytesRemaining != 0) {
  3355. if (BytesRemaining > RTLW81_MAX_FIRMWARE_WRITE_SIZE) {
  3356. BytesThisRound = RTLW81_MAX_FIRMWARE_WRITE_SIZE;
  3357. } else if (BytesRemaining > 4) {
  3358. BytesThisRound = 4;
  3359. } else {
  3360. BytesThisRound = 1;
  3361. }
  3362. Rtlw81pWriteData(Device,
  3363. DownloadAddress,
  3364. FirmwareData,
  3365. BytesThisRound);
  3366. DownloadAddress += BytesThisRound;
  3367. FirmwareData += BytesThisRound;
  3368. BytesRemaining -= BytesThisRound;
  3369. }
  3370. PageIndex += 1;
  3371. }
  3372. //
  3373. // Disable firmware download.
  3374. //
  3375. Value = RTLW81_READ_REGISTER8(Device, Rtlw81RegisterMcuFirmwareDownload0);
  3376. Value &= ~RTLW81_MCU_FIRMWARE_DOWNLOAD_ENABLE;
  3377. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterMcuFirmwareDownload0, Value);
  3378. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterMcuFirmwareDownload1, 0);
  3379. //
  3380. // Wait for the checksum report.
  3381. //
  3382. CurrentTime = KeGetRecentTimeCounter();
  3383. Timeout = CurrentTime + TimeoutTicks;
  3384. do {
  3385. Value = RTLW81_READ_REGISTER32(Device,
  3386. Rtlw81RegisterMcuFirmwareDownload0);
  3387. if ((Value & RTLW81_MCU_FIRMWARE_DOWNLOAD_CHECKSUM_REPORT) != 0) {
  3388. break;
  3389. }
  3390. CurrentTime = KeGetRecentTimeCounter();
  3391. } while (CurrentTime <= Timeout);
  3392. if (CurrentTime > Timeout) {
  3393. Status = STATUS_TIMEOUT;
  3394. goto InitializeFirmwareEnd;
  3395. }
  3396. Value = RTLW81_READ_REGISTER32(Device, Rtlw81RegisterMcuFirmwareDownload0);
  3397. Value &= ~RTLW81_MCU_FIRMWARE_DOWNLOAD_WINTINI_READY;
  3398. Value |= RTLW81_MCU_FIRMWARE_DOWNLOAD_READY;
  3399. RTLW81_WRITE_REGISTER32(Device, Rtlw81RegisterMcuFirmwareDownload0, Value);
  3400. //
  3401. // Reset again for RTL8188E devices.
  3402. //
  3403. if ((Device->Flags & RTLW81_FLAG_8188E) != 0) {
  3404. Rtlw81pFirmwareReset(Device);
  3405. }
  3406. //
  3407. // Wait for the device to signal that the firmware is ready.
  3408. //
  3409. CurrentTime = KeGetRecentTimeCounter();
  3410. Timeout = CurrentTime + TimeoutTicks;
  3411. do {
  3412. Value = RTLW81_READ_REGISTER32(Device,
  3413. Rtlw81RegisterMcuFirmwareDownload0);
  3414. if ((Value & RTLW81_MCU_FIRMWARE_DOWNLOAD_WINTINI_READY) != 0) {
  3415. break;
  3416. }
  3417. CurrentTime = KeGetRecentTimeCounter();
  3418. } while (CurrentTime <= Timeout);
  3419. if (CurrentTime > Timeout) {
  3420. Status = STATUS_TIMEOUT;
  3421. goto InitializeFirmwareEnd;
  3422. }
  3423. Status = STATUS_SUCCESS;
  3424. InitializeFirmwareEnd:
  3425. //
  3426. // Unload the firmware.
  3427. //
  3428. if (Firmware != NULL) {
  3429. ASSERT(Firmware == Device->Firmware);
  3430. Device->Firmware = NULL;
  3431. IoUnloadFile(Firmware);
  3432. }
  3433. if (!KSUCCESS(Status)) {
  3434. RtlDebugPrint("RTLW: Initailize firmware failed %d\n", Status);
  3435. }
  3436. return Status;
  3437. }
  3438. VOID
  3439. Rtlw81pLoadFirmwareCompletionRoutine (
  3440. PVOID Context,
  3441. PLOADED_FILE File
  3442. )
  3443. /*++
  3444. Routine Description:
  3445. This routine is called when the asynchronous firmware load has completed.
  3446. Arguments:
  3447. Context - Supplies the context supplied by the caller who initiation the
  3448. file load.
  3449. File - Supplies a pointer to the loaded file.
  3450. Return Value:
  3451. None.
  3452. --*/
  3453. {
  3454. PRTLW81_DEVICE Device;
  3455. Device = (PRTLW81_DEVICE)Context;
  3456. Device->Firmware = File;
  3457. IoContinueIrp(Rtlw81Driver, Device->InitializationIrp);
  3458. return;
  3459. }
  3460. VOID
  3461. Rtlw81pLcCalibration (
  3462. PRTLW81_DEVICE Device
  3463. )
  3464. /*++
  3465. Routine Description:
  3466. This routine performcs LC calibration.
  3467. Arguments:
  3468. Device - Supplies a pointer to the RTLW81xx device to calibrate.
  3469. Return Value:
  3470. None.
  3471. --*/
  3472. {
  3473. ULONG Index;
  3474. ULONG RfAc[RTLW81_MAX_CHAIN_COUNT];
  3475. UCHAR TransmitMode;
  3476. ULONG Value;
  3477. //
  3478. // If the transmit mode is enabled, then disable all continuous transmits
  3479. // and set the RF mode to standby.
  3480. //
  3481. TransmitMode = RTLW81_READ_REGISTER8(Device, Rtlw81RegisterOfdm1Lstf3);
  3482. if ((TransmitMode & RTLW81_OFDM1_LSTF3_TRANSMIT_ENABLED) != 0) {
  3483. Value = TransmitMode & ~RTLW81_OFDM1_LSTF3_TRANSMIT_ENABLED;
  3484. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterOfdm1Lstf3, Value);
  3485. for (Index = 0; Index < Device->ReceiveChainCount; Index += 1) {
  3486. RfAc[Index] = Rtlw81pReadRfRegister(Device,
  3487. Index,
  3488. Rtlw81RfRegisterAc);
  3489. Value = RfAc[Index];
  3490. Value &= ~RTLW81_RF_AC_MODE_MASK;
  3491. Value |= (RTLW81_RF_AC_MODE_STANDBY << RTLW81_RF_AC_MODE_SHIFT) &
  3492. RTLW81_RF_AC_MODE_MASK;
  3493. Rtlw81pWriteRfRegister(Device, Index, Rtlw81RfRegisterAc, Value);
  3494. }
  3495. //
  3496. // Otherwise block all transfer queues.
  3497. //
  3498. } else {
  3499. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterTransmitPause, 0xFF);
  3500. }
  3501. //
  3502. // Start the calibration process.
  3503. //
  3504. Value = Rtlw81pReadRfRegister(Device, 0, Rtlw81RfRegisterChannelBandwidth);
  3505. Value |= RTLW81_RF_CHANNEL_BANDWIDTH_LC_START;
  3506. Rtlw81pWriteRfRegister(Device, 0, Rtlw81RfRegisterChannelBandwidth, Value);
  3507. KeDelayExecution(FALSE, FALSE, 100 * MICROSECONDS_PER_MILLISECOND);
  3508. //
  3509. // Restore the mode.
  3510. //
  3511. if ((TransmitMode & RTLW81_OFDM1_LSTF3_TRANSMIT_ENABLED) != 0) {
  3512. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterOfdm1Lstf3, TransmitMode);
  3513. for (Index = 0; Index < Device->ReceiveChainCount; Index += 1) {
  3514. Value = RfAc[Index];
  3515. Rtlw81pWriteRfRegister(Device, Index, Rtlw81RfRegisterAc, Value);
  3516. }
  3517. } else {
  3518. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterTransmitPause, 0x00);
  3519. }
  3520. return;
  3521. }
  3522. VOID
  3523. Rtlw81pSetChannel (
  3524. PRTLW81_DEVICE Device,
  3525. ULONG Channel
  3526. )
  3527. /*++
  3528. Routine Description:
  3529. This routine sets the given channel for the RTLW81xx device.
  3530. Arguments:
  3531. Device - Supplies a pointer to the RTLW81xx device.
  3532. Channel - Supplies the channel to set in the RTLW81xx device.
  3533. Return Value:
  3534. None.
  3535. --*/
  3536. {
  3537. ULONG BandwidthValue;
  3538. ULONG Index;
  3539. ULONG Value;
  3540. //
  3541. // Do nothing if the desired channel is already set.
  3542. //
  3543. if (Device->CurrentChannel == Channel) {
  3544. return;
  3545. }
  3546. //
  3547. // Enable transmit power on the channel.
  3548. //
  3549. for (Index = 0; Index < Device->TransmitChainCount; Index += 1) {
  3550. Rtlw81pEnableChannelTransmitPower(Device, Index, Channel);
  3551. }
  3552. //
  3553. // Enable the channel for receive.
  3554. //
  3555. for (Index = 0; Index < Device->ReceiveChainCount; Index += 1) {
  3556. Value = Rtlw81pReadRfRegister(Device,
  3557. Index,
  3558. Rtlw81RfRegisterChannelBandwidth);
  3559. Value &= ~RTLW81_RF_CHANNEL_BANDWIDTH_CHANNEL_MASK;
  3560. Value |= (Channel << RTLW81_RF_CHANNEL_BANDWIDTH_CHANNEL_SHIFT) &
  3561. RTLW81_RF_CHANNEL_BANDWIDTH_CHANNEL_MASK;
  3562. Rtlw81pWriteRfRegister(Device,
  3563. Index,
  3564. Rtlw81RfRegisterChannelBandwidth,
  3565. Value);
  3566. }
  3567. //
  3568. // Set the bandwidth to 20MHz.
  3569. //
  3570. Value = RTLW81_READ_REGISTER8(Device, Rtlw81RegisterBandwidthMode);
  3571. Value |= RTLW81_BANDWIDTH_MODE_20MHZ;
  3572. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterBandwidthMode, Value);
  3573. Value = RTLW81_READ_REGISTER32(Device, Rtlw81RegisterFpga0Rfmod);
  3574. Value &= ~RTLW81_RFMOD_40MHZ;
  3575. RTLW81_WRITE_REGISTER32(Device, Rtlw81RegisterFpga0Rfmod, Value);
  3576. Value = RTLW81_READ_REGISTER32(Device, Rtlw81RegisterFpga1Rfmod);
  3577. Value &= ~RTLW81_RFMOD_40MHZ;
  3578. RTLW81_WRITE_REGISTER32(Device, Rtlw81RegisterFpga1Rfmod, Value);
  3579. if ((Device->Flags & RTLW81_FLAG_8188E) == 0) {
  3580. Value = RTLW81_READ_REGISTER32(Device, Rtlw81RegisterFpga0AnaParam2);
  3581. Value |= RTLW81_FPGA0_ANA_PARAM2_CBW20;
  3582. RTLW81_WRITE_REGISTER32(Device, Rtlw81RegisterFpga0AnaParam2, Value);
  3583. }
  3584. BandwidthValue = RTLW81_RF_CHANNEL_BANDWIDTH_DEFAULT_20MHZ;
  3585. if ((Device->Flags & RTLW81_FLAG_8188E) != 0) {
  3586. BandwidthValue = RTLW81_RF_CHANNEL_BANDWIDTH_8188E_20MHZ;
  3587. }
  3588. Value = Rtlw81pReadRfRegister(Device,
  3589. 0,
  3590. Rtlw81RfRegisterChannelBandwidth);
  3591. Value &= ~(RTLW81_RF_CHANNEL_BANDWIDTH_CHANNEL_MASK |
  3592. RTLW81_RF_CHANNEL_BANDWIDTH_DEFAULT_20MHZ |
  3593. RTLW81_RF_CHANNEL_BANDWIDTH_8188E_20MHZ);
  3594. Value |= (Channel << RTLW81_RF_CHANNEL_BANDWIDTH_CHANNEL_SHIFT) &
  3595. RTLW81_RF_CHANNEL_BANDWIDTH_CHANNEL_MASK;
  3596. Value |= BandwidthValue;
  3597. Rtlw81pWriteRfRegister(Device,
  3598. 0,
  3599. Rtlw81RfRegisterChannelBandwidth,
  3600. Value);
  3601. Device->CurrentChannel = Channel;
  3602. return;
  3603. }
  3604. VOID
  3605. Rtlw81pEnableChannelTransmitPower (
  3606. PRTLW81_DEVICE Device,
  3607. ULONG Chain,
  3608. ULONG Channel
  3609. )
  3610. /*++
  3611. Routine Description:
  3612. This routine enables the transmit power for the given channel on the
  3613. supplied chain.
  3614. Arguments:
  3615. Device - Supplies a pointer to the RTLW81xx device.
  3616. Chain - Supplies the transmit chain to enable.
  3617. Channel - Supplies the channel to set in the RTLW81xx device.
  3618. Return Value:
  3619. None.
  3620. --*/
  3621. {
  3622. USHORT Bw20Power;
  3623. USHORT CckPower;
  3624. PRTLW81_DEFAULT_TRANSMIT_POWER_DATA DefaultPowerData;
  3625. ULONG Diff;
  3626. ULONG Group;
  3627. USHORT HtPower;
  3628. ULONG Index;
  3629. UCHAR MaxPower;
  3630. USHORT OfdmPower;
  3631. USHORT PowerStates[RTLW81_POWER_STATE_COUNT];
  3632. RTLW81_REGISTER Register;
  3633. PRTLW81_8188E_TRANSMIT_POWER_DATA Rtl8188ePowerData;
  3634. ULONG Value;
  3635. RtlZeroMemory(PowerStates, RTLW81_POWER_STATE_COUNT * sizeof(USHORT));
  3636. if ((Device->Flags & RTLW81_FLAG_8188E) != 0) {
  3637. Rtl8188ePowerData = Rtlw8188eTransmitPowerData;
  3638. if (Chain <= 2) {
  3639. Group = 0;
  3640. } else if (Chain <= 5) {
  3641. Group = 1;
  3642. } else if (Chain <= 8) {
  3643. Group = 2;
  3644. } else if (Chain <= 11) {
  3645. Group = 3;
  3646. } else if (Chain <= 13) {
  3647. Group = 4;
  3648. } else {
  3649. Group = 5;
  3650. }
  3651. if (Device->Regulatory == 0) {
  3652. for (Index = 0; Index <= 3; Index += 1) {
  3653. PowerStates[Index] = Rtl8188ePowerData->GroupPower[0][Index];
  3654. }
  3655. }
  3656. for (Index = 4; Index < RTLW81_POWER_STATE_COUNT; Index += 1) {
  3657. if (Device->Regulatory == 3) {
  3658. PowerStates[Index] = Rtl8188ePowerData->GroupPower[0][Index];
  3659. } else if (Device->Regulatory == 1) {
  3660. PowerStates[Index] =
  3661. Rtl8188ePowerData->GroupPower[Group][Index];
  3662. } else if (Device->Regulatory != 2) {
  3663. PowerStates[Index] = Rtl8188ePowerData->GroupPower[0][Index];
  3664. }
  3665. }
  3666. CckPower = Device->Power.Rtlw8188e.CckTransmitPower[Group];
  3667. HtPower = Device->Power.Rtlw8188e.Ht40TransmitPower[Group];
  3668. OfdmPower = HtPower + Device->Power.Rtlw8188e.OfdmTransmitPowerDiff;
  3669. Bw20Power = HtPower + Device->Power.Rtlw8188e.Bw20TransmitPowerDiff;
  3670. } else {
  3671. if (((Device->Flags & RTLW81_FLAG_8192C) == 0) &&
  3672. (Device->BoardType == RTLW81_ROM_RF_OPT1_BOARD_TYPE_HIGHPA)) {
  3673. DefaultPowerData = &Rtlw8188ruTransmitPowerData[Chain];
  3674. } else {
  3675. DefaultPowerData = &RtlwDefaultTransmitPowerData[Chain];
  3676. }
  3677. if (Channel <= 3) {
  3678. Group = 0;
  3679. } else if (Channel <= 9) {
  3680. Group = 1;
  3681. } else {
  3682. Group = 2;
  3683. }
  3684. if (Device->Regulatory == 0) {
  3685. for (Index = 0; Index <= 3; Index += 1) {
  3686. PowerStates[Index] = DefaultPowerData->GroupPower[0][Index];
  3687. }
  3688. }
  3689. for (Index = 4; Index < RTLW81_POWER_STATE_COUNT; Index += 1) {
  3690. if (Device->Regulatory == 3) {
  3691. PowerStates[Index] = DefaultPowerData->GroupPower[0][Index];
  3692. MaxPower = Device->Power.Default.Ht20MaxPower[Group];
  3693. MaxPower = (MaxPower >> (Chain * 4)) & 0xF;
  3694. if (PowerStates[Index] > MaxPower) {
  3695. PowerStates[Index] = MaxPower;
  3696. }
  3697. } else if (Device->Regulatory == 1) {
  3698. PowerStates[Index] = DefaultPowerData->GroupPower[Group][Index];
  3699. } else if (Device->Regulatory != 2) {
  3700. PowerStates[Index] = DefaultPowerData->GroupPower[0][Index];
  3701. }
  3702. }
  3703. CckPower = Device->Power.Default.CckTransmitPower[Chain][Group];
  3704. HtPower = Device->Power.Default.Ht40TransmitPower[Chain][Group];
  3705. if (Device->TransmitChainCount > 1) {
  3706. Diff = Device->Power.Default.Ht40TransmitPowerDiff[Group];
  3707. Diff = (Diff >> (Chain * 4)) & 0xF;
  3708. if (HtPower > Diff) {
  3709. HtPower = HtPower - Diff;
  3710. } else {
  3711. HtPower = 0;
  3712. }
  3713. }
  3714. Diff = Device->Power.Default.OfdmTransmitPowerDiff[Group];
  3715. Diff = (Diff >> (Chain * 4)) & 0xF;
  3716. OfdmPower = HtPower + Diff;
  3717. Diff = Device->Power.Default.Ht20TransmitPowerDiff[Group];
  3718. Diff = (Diff >> (Chain * 4)) & 0xF;
  3719. Bw20Power = HtPower + Diff;
  3720. }
  3721. for (Index = 0; Index <= 3; Index += 1) {
  3722. PowerStates[Index] += CckPower;
  3723. if (PowerStates[Index] > RTLW81_MAX_TRANSMIT_POWER) {
  3724. PowerStates[Index] = RTLW81_MAX_TRANSMIT_POWER;
  3725. }
  3726. }
  3727. for (Index = 4; Index <= 11; Index += 1) {
  3728. PowerStates[Index] += OfdmPower;
  3729. if (PowerStates[Index] > RTLW81_MAX_TRANSMIT_POWER) {
  3730. PowerStates[Index] = RTLW81_MAX_TRANSMIT_POWER;
  3731. }
  3732. }
  3733. for (Index = 12; Index < RTLW81_POWER_STATE_COUNT; Index += 1) {
  3734. PowerStates[Index] += Bw20Power;
  3735. if (PowerStates[Index] > RTLW81_MAX_TRANSMIT_POWER) {
  3736. PowerStates[Index] = RTLW81_MAX_TRANSMIT_POWER;
  3737. }
  3738. }
  3739. //
  3740. // Now set the power states in the hardware.
  3741. //
  3742. if (Chain == 0) {
  3743. Value = RTLW81_READ_REGISTER32(Device,
  3744. Rtlw81RegisterTransmitAgcACck1Mcs32);
  3745. Value &= ~RLTW81_TRANSMIT_AGC_A_CCK1_MCS32_MASK;
  3746. Value |= (PowerStates[0] << RLTW81_TRANSMIT_AGC_A_CCK1_MCS32_SHIFT) &
  3747. RLTW81_TRANSMIT_AGC_A_CCK1_MCS32_MASK;
  3748. RTLW81_WRITE_REGISTER32(Device,
  3749. Rtlw81RegisterTransmitAgcACck1Mcs32,
  3750. Value);
  3751. Value = RTLW81_READ_REGISTER32(Device,
  3752. Rtlw81RegisterTransmitAgcBCck11ACck211);
  3753. Value &= ~RTLW81_TRANSMIT_AGC_A_CCK2_MASK;
  3754. Value |= (PowerStates[1] << RTLW81_TRANSMIT_AGC_A_CCK2_SHIFT) &
  3755. RTLW81_TRANSMIT_AGC_A_CCK2_MASK;
  3756. Value &= ~RTLW81_TRANSMIT_AGC_A_CCK55_MASK;
  3757. Value |= (PowerStates[2] << RTLW81_TRANSMIT_AGC_A_CCK55_SHIFT) &
  3758. RTLW81_TRANSMIT_AGC_A_CCK55_MASK;
  3759. Value &= ~RTLW81_TRANSMIT_AGC_A_CCK11_MASK;
  3760. Value |= (PowerStates[3] << RTLW81_TRANSMIT_AGC_A_CCK11_SHIFT) &
  3761. RTLW81_TRANSMIT_AGC_A_CCK11_MASK;
  3762. RTLW81_WRITE_REGISTER32(Device,
  3763. Rtlw81RegisterTransmitAgcBCck11ACck211,
  3764. Value);
  3765. } else {
  3766. Value = RTLW81_READ_REGISTER32(Device,
  3767. Rtlw81RegisterTransmitAgcBCck155Mcs32);
  3768. Value &= ~RTLW81_TRANSMIT_AGC_B_CCK1_MASK;
  3769. Value |= (PowerStates[0] << RTLW81_TRANSMIT_AGC_B_CCK1_SHIFT) &
  3770. RTLW81_TRANSMIT_AGC_B_CCK1_MASK;
  3771. Value &= ~RTLW81_TRANSMIT_AGC_B_CCK2_MASK;
  3772. Value |= (PowerStates[1] << RTLW81_TRANSMIT_AGC_B_CCK2_SHIFT) &
  3773. RTLW81_TRANSMIT_AGC_B_CCK2_MASK;
  3774. Value &= ~RTLW81_TRANSMIT_AGC_B_CCK55_MASK;
  3775. Value |= (PowerStates[2] << RTLW81_TRANSMIT_AGC_B_CCK55_SHIFT) &
  3776. RTLW81_TRANSMIT_AGC_B_CCK55_MASK;
  3777. RTLW81_WRITE_REGISTER32(Device,
  3778. Rtlw81RegisterTransmitAgcBCck155Mcs32,
  3779. Value);
  3780. Value = RTLW81_READ_REGISTER32(Device,
  3781. Rtlw81RegisterTransmitAgcBCck11ACck211);
  3782. Value &= ~RTLW81_TRANSMIT_AGC_B_CCK11_MASK;
  3783. Value |= (PowerStates[3] << RTLW81_TRANSMIT_AGC_B_CCK11_SHIFT) &
  3784. RTLW81_TRANSMIT_AGC_B_CCK11_MASK;
  3785. RTLW81_WRITE_REGISTER32(Device,
  3786. Rtlw81RegisterTransmitAgcBCck11ACck211,
  3787. Value);
  3788. }
  3789. Value = ((PowerStates[4] << RTLW81_TRANSMIT_AGC_RATE_06_SHIFT) &
  3790. RTLW81_TRANSMIT_AGC_RATE_06_MASK) |
  3791. ((PowerStates[5] << RTLW81_TRANSMIT_AGC_RATE_09_SHIFT) &
  3792. RTLW81_TRANSMIT_AGC_RATE_09_MASK) |
  3793. ((PowerStates[6] << RTLW81_TRANSMIT_AGC_RATE_12_SHIFT) &
  3794. RTLW81_TRANSMIT_AGC_RATE_12_MASK) |
  3795. ((PowerStates[7] << RTLW81_TRANSMIT_AGC_RATE_18_SHIFT) &
  3796. RTLW81_TRANSMIT_AGC_RATE_18_MASK);
  3797. Register = Rtlw81RegisterTransmitAgcRate1806Chain1;
  3798. if (Chain == 0) {
  3799. Register = Rtlw81RegisterTransmitAgcRate1806Chain0;
  3800. }
  3801. RTLW81_WRITE_REGISTER32(Device, Register, Value);
  3802. Value = ((PowerStates[8] << RTLW81_TRANSMIT_AGC_RATE_24_SHIFT) &
  3803. RTLW81_TRANSMIT_AGC_RATE_24_MASK) |
  3804. ((PowerStates[9] << RTLW81_TRANSMIT_AGC_RATE_36_SHIFT) &
  3805. RTLW81_TRANSMIT_AGC_RATE_36_MASK) |
  3806. ((PowerStates[10] << RTLW81_TRANSMIT_AGC_RATE_48_SHIFT) &
  3807. RTLW81_TRANSMIT_AGC_RATE_48_MASK) |
  3808. ((PowerStates[11] << RTLW81_TRANSMIT_AGC_RATE_54_SHIFT) &
  3809. RTLW81_TRANSMIT_AGC_RATE_54_MASK);
  3810. Register = Rtlw81RegisterTransmitAgcRate5424Chain1;
  3811. if (Chain == 0) {
  3812. Register = Rtlw81RegisterTransmitAgcRate5424Chain0;
  3813. }
  3814. RTLW81_WRITE_REGISTER32(Device, Register, Value);
  3815. Value = ((PowerStates[12] << RTLW81_TRANSMIT_AGC_MCS00_SHIFT) &
  3816. RTLW81_TRANSMIT_AGC_MCS00_MASK) |
  3817. ((PowerStates[13] << RTLW81_TRANSMIT_AGC_MCS01_SHIFT) &
  3818. RTLW81_TRANSMIT_AGC_MCS01_MASK) |
  3819. ((PowerStates[14] << RTLW81_TRANSMIT_AGC_MCS02_SHIFT) &
  3820. RTLW81_TRANSMIT_AGC_MCS02_MASK) |
  3821. ((PowerStates[15] << RTLW81_TRANSMIT_AGC_MCS03_SHIFT) &
  3822. RTLW81_TRANSMIT_AGC_MCS03_MASK);
  3823. Register = Rtlw81RegisterTransmitAgcMcs03Mcs00Chain1;
  3824. if (Chain == 0) {
  3825. Register = Rtlw81RegisterTransmitAgcMcs03Mcs00Chain0;
  3826. }
  3827. RTLW81_WRITE_REGISTER32(Device, Register, Value);
  3828. Value = ((PowerStates[16] << RTLW81_TRANSMIT_AGC_MCS04_SHIFT) &
  3829. RTLW81_TRANSMIT_AGC_MCS04_MASK) |
  3830. ((PowerStates[17] << RTLW81_TRANSMIT_AGC_MCS05_SHIFT) &
  3831. RTLW81_TRANSMIT_AGC_MCS05_MASK) |
  3832. ((PowerStates[18] << RTLW81_TRANSMIT_AGC_MCS06_SHIFT) &
  3833. RTLW81_TRANSMIT_AGC_MCS06_MASK) |
  3834. ((PowerStates[19] << RTLW81_TRANSMIT_AGC_MCS07_SHIFT) &
  3835. RTLW81_TRANSMIT_AGC_MCS07_MASK);
  3836. Register = Rtlw81RegisterTransmitAgcMcs07Mcs04Chain1;
  3837. if (Chain == 0) {
  3838. Register = Rtlw81RegisterTransmitAgcMcs07Mcs04Chain0;
  3839. }
  3840. RTLW81_WRITE_REGISTER32(Device, Register, Value);
  3841. Value = ((PowerStates[20] << RTLW81_TRANSMIT_AGC_MCS08_SHIFT) &
  3842. RTLW81_TRANSMIT_AGC_MCS08_MASK) |
  3843. ((PowerStates[21] << RTLW81_TRANSMIT_AGC_MCS09_SHIFT) &
  3844. RTLW81_TRANSMIT_AGC_MCS09_MASK) |
  3845. ((PowerStates[22] << RTLW81_TRANSMIT_AGC_MCS10_SHIFT) &
  3846. RTLW81_TRANSMIT_AGC_MCS10_MASK) |
  3847. ((PowerStates[23] << RTLW81_TRANSMIT_AGC_MCS11_SHIFT) &
  3848. RTLW81_TRANSMIT_AGC_MCS11_MASK);
  3849. Register = Rtlw81RegisterTransmitAgcMcs11Mcs08Chain1;
  3850. if (Chain == 0) {
  3851. Register = Rtlw81RegisterTransmitAgcMcs11Mcs08Chain0;
  3852. }
  3853. RTLW81_WRITE_REGISTER32(Device, Register, Value);
  3854. Value = ((PowerStates[24] << RTLW81_TRANSMIT_AGC_MCS12_SHIFT) &
  3855. RTLW81_TRANSMIT_AGC_MCS12_MASK) |
  3856. ((PowerStates[25] << RTLW81_TRANSMIT_AGC_MCS13_SHIFT) &
  3857. RTLW81_TRANSMIT_AGC_MCS13_MASK) |
  3858. ((PowerStates[26] << RTLW81_TRANSMIT_AGC_MCS14_SHIFT) &
  3859. RTLW81_TRANSMIT_AGC_MCS14_MASK) |
  3860. ((PowerStates[27] << RTLW81_TRANSMIT_AGC_MCS15_SHIFT) &
  3861. RTLW81_TRANSMIT_AGC_MCS15_MASK);
  3862. Register = Rtlw81RegisterTransmitAgcMcs15Mcs12Chain1;
  3863. if (Chain == 0) {
  3864. Register = Rtlw81RegisterTransmitAgcMcs15Mcs12Chain0;
  3865. }
  3866. RTLW81_WRITE_REGISTER32(Device, Register, Value);
  3867. return;
  3868. }
  3869. KSTATUS
  3870. Rtlw81pWriteLlt (
  3871. PRTLW81_DEVICE Device,
  3872. ULONG Address,
  3873. ULONG Data
  3874. )
  3875. /*++
  3876. Routine Description:
  3877. This routine writes the given data to the LLT at the supplied address.
  3878. Arguments:
  3879. Device - Supplies a pointer to the RTLW81 device.
  3880. Address - Supplies the address of the LLT to write.
  3881. Data - Supplies the data to write to the LLT.
  3882. Return Value:
  3883. Status code.
  3884. --*/
  3885. {
  3886. ULONGLONG CurrentTime;
  3887. KSTATUS Status;
  3888. ULONGLONG Timeout;
  3889. ULONGLONG TimeoutTicks;
  3890. ULONG Value;
  3891. Value = (RTLW81_LLT_INIT_OP_WRITE << RTLW81_LLT_INIT_OP_SHIFT) |
  3892. ((Data << RTLW81_LLT_INIT_DATA_SHIFT) & RTLW81_LLT_INIT_DATA_MASK) |
  3893. ((Address << RTLW81_LLT_INIT_ADDRESS_SHIFT) &
  3894. RTLW81_LLT_INIT_ADDRESS_MASK);
  3895. RTLW81_WRITE_REGISTER32(Device, Rtlw81RegisterLltInit, Value);
  3896. //
  3897. // Wait for the write to complete.
  3898. //
  3899. CurrentTime = KeGetRecentTimeCounter();
  3900. TimeoutTicks = HlQueryTimeCounterFrequency() * RTLW81_DEVICE_TIMEOUT;
  3901. Timeout = CurrentTime + TimeoutTicks;
  3902. do {
  3903. Value = RTLW81_READ_REGISTER32(Device, Rtlw81RegisterLltInit);
  3904. Value = (Value & RTLW81_LLT_INIT_OP_MASK) >> RTLW81_LLT_INIT_OP_SHIFT;
  3905. if (Value == RTLW81_LLT_INIT_OP_NO_ACTIVE) {
  3906. break;
  3907. }
  3908. CurrentTime = KeGetRecentTimeCounter();
  3909. } while (CurrentTime <= Timeout);
  3910. if (CurrentTime > Timeout) {
  3911. Status = STATUS_TIMEOUT;
  3912. goto WriteLltEnd;
  3913. }
  3914. Status = STATUS_SUCCESS;
  3915. WriteLltEnd:
  3916. return Status;
  3917. }
  3918. KSTATUS
  3919. Rtlw81pWriteData (
  3920. PRTLW81_DEVICE Device,
  3921. USHORT Address,
  3922. PVOID Data,
  3923. ULONG DataLength
  3924. )
  3925. /*++
  3926. Routine Description:
  3927. This routine performs a write to the wireless RTL81xx device at the given
  3928. address.
  3929. Arguments:
  3930. Device - Supplies a pointer to the device.
  3931. Address - Supplies the address within the configuration space to write.
  3932. Data - Supplies a pointer to the value to write.
  3933. DataLength - Supplies the size of the data to write, in bytes.
  3934. Return Value:
  3935. Status code.
  3936. --*/
  3937. {
  3938. PUSB_TRANSFER ControlTransfer;
  3939. PUSB_SETUP_PACKET Setup;
  3940. KSTATUS Status;
  3941. ControlTransfer = Device->ControlTransfer;
  3942. Setup = ControlTransfer->Buffer;
  3943. Setup->RequestType = USB_SETUP_REQUEST_TO_DEVICE |
  3944. USB_SETUP_REQUEST_VENDOR |
  3945. USB_SETUP_REQUEST_DEVICE_RECIPIENT;
  3946. Setup->Request = RTLW81_VENDOR_REQUEST_REGISTER;
  3947. Setup->Value = Address;
  3948. Setup->Index = 0;
  3949. Setup->Length = DataLength;
  3950. RtlCopyMemory(Setup + 1, Data, DataLength);
  3951. ControlTransfer->Direction = UsbTransferDirectionOut;
  3952. ControlTransfer->Length = sizeof(USB_SETUP_PACKET) + DataLength;
  3953. Status = UsbSubmitSynchronousTransfer(ControlTransfer);
  3954. if (!KSUCCESS(Status) && KSUCCESS(Device->InitializationStatus)) {
  3955. RtlDebugPrint("RTLW81: Write to address 0x%04x failed with status %d\n",
  3956. Address,
  3957. Status);
  3958. Device->InitializationStatus = Status;
  3959. }
  3960. return Status;
  3961. }
  3962. KSTATUS
  3963. Rtlw81pReadData (
  3964. PRTLW81_DEVICE Device,
  3965. USHORT Address,
  3966. PVOID Data,
  3967. ULONG DataLength
  3968. )
  3969. /*++
  3970. Routine Description:
  3971. This routine performs a read from the wireless RTL81xx device at the given
  3972. address.
  3973. Arguments:
  3974. Device - Supplies a pointer to the device.
  3975. Address - Supplies the address within the device configuration space to
  3976. read.
  3977. Data - Supplies a pointer to the data buffer to receive the read data.
  3978. DataLength - Supplies the number of bytes to read.
  3979. Return Value:
  3980. Status code.
  3981. --*/
  3982. {
  3983. PUSB_TRANSFER ControlTransfer;
  3984. PUSB_SETUP_PACKET Setup;
  3985. KSTATUS Status;
  3986. ControlTransfer = Device->ControlTransfer;
  3987. Setup = ControlTransfer->Buffer;
  3988. Setup->RequestType = USB_SETUP_REQUEST_TO_HOST |
  3989. USB_SETUP_REQUEST_VENDOR |
  3990. USB_SETUP_REQUEST_DEVICE_RECIPIENT;
  3991. Setup->Request = RTLW81_VENDOR_REQUEST_REGISTER;
  3992. Setup->Value = Address;
  3993. Setup->Index = 0;
  3994. Setup->Length = DataLength;
  3995. ControlTransfer->Direction = UsbTransferDirectionIn;
  3996. ControlTransfer->Length = sizeof(USB_SETUP_PACKET) + DataLength;
  3997. Status = UsbSubmitSynchronousTransfer(ControlTransfer);
  3998. if (KSUCCESS(Status)) {
  3999. RtlCopyMemory(Data, Setup + 1, DataLength);
  4000. } else if (KSUCCESS(Device->InitializationStatus)) {
  4001. RtlDebugPrint("RTLW81: Read from address 0x%04x failed with status "
  4002. "%d\n",
  4003. Address,
  4004. Status);
  4005. Device->InitializationStatus = Status;
  4006. }
  4007. return Status;
  4008. }
  4009. VOID
  4010. Rtlw81pWriteRegister (
  4011. PRTLW81_DEVICE Device,
  4012. USHORT Register,
  4013. ULONG Data,
  4014. ULONG DataLength
  4015. )
  4016. /*++
  4017. Routine Description:
  4018. This routine performs a register write to the wireless RTL81xx device.
  4019. Arguments:
  4020. Device - Supplies a pointer to the device.
  4021. Register - Supplies the register number to write to.
  4022. Data - Supplies a pointer to the value to write.
  4023. DataLength - Supplies the size of the data to write, in bytes.
  4024. Return Value:
  4025. Status code.
  4026. --*/
  4027. {
  4028. Rtlw81pWriteData(Device, Register, &Data, DataLength);
  4029. return;
  4030. }
  4031. ULONG
  4032. Rtlw81pReadRegister (
  4033. PRTLW81_DEVICE Device,
  4034. USHORT Register,
  4035. ULONG DataLength
  4036. )
  4037. /*++
  4038. Routine Description:
  4039. This routine performs a register read from the wireless RTL81xx device.
  4040. Arguments:
  4041. Device - Supplies a pointer to the device.
  4042. Register - Supplies the register number to read from.
  4043. DataLength - Supplies the number of bytes to read.
  4044. Return Value:
  4045. Returns the value read from the register.
  4046. --*/
  4047. {
  4048. ULONG Data;
  4049. Data = 0;
  4050. Rtlw81pReadData(Device, Register, &Data, DataLength);
  4051. return Data;
  4052. }
  4053. UCHAR
  4054. Rtlw81pEfuseRead8 (
  4055. PRTLW81_DEVICE Device,
  4056. USHORT Address
  4057. )
  4058. /*++
  4059. Routine Description:
  4060. This routine reads a byte from the EFUSE region.
  4061. Arguments:
  4062. Device - Supplies a pointer to the RTLW81 device.
  4063. Address - Supplies the address of the EFUSE byte to read.
  4064. Return Value:
  4065. Returns the value of the byte read from the EFUSE region..
  4066. --*/
  4067. {
  4068. UCHAR Data;
  4069. ULONG Index;
  4070. ULONG Value;
  4071. Value = RTLW81_READ_REGISTER32(Device, Rtlw81RegisterEfuseControl);
  4072. Value &= ~RTLW81_EFUSE_CONTROL_ADDRESS_MASK;
  4073. Value |= (Address << RTLW81_EFUSE_CONTROL_ADDRESS_SHIFT) &
  4074. RTLW81_EFUSE_CONTROL_ADDRESS_MASK;
  4075. Value &= ~RTLW81_EFUSE_CONTROL_VALID;
  4076. RTLW81_WRITE_REGISTER32(Device, Rtlw81RegisterEfuseControl, Value);
  4077. //
  4078. // Wait for the operation to complete.
  4079. //
  4080. Data = RTLW81_EFUSE_INVALID;
  4081. for (Index = 0; Index < RTLW81_EFUSE_RETRY_COUNT; Index += 1) {
  4082. Value = RTLW81_READ_REGISTER32(Device, Rtlw81RegisterEfuseControl);
  4083. if ((Value & RTLW81_EFUSE_CONTROL_VALID) != 0) {
  4084. Data = (Value & RTLW81_EFUSE_CONTROL_DATA_MASK) >>
  4085. RTLW81_EFUSE_CONTROL_DATA_SHIFT;
  4086. break;
  4087. }
  4088. HlBusySpin(1000);
  4089. }
  4090. return Data;
  4091. }
  4092. VOID
  4093. Rtlw81pWriteRfRegister (
  4094. PRTLW81_DEVICE Device,
  4095. ULONG Chain,
  4096. ULONG RfRegister,
  4097. ULONG Data
  4098. )
  4099. /*++
  4100. Routine Description:
  4101. This routine writes an RF register for the given chain.
  4102. Arguments:
  4103. Device - Supplies a pointer to the RTLW81 device.
  4104. Chain - Supplies the chain whose RF register is to be written.
  4105. RfRegister - Supplies the register to which the write will be performed.
  4106. Data - Supplies the value to write to the RF register.
  4107. Return Value:
  4108. None.
  4109. --*/
  4110. {
  4111. ULONG Register;
  4112. ULONG Value;
  4113. Register = Rtlw81RegisterLssiParameter + (4 * Chain);
  4114. if ((Device->Flags & RTLW81_FLAG_8188E) != 0) {
  4115. Value = (RfRegister << RTLW81_LSSI_PARAMETER_8188E_ADDRESS_SHIFT) &
  4116. RTLW81_LSSI_PARAMETER_8188E_ADDRESS_MASK;
  4117. } else {
  4118. Value = (RfRegister << RTLW81_LSSI_PARAMETER_DEFAULT_ADDRESS_SHIFT) &
  4119. RTLW81_LSSI_PARAMETER_DEFAULT_ADDRESS_MASK;
  4120. }
  4121. Value |= (Data << RTLW81_LSSI_PARAMETER_DATA_SHIFT) &
  4122. RTLW81_LSSI_PARAMETER_DATA_MASK;
  4123. RTLW81_WRITE_REGISTER32(Device, Register, Value);
  4124. return;
  4125. }
  4126. ULONG
  4127. Rtlw81pReadRfRegister (
  4128. PRTLW81_DEVICE Device,
  4129. ULONG Chain,
  4130. ULONG RfRegister
  4131. )
  4132. /*++
  4133. Routine Description:
  4134. This routine read an RF register for the given chain.
  4135. Arguments:
  4136. Device - Supplies a pointer to the RTLW81 device.
  4137. Chain - Supplies the chain whose RF register is to be read.
  4138. RfRegister - Supplies the RF register to read.
  4139. Return Value:
  4140. Returns the value read from the RF register..
  4141. --*/
  4142. {
  4143. ULONG ChainValues[RTLW81_MAX_CHAIN_COUNT];
  4144. ULONG Register;
  4145. ULONG Value;
  4146. Register = Rtlw81RegisterHssiParameter2;
  4147. ChainValues[0] = RTLW81_READ_REGISTER32(Device, Register);
  4148. if (Chain != 0) {
  4149. Register += (Chain * 8);
  4150. ChainValues[Chain] = RTLW81_READ_REGISTER32(Device, Register);
  4151. }
  4152. //
  4153. // Initiate the read from the RF register.
  4154. //
  4155. Value = ChainValues[0];
  4156. Value &= ~RTLW81_HSSI_PARAMETER2_READ_EDGE;
  4157. Register = Rtlw81RegisterHssiParameter2;
  4158. RTLW81_WRITE_REGISTER32(Device, Register, Value);
  4159. HlBusySpin(1000);
  4160. Value = ChainValues[Chain];
  4161. Value &= ~RTLW81_HSSI_PARAMETER2_READ_ADDRESS_MASK;
  4162. Value |= (RfRegister << RTLW81_HSSI_PARAMETER2_READ_ADDRESS_SHIFT) &
  4163. RTLW81_HSSI_PARAMETER2_READ_ADDRESS_MASK;
  4164. Value |= RTLW81_HSSI_PARAMETER2_READ_EDGE;
  4165. Register += (Chain * 8);
  4166. RTLW81_WRITE_REGISTER32(Device, Register, Value);
  4167. HlBusySpin(1000);
  4168. Value = ChainValues[0];
  4169. Value |= RTLW81_HSSI_PARAMETER2_READ_EDGE;
  4170. Register = Rtlw81RegisterHssiParameter2;
  4171. RTLW81_WRITE_REGISTER32(Device, Register, Value);
  4172. HlBusySpin(1000);
  4173. //
  4174. // Read the value back from the appropriate register.
  4175. //
  4176. Register = Rtlw81RegisterHssiParameter1 + (Chain * 8);
  4177. Value = RTLW81_READ_REGISTER32(Device, Register);
  4178. if ((Value & RTLW81_HSSI_PARAMETER1_PI) != 0) {
  4179. Register = Rtlw81RegisterHspiReadback + (Chain * 4);
  4180. } else {
  4181. Register = Rtlw81RegisterLssiReadback + (Chain * 4);
  4182. }
  4183. Value = RTLW81_READ_REGISTER32(Device, Register);
  4184. Value = (Value & RTLW81_LSSI_READBACK_DATA_MASK) >>
  4185. RTLW81_LSSI_READBACK_DATA_SHIFT;
  4186. return Value;
  4187. }
  4188. KSTATUS
  4189. Rtlw81pSendFirmwareCommand (
  4190. PRTLW81_DEVICE Device,
  4191. UCHAR CommandId,
  4192. PVOID Message,
  4193. ULONG MessageLength
  4194. )
  4195. /*++
  4196. Routine Description:
  4197. This routine sends a firmware command to the wireless RTL81xx device.
  4198. Arguments:
  4199. Device - Supplies a pointer to the RTLW81xx device.
  4200. CommandId - Supplies the firmware command ID to send to the device.
  4201. Message - Supplies a pointer to the command message.
  4202. MessageLength - Supplies the length of the command message to write.
  4203. Return Value:
  4204. Status code.
  4205. --*/
  4206. {
  4207. RTLW81_FIRMWARE_COMMAND Command;
  4208. ULONGLONG CurrentTime;
  4209. USHORT Register;
  4210. KSTATUS Status;
  4211. ULONGLONG Timeout;
  4212. ULONGLONG TimeoutTicks;
  4213. ULONG Value;
  4214. //
  4215. // Wait for the firmware box to be ready to receive the command.
  4216. //
  4217. CurrentTime = KeGetRecentTimeCounter();
  4218. TimeoutTicks = HlQueryTimeCounterFrequency() * RTLW81_DEVICE_TIMEOUT;
  4219. Timeout = CurrentTime + TimeoutTicks;
  4220. do {
  4221. Value = RTLW81_READ_REGISTER8(Device, Rtlw81RegisterHmetfr0);
  4222. if ((Value & (1 << Device->FirmwareBox)) == 0) {
  4223. break;
  4224. }
  4225. CurrentTime = KeGetRecentTimeCounter();
  4226. } while (CurrentTime > Timeout);
  4227. if (CurrentTime > Timeout) {
  4228. Status = STATUS_TIMEOUT;
  4229. goto SendFirmwareCommandEnd;
  4230. }
  4231. //
  4232. // Write the command to the current firmware box.
  4233. //
  4234. RtlZeroMemory(&Command, sizeof(RTLW81_FIRMWARE_COMMAND));
  4235. Command.Id = CommandId;
  4236. if (MessageLength > RTLW81_FIRMWARE_COMMAND_MAX_NO_EXTENSION_LENGTH) {
  4237. Command.Id |= RTLW81_FIRMWARE_COMMAND_FLAG_EXTENSION;
  4238. }
  4239. ASSERT(MessageLength <= RTLW81_FIRMWARE_COMMAND_MAX_MESSAGE_LENGTH);
  4240. RtlCopyMemory(Command.Message, Message, MessageLength);
  4241. Register = Rtlw81RegisterHmeBoxExtension + (Device->FirmwareBox * 2);
  4242. Status = Rtlw81pWriteData(Device, Register, (PUCHAR)&Command + 4, 2);
  4243. if (!KSUCCESS(Status)) {
  4244. goto SendFirmwareCommandEnd;
  4245. }
  4246. Register = Rtlw81RegisterHmeBox + (Device->FirmwareBox * 4);
  4247. Status = Rtlw81pWriteData(Device, Register, (PUCHAR)&Command, 4);
  4248. if (!KSUCCESS(Status)) {
  4249. goto SendFirmwareCommandEnd;
  4250. }
  4251. //
  4252. // Move to the next firmware box.
  4253. //
  4254. Device->FirmwareBox += 1;
  4255. Device->FirmwareBox %= RTLW81_FIRMWARE_BOX_COUNT;
  4256. SendFirmwareCommandEnd:
  4257. return Status;
  4258. }
  4259. KSTATUS
  4260. Rtlw81pSubmitBulkInTransfers (
  4261. PRTLW81_DEVICE Device
  4262. )
  4263. /*++
  4264. Routine Description:
  4265. This routine submits all the bulk IN transfers allocated for the device.
  4266. Arguments:
  4267. Device - Supplies a pointer to an SM95 device.
  4268. Return Value:
  4269. Status code.
  4270. --*/
  4271. {
  4272. ULONG Index;
  4273. KSTATUS Status;
  4274. for (Index = 0; Index < RTLW81_BULK_IN_TRANSFER_COUNT; Index += 1) {
  4275. Status = UsbSubmitTransfer(Device->BulkInTransfer[Index]);
  4276. if (!KSUCCESS(Status)) {
  4277. break;
  4278. }
  4279. }
  4280. return Status;
  4281. }
  4282. VOID
  4283. Rtlw81pCancelBulkInTransfers (
  4284. PRTLW81_DEVICE Device
  4285. )
  4286. /*++
  4287. Routine Description:
  4288. This routine attempts to cancel all the bulk IN transfers for the device.
  4289. Arguments:
  4290. Device - Supplies a pointer to an SM95 device.
  4291. Return Value:
  4292. None.
  4293. --*/
  4294. {
  4295. ULONG Index;
  4296. for (Index = 0; Index < RTLW81_BULK_IN_TRANSFER_COUNT; Index += 1) {
  4297. UsbCancelTransfer(Device->BulkInTransfer[Index], FALSE);
  4298. }
  4299. return;
  4300. }
  4301. PRTLW81_BULK_OUT_TRANSFER
  4302. Rtlw81pAllocateBulkOutTransfer (
  4303. PRTLW81_DEVICE Device,
  4304. RTLW81_BULK_OUT_TYPE Type
  4305. )
  4306. /*++
  4307. Routine Description:
  4308. This routine allocates an RTLW81 bulk OUT transfer. If there are no free
  4309. bulk OUT transfers ready to go, it will create a new transfer.
  4310. Arguments:
  4311. Device - Supplies a pointer to the RTLW81 device in need of a new transfer.
  4312. Type - Supplies the type of bulk out transfer to allocate.
  4313. Return Value:
  4314. Returns a pointer to the allocated RTLW81 bulk OUT transfer on success or
  4315. NULL on failure.
  4316. --*/
  4317. {
  4318. UCHAR Endpoint;
  4319. UCHAR EndpointIndex;
  4320. ULONG Flags;
  4321. PLIST_ENTRY FreeList;
  4322. PRTLW81_BULK_OUT_TRANSFER Rtlw81Transfer;
  4323. PUSB_TRANSFER UsbTransfer;
  4324. ASSERT(KeGetRunLevel() == RunLevelLow);
  4325. EndpointIndex = Device->BulkOutTypeEndpointIndex[Type];
  4326. Endpoint = Device->BulkOutEndpoint[EndpointIndex];
  4327. FreeList = &(Device->BulkOutFreeTransferList[EndpointIndex]);
  4328. //
  4329. // Loop attempting to use the most recently released existing transfer, but
  4330. // allocate a new transfer if none are available.
  4331. //
  4332. Rtlw81Transfer = NULL;
  4333. while (Rtlw81Transfer == NULL) {
  4334. if (LIST_EMPTY(FreeList) != FALSE) {
  4335. Rtlw81Transfer = MmAllocatePagedPool(
  4336. sizeof(RTLW81_BULK_OUT_TRANSFER),
  4337. RTLW81_ALLOCATION_TAG);
  4338. if (Rtlw81Transfer == NULL) {
  4339. goto AllocateBulkOutTransferEnd;
  4340. }
  4341. Flags = USB_TRANSFER_FLAG_FORCE_SHORT_TRANSFER;
  4342. UsbTransfer = UsbAllocateTransfer(Device->UsbCoreHandle,
  4343. Endpoint,
  4344. RTLW81_MAX_PACKET_SIZE,
  4345. Flags);
  4346. if (UsbTransfer == NULL) {
  4347. MmFreePagedPool(Rtlw81Transfer);
  4348. Rtlw81Transfer = NULL;
  4349. goto AllocateBulkOutTransferEnd;
  4350. }
  4351. UsbTransfer->Direction = UsbTransferDirectionOut;
  4352. UsbTransfer->CallbackRoutine = Rtlw81pBulkOutTransferCompletion;
  4353. UsbTransfer->UserData = Rtlw81Transfer;
  4354. Rtlw81Transfer->Device = Device;
  4355. Rtlw81Transfer->UsbTransfer = UsbTransfer;
  4356. Rtlw81Transfer->Packet = NULL;
  4357. Rtlw81Transfer->EndpointIndex = EndpointIndex;
  4358. } else {
  4359. KeAcquireQueuedLock(Device->BulkOutListLock);
  4360. if (LIST_EMPTY(FreeList) == FALSE) {
  4361. Rtlw81Transfer = LIST_VALUE(FreeList->Next,
  4362. RTLW81_BULK_OUT_TRANSFER,
  4363. ListEntry);
  4364. LIST_REMOVE(&(Rtlw81Transfer->ListEntry));
  4365. }
  4366. KeReleaseQueuedLock(Device->BulkOutListLock);
  4367. }
  4368. }
  4369. AllocateBulkOutTransferEnd:
  4370. return Rtlw81Transfer;
  4371. }
  4372. VOID
  4373. Rtlw81pFreeBulkOutTransfer (
  4374. PRTLW81_BULK_OUT_TRANSFER Transfer
  4375. )
  4376. /*++
  4377. Routine Description:
  4378. This routine releases an RTLW81 bulk OUT transfer for recycling.
  4379. Arguments:
  4380. Transfer - Supplies a pointer to the RTLW81 transfer to be recycled.
  4381. Return Value:
  4382. None.
  4383. --*/
  4384. {
  4385. PRTLW81_DEVICE Device;
  4386. PLIST_ENTRY FreeList;
  4387. ASSERT(KeGetRunLevel() == RunLevelLow);
  4388. //
  4389. // Insert it onto the head of the list so it stays hot.
  4390. //
  4391. Device = Transfer->Device;
  4392. FreeList = &(Device->BulkOutFreeTransferList[Transfer->EndpointIndex]);
  4393. KeAcquireQueuedLock(Device->BulkOutListLock);
  4394. INSERT_AFTER(&(Transfer->ListEntry), FreeList);
  4395. KeReleaseQueuedLock(Device->BulkOutListLock);
  4396. return;
  4397. }
  4398. VOID
  4399. Rtlw81pBulkOutTransferCompletion (
  4400. PUSB_TRANSFER Transfer
  4401. )
  4402. /*++
  4403. Routine Description:
  4404. This routine is called when an asynchronous I/O request completes with
  4405. success, failure, or is cancelled.
  4406. Arguments:
  4407. Transfer - Supplies a pointer to the transfer that completed.
  4408. Return Value:
  4409. None.
  4410. --*/
  4411. {
  4412. PRTLW81_BULK_OUT_TRANSFER Rtlw81Transfer;
  4413. Rtlw81Transfer = Transfer->UserData;
  4414. RtlAtomicAdd32(&(Rtlw81Transfer->Device->BulkOutTransferCount), -1);
  4415. NetFreeBuffer(Rtlw81Transfer->Packet);
  4416. Rtlw81Transfer->Packet = NULL;
  4417. Rtlw81pFreeBulkOutTransfer(Rtlw81Transfer);
  4418. return;
  4419. }
  4420. VOID
  4421. Rtlw81pSetLed (
  4422. PRTLW81_DEVICE Device,
  4423. BOOL Enable
  4424. )
  4425. /*++
  4426. Routine Description:
  4427. This routine modified the RTL81xx wireless device's LED state.
  4428. Arguments:
  4429. Device - Supplies a pointer to the RTLW81 device.
  4430. Enable - Supplies a boolean indicating if the LED should be turned on
  4431. (TRUE) or turned off (FALSE).
  4432. Return Value:
  4433. None.
  4434. --*/
  4435. {
  4436. UCHAR Value;
  4437. Value = RTLW81_READ_REGISTER8(Device, Rtlw81RegisterLedConfig0);
  4438. Value &= RTLW81_LED_SAVE_MASK;
  4439. if (Enable == FALSE) {
  4440. Value |= RTLW81_LED_DISABLE;
  4441. }
  4442. RTLW81_WRITE_REGISTER8(Device, Rtlw81RegisterLedConfig0, Value);
  4443. return;
  4444. }
  4445. KSTATUS
  4446. Rtlw81pGetRssi (
  4447. PRTLW81_DEVICE Device,
  4448. PVOID PhyStatus,
  4449. ULONG PhyStatusSize,
  4450. ULONG Rate,
  4451. PLONG Rssi
  4452. )
  4453. /*++
  4454. Routine Description:
  4455. This routine determines the RSSI value from a received network packet based
  4456. on the PHY status and the rate.
  4457. Arguments:
  4458. Device - Supplies a pointer to the RTL81xx wireless device that received
  4459. the PHY status.
  4460. PhyStatus - Supplies a pointer to the PHY status to parse for RSSI
  4461. information.
  4462. PhyStatusSize - Supplies the size of the PHY status in bytes.
  4463. Rate - Supplies the data rate at which the PHY status was received.
  4464. Rssi - Supplies a pointer that receives the RSSI value.
  4465. Return Value:
  4466. Status code.
  4467. --*/
  4468. {
  4469. ULONG AgcIndexMask;
  4470. ULONG AgcIndexShift;
  4471. UCHAR AgcReport;
  4472. ULONG AgcValueMask;
  4473. ULONG AgcValueShift;
  4474. PRTLW81_8188E_PHY_STATUS_CCK Cck8188e;
  4475. PRTLW81_DEFAULT_PHY_STATUS_CCK CckDefault;
  4476. UCHAR LnaIndex;
  4477. PRTLW81_PHY_STATUS_OFDM Ofdm;
  4478. ULONG OfdmStatus;
  4479. UCHAR ReportIndex;
  4480. LONG RssiValue;
  4481. KSTATUS Status;
  4482. UCHAR VgaIndex;
  4483. //
  4484. // If the packet's rate is not high throughput then the PHY status is CCK
  4485. // data.
  4486. //
  4487. if (Rate <= RTLW81_PHY_STATUS_MAX_CCK_RATE) {
  4488. if ((Device->Flags & RTLW81_FLAG_8188E) != 0) {
  4489. if (PhyStatusSize < sizeof(RTLW81_8188E_PHY_STATUS_CCK)) {
  4490. Status = STATUS_DATA_LENGTH_MISMATCH;
  4491. goto GetRssiEnd;
  4492. }
  4493. Cck8188e = (PRTLW81_8188E_PHY_STATUS_CCK)PhyStatus;
  4494. AgcReport = Cck8188e->AgcReport;
  4495. LnaIndex = (AgcReport & RTLW81_8188E_PHY_CCK_AGC_REPORT_LNA_MASK) >>
  4496. RTLW81_8188E_PHY_CCK_AGC_REPORT_LNA_SHIFT;
  4497. VgaIndex = (AgcReport & RTLW81_8188E_PHY_CCK_AGC_REPORT_VGA_MASK) >>
  4498. RTLW81_8188E_PHY_CCK_AGC_REPORT_VGA_SHIFT;
  4499. switch (LnaIndex) {
  4500. case 7:
  4501. if (VgaIndex <= 27) {
  4502. RssiValue = -100 + 2 * (27 - VgaIndex);
  4503. } else {
  4504. RssiValue = -100;
  4505. }
  4506. break;
  4507. case 6:
  4508. RssiValue = -48 + (2 * (2 - VgaIndex));
  4509. break;
  4510. case 5:
  4511. RssiValue = -42 + (2 * (7 - VgaIndex));
  4512. break;
  4513. case 4:
  4514. RssiValue = -36 + (2 * (7 - VgaIndex));
  4515. break;
  4516. case 3:
  4517. RssiValue = -24 + (2 * (7 - VgaIndex));
  4518. break;
  4519. case 2:
  4520. RssiValue = -12 + (2 * (5 - VgaIndex));
  4521. break;
  4522. case 1:
  4523. RssiValue = 8 - (2 * VgaIndex);
  4524. break;
  4525. case 0:
  4526. RssiValue = 14 - (2 * VgaIndex);
  4527. break;
  4528. default:
  4529. RssiValue = 0;
  4530. break;
  4531. }
  4532. RssiValue += 6;
  4533. } else {
  4534. if (PhyStatusSize < sizeof(RTLW81_DEFAULT_PHY_STATUS_CCK)) {
  4535. Status = STATUS_DATA_LENGTH_MISMATCH;
  4536. goto GetRssiEnd;
  4537. }
  4538. CckDefault = (PRTLW81_DEFAULT_PHY_STATUS_CCK)PhyStatus;
  4539. AgcReport = CckDefault->AgcReport;
  4540. AgcIndexMask = RTLW81_DEFAULT_PHY_CCK_HP_AGC_REPORT_INDEX_MASK;
  4541. AgcIndexShift = RTLW81_DEFAULT_PHY_CCK_HP_AGC_REPORT_INDEX_SHIFT;
  4542. AgcValueMask = RTLW81_DEFAULT_PHY_CCK_HP_AGC_REPORT_VALUE_MASK;
  4543. AgcValueShift = RTLW81_DEFAULT_PHY_CCK_HP_AGC_REPORT_VALUE_SHIFT;
  4544. if ((Device->Flags & RTLW81_FLAG_CCK_HIGH_POWER) == 0) {
  4545. AgcIndexMask = RTLW81_DEFAULT_PHY_CCK_AGC_REPORT_INDEX_MASK;
  4546. AgcIndexShift = RTLW81_DEFAULT_PHY_CCK_AGC_REPORT_INDEX_SHIFT;
  4547. AgcValueMask = RTLW81_DEFAULT_PHY_CCK_AGC_REPORT_VALUE_MASK;
  4548. AgcValueShift = RTLW81_DEFAULT_PHY_CCK_AGC_REPORT_VALUE_SHIFT;
  4549. }
  4550. ReportIndex = (AgcReport & AgcIndexMask) >> AgcIndexShift;
  4551. RssiValue = ((AgcReport & AgcValueMask) >> AgcValueShift) << 1;
  4552. RssiValue = Rtlw81DefaultCckAgcReportOffsets[ReportIndex] -
  4553. RssiValue;
  4554. }
  4555. //
  4556. // Otherwise the PHY status is OFDM data.
  4557. //
  4558. } else {
  4559. if (PhyStatusSize < sizeof(RTLW81_PHY_STATUS_OFDM)) {
  4560. Status = STATUS_DATA_LENGTH_MISMATCH;
  4561. goto GetRssiEnd;
  4562. }
  4563. Ofdm = (PRTLW81_PHY_STATUS_OFDM)PhyStatus;
  4564. OfdmStatus = Ofdm->PhyStatus[RTLW81_PHY_OFDM_AGC_REPORT_INDEX];
  4565. OfdmStatus = (OfdmStatus & RTLW81_PHY_OFDM_AGC_REPORT_MASK) >>
  4566. RTLW81_PHY_OFDM_AGC_REPORT_SHIFT;
  4567. RssiValue = OfdmStatus - RTLW81_PHY_OFDM_AGC_REPORT_OFFSET;
  4568. }
  4569. *Rssi = RssiValue;
  4570. Status = STATUS_SUCCESS;
  4571. GetRssiEnd:
  4572. return Status;
  4573. }