1
0

ehci.h 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512
  1. /*++
  2. Copyright (c) 2013 Minoca Corp. All Rights Reserved
  3. Module Name:
  4. ehci.h
  5. Abstract:
  6. This header contains internal definitions for the EHCI USB Host Controller
  7. driver.
  8. Author:
  9. Evan Green 18-Mar-2013
  10. --*/
  11. //
  12. // ------------------------------------------------------------------- Includes
  13. //
  14. #include "ehcihw.h"
  15. #include "ehcidbg.h"
  16. #include <minoca/kernel/kdebug.h>
  17. #include <minoca/kernel/kdusb.h>
  18. //
  19. // ---------------------------------------------------------------- Definitions
  20. //
  21. //
  22. // Define the EHCI allocation tag.
  23. //
  24. #define EHCI_ALLOCATION_TAG 0x69636845 // 'ichE'
  25. #define EHCI_BLOCK_ALLOCATION_TAG 0x6C426845 // 'lBhE'
  26. //
  27. // Define the block expansion count for the EHCI transfer and queue block
  28. // allocator. This is defined in number of blocks.
  29. //
  30. #define EHCI_BLOCK_ALLOCATOR_EXPANSION_COUNT 40
  31. //
  32. // Define the required alignment for EHCI transfers and queues.
  33. //
  34. #define EHCI_BLOCK_ALLOCATOR_ALIGNMENT EHCI_LINK_ALIGNMENT
  35. //
  36. // Define the number of levels in the periodic schedule tree.
  37. //
  38. #define EHCI_PERIODIC_SCHEDULE_TREE_DEPTH 8
  39. //
  40. // Define the set of flags for the EHCI transfer set.
  41. //
  42. #define EHCI_TRANSFER_SET_FLAG_QUEUED 0x00000001
  43. #define EHCI_TRANSFER_SET_FLAG_CANCELLING 0x00000002
  44. //
  45. // ------------------------------------------------------ Data Type Definitions
  46. //
  47. typedef struct _EHCI_TRANSFER_SET EHCI_TRANSFER_SET, *PEHCI_TRANSFER_SET;
  48. /*++
  49. Structure Description:
  50. This structure stores information about an EHCI transfer.
  51. Members:
  52. GlobalListEntry - Stores pointers to the next and previous transfers in the
  53. global list of in-flight transfers.
  54. EndpointListEntry - Stores pointers to the next and previous transfers in
  55. the endpoint queue.
  56. Set - Stores a pointer to the transfer set that this transfer is a part of.
  57. HardwareTransfer - Stores a pointer to the hardware defined transfer
  58. descriptor.
  59. PhysicalAddress - Stores the physical address of the hardware transfer
  60. descriptor.
  61. TransferLength - Stores the length of the transfer (as the hardware
  62. decrements the field towards 0).
  63. LastTransfer - Stores a boolean indicating whether this is the last
  64. transfer submitted in the set.
  65. --*/
  66. typedef struct _EHCI_TRANSFER {
  67. LIST_ENTRY GlobalListEntry;
  68. LIST_ENTRY EndpointListEntry;
  69. PEHCI_TRANSFER_SET Set;
  70. PEHCI_TRANSFER_DESCRIPTOR HardwareTransfer;
  71. PHYSICAL_ADDRESS PhysicalAddress;
  72. ULONG TransferLength;
  73. BOOL LastTransfer;
  74. } EHCI_TRANSFER, *PEHCI_TRANSFER;
  75. /*++
  76. Structure Description:
  77. This structure stores information about an EHCI transfer queue.
  78. Members:
  79. ListEntry - Stores pointers to the next and previous transfer queue
  80. attached to the EHCI controller.
  81. DummyTransfer - Stores a pointer to the current inactive dummy transfer
  82. that gets left on every queue. This dummy transfer is needed so that
  83. additional sets of transfers can be added to a queue without race
  84. conditions. The dummy transfer rotates around as sets of transfers are
  85. added, as the first transfer in that set becomes the new dummy.
  86. HardwareQueueHead - Stores a pointer to the hardware defined transfer queue
  87. head. This is unused for isochronous transfers.
  88. PhysicalAddress - Stores the physical address of the hardware queue head.
  89. AsyncOnAdvanceCancel - Stores a boolean indicating whether or not the queue
  90. is being processed by the "async on advance" interrupt due to
  91. cancellation (TRUE) or destruction (FALSE).
  92. --*/
  93. typedef struct _EHCI_TRANSFER_QUEUE {
  94. LIST_ENTRY ListEntry;
  95. PEHCI_TRANSFER DummyTransfer;
  96. PEHCI_QUEUE_HEAD HardwareQueueHead;
  97. PHYSICAL_ADDRESS PhysicalAddress;
  98. BOOL AsyncOnAdvanceCancel;
  99. } EHCI_TRANSFER_QUEUE, *PEHCI_TRANSFER_QUEUE;
  100. /*++
  101. Structure Description:
  102. This structure stores information about an EHCI endpoint.
  103. Members:
  104. ListEntry - Stores pointers to the next and previous endpoints attached to
  105. the EHCI controller.
  106. TransferListHead - Stores the head of the list of transfers on this queue.
  107. Queue - Stores the EHCI transfer queue for this endpoint.
  108. TransferType - Stores the transfer type of the endpoint.
  109. Speed - Stores the speed of the device exposing the endpoint.
  110. MaxPacketSize - Stores the maximum number of bytes that can be moved in a
  111. packet for this endpoint.
  112. PollRate - Stores the interrupt poll rate, in (micro)frames.
  113. EndpointNumber - Stores the endpoint number, as defined by the USB device.
  114. --*/
  115. typedef struct _EHCI_ENDPOINT {
  116. LIST_ENTRY ListEntry;
  117. LIST_ENTRY TransferListHead;
  118. EHCI_TRANSFER_QUEUE Queue;
  119. USB_TRANSFER_TYPE TransferType;
  120. USB_DEVICE_SPEED Speed;
  121. ULONG MaxPacketSize;
  122. ULONG PollRate;
  123. UCHAR EndpointNumber;
  124. } EHCI_ENDPOINT, *PEHCI_ENDPOINT;
  125. /*++
  126. Structure Description:
  127. This structure stores a collection of EHCI transfers that together
  128. comprise a USB transfer.
  129. Members:
  130. ListEntry - Stores pointers to the next and previous transfer sets in
  131. whatever list of transfer sets this set is in (usually the set of
  132. lists waiting to be processed once the async advance doorbel is rung).
  133. TransferCount - Stores the number of elements in the transfer array.
  134. Flags - Stores a bitmask of flags for the transfer set. See
  135. EHCI_TRANSFER_SET_FLAG_* for definitions.
  136. UsbTransfer - Stores a pointer to the transfer as defined by the USB core
  137. library. Several EHCI transfers may constitute and point to a single USB
  138. transfer.
  139. Endpoint - Stores a pointer to the endpoint that owns this set of transfers.
  140. Transfer - Stores an array of pointers to EHCI transfers.
  141. --*/
  142. struct _EHCI_TRANSFER_SET {
  143. LIST_ENTRY ListEntry;
  144. ULONG TransferCount;
  145. ULONG Flags;
  146. PUSB_TRANSFER_INTERNAL UsbTransfer;
  147. PEHCI_ENDPOINT Endpoint;
  148. PEHCI_TRANSFER Transfer[ANYSIZE_ARRAY];
  149. };
  150. /*++
  151. Structure Description:
  152. This structure stores USB state for an EHCI controller.
  153. Members:
  154. RegisterBase - Stores the virtual address where the Operational Registers
  155. are mapped.
  156. PhysicalBase - Stores the physical address of the base of the registers
  157. (the base of EHCI itself, not the operational registers).
  158. PeriodicSchedule - Stores a pointer to the frame list schedule used by the
  159. controller.
  160. PeriodicScheduleIoBuffer - Stores a pointer to the I/O buffer containing the
  161. periodic schedule.
  162. AsynchronousSchedule - Stores the empty transfer queue that represents the
  163. head of the asynchronous schedule.
  164. IsochronousTransferListHead - Stores the list head of all active
  165. Isochronous transfers in the schedule.
  166. BlockAllocator - Stores a pointer to the block allocator used to
  167. allocate all queues and transfers.
  168. TransferListHead - Stores the global list of active transfers on the
  169. schedule.
  170. AsyncOnAdvanceReadyListHead - Stores the list of transfer queues that have
  171. been removed from the asynchronous schedule and that the host
  172. controller can no longer reach.
  173. AsyncOnAdvancePendingListHead - Stores the list of transfer queues that
  174. have been removed from the asynchronous schedule, but that the host
  175. controller may still be able to reach.
  176. QueuesToDestroyListHead - Stores the list of transfer queues that need to
  177. be destroyed by the destroy queues work item.
  178. Lock - Stores the lock that protects access to all list entries under this
  179. controller. It must be a spin lock because it synchronizes with a DPC,
  180. which cannot block.
  181. UsbCoreHandle - Stores the handle returned by the USB core that identifies
  182. this controller.
  183. CommandRegister - Stores the current state of the USB command register
  184. (to avoid unnecessary reads).
  185. PendingStatusBits - Stores the bits in the USB status register that have
  186. not yet been addressed by the DPC.
  187. InterruptHandle - Stores the interrupt handle of the connected interrupt.
  188. InterruptTree - Stores an array of empty transfer queues at each level of
  189. the periodic schedule tree. Think of each frame in the schedule as a
  190. leaf node, and each leaf node points at a more common entry, which
  191. points at an even more common entry, etc. The last entry in this array
  192. is polled every millisecond, the next last one every 2ms, then every
  193. 4ms, etc.
  194. DestroyQueuesWorkItem - Stores a pointer to a work item that destroys queue
  195. heads that have been completely removed from the schedule.
  196. PortCount - Stores the number of ports on the EHCI host controller.
  197. EndpointCount - Stores the number of active endpoints in the controller.
  198. EndpointListHead - Stores the head of the list of endpoints.
  199. HandoffData - Stores an optional pointer to the kernel debugger handoff
  200. data.
  201. --*/
  202. typedef struct _EHCI_CONTROLLER {
  203. PVOID RegisterBase;
  204. PHYSICAL_ADDRESS PhysicalBase;
  205. PEHCI_PERIODIC_SCHEDULE PeriodicSchedule;
  206. PIO_BUFFER PeriodicScheduleIoBuffer;
  207. EHCI_TRANSFER_QUEUE AsynchronousSchedule;
  208. LIST_ENTRY IsochronousTransferListHead;
  209. PBLOCK_ALLOCATOR BlockAllocator;
  210. LIST_ENTRY TransferListHead;
  211. LIST_ENTRY AsyncOnAdvanceReadyListHead;
  212. LIST_ENTRY AsyncOnAdvancePendingListHead;
  213. LIST_ENTRY QueuesToDestroyListHead;
  214. KSPIN_LOCK Lock;
  215. HANDLE UsbCoreHandle;
  216. ULONG CommandRegister;
  217. volatile ULONG PendingStatusBits;
  218. HANDLE InterruptHandle;
  219. EHCI_TRANSFER_QUEUE InterruptTree[EHCI_PERIODIC_SCHEDULE_TREE_DEPTH];
  220. PWORK_ITEM DestroyQueuesWorkItem;
  221. ULONG PortCount;
  222. ULONG EndpointCount;
  223. LIST_ENTRY EndpointListHead;
  224. PEHCI_DEBUG_HANDOFF_DATA HandoffData;
  225. } EHCI_CONTROLLER, *PEHCI_CONTROLLER;
  226. //
  227. // -------------------------------------------------------------------- Globals
  228. //
  229. extern PDRIVER EhciDriver;
  230. //
  231. // -------------------------------------------------------- Function Prototypes
  232. //
  233. PEHCI_CONTROLLER
  234. EhcipInitializeControllerState (
  235. PVOID OperationalRegisterBase,
  236. PHYSICAL_ADDRESS RegisterBasePhysical,
  237. ULONG PortCount,
  238. PDEBUG_USB_HANDOFF_DATA HandoffData
  239. );
  240. /*++
  241. Routine Description:
  242. This routine initializes the state and variables needed to start up an EHCI
  243. host controller.
  244. Arguments:
  245. OperationalRegisterBase - Supplies the virtual address of the base of the
  246. operational registers.
  247. RegisterBasePhysical - Supplies the physical address of the base of the
  248. EHCI registers (not the operational registers).
  249. PortCount - Supplies the number of ports on the EHCI controller.
  250. HandoffData - Supplies an optional pointer to the debug handoff data if the
  251. kernel debugger is using this controller.
  252. Return Value:
  253. Returns a pointer to the EHCI controller state object on success.
  254. NULL on failure.
  255. --*/
  256. VOID
  257. EhcipDestroyControllerState (
  258. PEHCI_CONTROLLER Controller
  259. );
  260. /*++
  261. Routine Description:
  262. This routine destroys the memory associated with an EHCI controller.
  263. Arguments:
  264. Controller - Supplies a pointer to the EHCI controller state to release.
  265. Return Value:
  266. None.
  267. --*/
  268. KSTATUS
  269. EhcipRegisterController (
  270. PEHCI_CONTROLLER Controller,
  271. PDEVICE Device
  272. );
  273. /*++
  274. Routine Description:
  275. This routine registers the started EHCI controller with the core USB
  276. library.
  277. Arguments:
  278. Controller - Supplies a pointer to the EHCI controller state of the
  279. controller to register.
  280. Device - Supplies a pointer to the device object.
  281. Return Value:
  282. Status code.
  283. --*/
  284. VOID
  285. EhcipSetInterruptHandle (
  286. PEHCI_CONTROLLER Controller,
  287. HANDLE InterruptHandle
  288. );
  289. /*++
  290. Routine Description:
  291. This routine saves the handle of the connected interrupt in the EHCI
  292. controller.
  293. Arguments:
  294. Controller - Supplies a pointer to the EHCI controller state.
  295. InterruptHandle - Supplies the connected interrupt handle.
  296. Return Value:
  297. None.
  298. --*/
  299. KSTATUS
  300. EhcipResetController (
  301. PEHCI_CONTROLLER Controller
  302. );
  303. /*++
  304. Routine Description:
  305. This routine resets and starts the EHCI controller.
  306. Arguments:
  307. Controller - Supplies a pointer to the EHCI controller state of the
  308. controller to reset.
  309. Return Value:
  310. Status code.
  311. --*/
  312. INTERRUPT_STATUS
  313. EhcipInterruptService (
  314. PVOID Context
  315. );
  316. /*++
  317. Routine Description:
  318. This routine implements the EHCI interrupt service routine.
  319. Arguments:
  320. Context - Supplies the context pointer given to the system when the
  321. interrupt was connected. In this case, this points to the EHCI
  322. controller.
  323. Return Value:
  324. Interrupt status.
  325. --*/
  326. INTERRUPT_STATUS
  327. EhcipInterruptServiceDpc (
  328. PVOID Parameter
  329. );
  330. /*++
  331. Routine Description:
  332. This routine implements the EHCI dispatch level interrupt service.
  333. Arguments:
  334. Parameter - Supplies the context, in this case the EHCI controller
  335. structure.
  336. Return Value:
  337. None.
  338. --*/