rtl81.h 42 KB

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  1. /*++
  2. Copyright (c) 2014 Minoca Corp. All Rights Reserved
  3. Module Name:
  4. rtl81.h
  5. Abstract:
  6. This header contains definitions for for the Realtek RTL81xx family of
  7. Ethernet controllers.
  8. Author:
  9. Chris Stevens 20-Jun-2014
  10. --*/
  11. //
  12. // ------------------------------------------------------------------- Includes
  13. //
  14. #include <minoca/intrface/pci.h>
  15. //
  16. // --------------------------------------------------------------------- Macros
  17. //
  18. //
  19. // Define macros for accessing a generic register in the controller.
  20. //
  21. #define RTL81_READ_REGISTER32(_Controller, _Register) \
  22. HlReadRegister32((PUCHAR)(_Controller)->ControllerBase + (_Register))
  23. #define RTL81_READ_REGISTER16(_Controller, _Register) \
  24. HlReadRegister16((PUCHAR)(_Controller)->ControllerBase + (_Register))
  25. #define RTL81_READ_REGISTER8(_Controller, _Register) \
  26. HlReadRegister8((PUCHAR)(_Controller)->ControllerBase + (_Register))
  27. #define RTL81_WRITE_REGISTER32(_Controller, _Register, _Value) \
  28. HlWriteRegister32((PUCHAR)(_Controller)->ControllerBase + (_Register), \
  29. (_Value))
  30. #define RTL81_WRITE_REGISTER16(_Controller, _Register, _Value) \
  31. HlWriteRegister16((PUCHAR)(_Controller)->ControllerBase + (_Register), \
  32. (_Value))
  33. #define RTL81_WRITE_REGISTER8(_Controller, _Register, _Value) \
  34. HlWriteRegister8((PUCHAR)(_Controller)->ControllerBase + (_Register), \
  35. (_Value))
  36. //
  37. // ---------------------------------------------------------------- Definitions
  38. //
  39. #define RTL81_ALLOCATION_TAG 0x31387452 // '18tR'
  40. //
  41. // Define the required alignment for transmit descriptor physical addresses.
  42. //
  43. #define RTL81_TRANSMIT_ALIGNMENT sizeof(ULONG)
  44. //
  45. // Define the number of available transmit descriptors for the legacy chips.
  46. //
  47. #define RTL81_TRANSMIT_DESCRIPTOR_COUNT_LEGACY 4
  48. //
  49. // Define the size of the receive packet ring from the hardware's perspective.
  50. //
  51. #define RTL81_RECEIVE_RING_BUFFER_SIZE _64KB
  52. //
  53. // Define the size of the receive packet ring buffer for the legacy chips,
  54. // including the padding to handle wrapping.
  55. //
  56. #define RTL81_RECEIVE_RING_BUFFER_PADDED_SIZE \
  57. (RTL81_RECEIVE_RING_BUFFER_SIZE + 16 + 1536)
  58. //
  59. // Define the alignment of the receive packet ring buffer for the legacy chips.
  60. //
  61. #define RTL81_RECEIVE_RING_BUFFER_ALIGNMENT sizeof(ULONG)
  62. //
  63. // Define the the maximum receive ring buffer offset for the legacy chips.
  64. //
  65. #define RTL81_MAXIMUM_RECEIVE_RING_BUFFER_OFFSET RTL81_RECEIVE_RING_BUFFER_SIZE
  66. //
  67. // Define the adjustment necessary for receive offsets to prevent overflows.
  68. //
  69. #define RTL81_RECEIVE_OFFSET_ADJUSTMENT 16
  70. //
  71. // Define the size of the CRC that comes at the end of a received buffer.
  72. //
  73. #define RTL81_RECEIVE_CRC_LENGTH sizeof(ULONG)
  74. //
  75. // Define the maximum and minimum sizes allowed for a received packet.
  76. //
  77. #define RTL81_MINIMUM_PACKET_LENGTH 64
  78. #define RTL81_MAXIMUM_PACKET_LENGTH _4KB
  79. //
  80. // Define the maximum transmit packet size.
  81. //
  82. #define RTL81_MAX_TRANSMIT_PACKET_SIZE 0xFFF
  83. //
  84. // Define the maximum receive packet size.
  85. //
  86. #define RTL81_MAX_RECEIVE_PACKET_SIZE 0x1FFF
  87. //
  88. // Define the descriptor alignment for the newer RTL81xx chips (i.e. RTL8139C+
  89. // and later).
  90. //
  91. #define RTL81_DESCRIPTOR_ALIGNMENT 256
  92. //
  93. // Define the transmit descriptor count for the older chips that still support
  94. // dynamic descriptor.
  95. //
  96. #define RTL81_TRANSMIT_DESCRIPTOR_COUNT_LIMITED 64
  97. //
  98. // Define the receive descriptor count for the older chips that still support
  99. // dynamic descriptors.
  100. //
  101. #define RTL81_RECEIVE_DESCRIPTOR_COUNT_LIMITED 64
  102. //
  103. // Define the transmit descriptor count for the default chips that support
  104. // dynamic descriptors.
  105. //
  106. #define RTL81_TRANSMIT_DESCRIPTOR_COUNT_DEFAULT 256
  107. //
  108. // Define the receive descriptor count for the default chips that support
  109. // dynamic descriptors.
  110. //
  111. #define RTL81_RECEIVE_DESCRIPTOR_COUNT_DEFAULT 256
  112. //
  113. // Define the maximum size of each receive descriptor's data buffer.
  114. //
  115. // N.B. RTL8168 and RTL8169 can support larger receive buffers, greater than
  116. // the 4KB maximum for RTL8139C+.
  117. //
  118. #define RTL81_RECEIVE_BUFFER_DATA_SIZE 1536
  119. //
  120. // Define how long to wait for the device to perform an initialization
  121. // operation before timing out, in seconds.
  122. //
  123. #define RTL81_DEVICE_TIMEOUT 1
  124. //
  125. // Define a set of flags used to determine if MSI/MSI-X interrupt should be
  126. // used.
  127. //
  128. #define RTL81_PCI_MSI_FLAG_INTERFACE_REGISTERED 0x00000001
  129. #define RTL81_PCI_MSI_FLAG_INTERFACE_AVAILABLE 0x00000002
  130. #define RTL81_PCI_MSI_FLAG_RESOURCES_REQUESTED 0x00000004
  131. #define RTL81_PCI_MSI_FLAG_RESOURCES_ALLOCATED 0x00000008
  132. //
  133. // Define the transmit status register bits.
  134. //
  135. #define RTL81_TRANSMIT_STATUS_CARRIER_SENSE_LOST (1 << 31)
  136. #define RTL81_TRANSMIT_STATUS_ABORT (1 << 30)
  137. #define RTL81_TRANSMIT_STATUS_OUT_OF_WINDOW_COLLISION (1 << 29)
  138. #define RTL81_TRANSMIT_STATUS_CD_HEART_BEAT (1 << 28)
  139. #define RTL81_TRANSMIT_STATUS_COLLISION_COUNT_MASK (0xF << 24)
  140. #define RTL81_TRANSMIT_STATUS_COLLISION_COUNT_SHIFT 24
  141. #define RTL81_TRANSMIT_STATUS_EARLY_TRANSMIT_THRESHOLD_MASK (0x3F << 16)
  142. #define RTL81_TRANSMIT_STATUS_EARLY_TRANSMIT_THRESHOLD_SHIFT 16
  143. #define RTL81_TRANSMIT_STATUS_OK (1 << 15)
  144. #define RTL81_TRANSMIT_STATUS_FIFO_UNDERRUN (1 << 14)
  145. #define RTL81_TRANSMIT_STATUS_OWN (1 << 13)
  146. #define RTL81_TRANSMIT_STATUS_SIZE_MASK (0xFFF << 0)
  147. #define RTL81_TRANSMIT_STATUS_SIZE_SHIFT 0
  148. //
  149. // Define the early receive status register bits.
  150. //
  151. #define RTL81_EARLY_RECEIVE_STATUS_GOOD_PACKET 0x08
  152. #define RTL81_EARLY_RECEIVE_STATUS_BAD_PACKET 0x04
  153. #define RTL81_EARLY_RECEIVE_STATUS_OVERWRITE 0x02
  154. #define RTL81_EARLY_RECEIVE_STATUS_OK 0x01
  155. //
  156. // Define the command register bits.
  157. //
  158. #define RTL81_COMMAND_REGISTER_RESET 0x10
  159. #define RTL81_COMMAND_REGISTER_RECEIVE_ENABLE 0x08
  160. #define RTL81_COMMAND_REGISTER_TRANSMIT_ENABLE 0x04
  161. #define RTL81_COMMAND_REGISTER_BUFFER_EMPTY 0x01
  162. //
  163. // Define the interrupt mask and status register bits.
  164. //
  165. #define RTL81_INTERRUPT_SYSTEM_ERROR 0x8000
  166. #define RTL81_INTERRUPT_TIMEOUT 0x4000
  167. #define RTL81_INTERRUPT_CABLE_LENGTH_CHANGE 0x2000
  168. #define RTL81_INTERRUPT_SOFTWARE 0x0100
  169. #define RTL81_INTERRUPT_TRANSMIT_UNAVAILABLE 0x0080
  170. #define RTL81_INTERRUPT_RECEIVE_FIFO_OVERFLOW 0x0040
  171. #define RTL81_INTERRUPT_PACKET_UNDERRUN 0x0020
  172. #define RTL81_INTERRUPT_LINK_CHANGE 0x0020
  173. #define RTL81_INTERRUPT_RECEIVE_OVERFLOW 0x0010
  174. #define RTL81_INTERRUPT_TRANSMIT_ERROR 0x0008
  175. #define RTL81_INTERRUPT_TRANSMIT_OK 0x0004
  176. #define RTL81_INTERRUPT_RECEIVE_ERROR 0x0002
  177. #define RTL81_INTERRUPT_RECEIVE_OK 0x0001
  178. //
  179. // Define the default set of interrupts to enable.
  180. //
  181. #define RTL81_DEFAULT_INTERRUPT_MASK \
  182. (RTL81_INTERRUPT_TRANSMIT_OK | \
  183. RTL81_INTERRUPT_RECEIVE_OK | \
  184. RTL81_INTERRUPT_RECEIVE_OVERFLOW | \
  185. RTL81_INTERRUPT_TRANSMIT_ERROR | \
  186. RTL81_INTERRUPT_RECEIVE_ERROR | \
  187. RTL81_INTERRUPT_RECEIVE_FIFO_OVERFLOW | \
  188. RTL81_INTERRUPT_TRANSMIT_UNAVAILABLE | \
  189. RTL81_INTERRUPT_TIMEOUT | \
  190. RTL81_INTERRUPT_SYSTEM_ERROR | \
  191. RTL81_INTERRUPT_LINK_CHANGE)
  192. //
  193. // Define the transmit configuration register bits.
  194. //
  195. #define RTL81_TRANSMIT_CONFIGURATION_HARDWARE_VERSION_MASK 0x7CC00000
  196. #define RTL81_TRANSMIT_CONFIGURATION_INTERFRAME_GAP_MASK (0x3 << 24)
  197. #define RTL81_TRANSMIT_CONFIGURATION_INTERFRAME_GAP_SHIFT 24
  198. #define RTL81_TRANSMIT_CONFIGURATION_INTERFRAME_GAP_DEFAULT 0x3
  199. #define RTL81_TRANSMIT_CONFIGURATION_INTERFRAME_GAP_2 (1 << 19)
  200. #define RTL81_TRANSMIT_CONFIGURATION_LOOPBACK_TEST_MASK (0x3 << 17)
  201. #define RTL81_TRANSMIT_CONFIGURATION_LOOPBACK_TEST_SHIFT 17
  202. #define RTL81_TRANSMIT_CONFIGURATION_CRC_NO_APPEND (1 << 16)
  203. #define RTL81_TRANSMIT_CONFIGURATION_MAX_DMA_BURST_MASK (0x7 << 8)
  204. #define RTL81_TRANSMIT_CONFIGURATION_MAX_DMA_BURST_SHIFT 8
  205. #define RTL81_TRANSMIT_CONFIGURATION_MAX_DMA_BURST_16_BYTES 0x0
  206. #define RTL81_TRANSMIT_CONFIGURATION_MAX_DMA_BURST_32_BYTES 0x1
  207. #define RTL81_TRANSMIT_CONFIGURATION_MAX_DMA_BURST_64_BYTES 0x2
  208. #define RTL81_TRANSMIT_CONFIGURATION_MAX_DMA_BURST_128_BYTES 0x3
  209. #define RTL81_TRANSMIT_CONFIGURATION_MAX_DMA_BURST_256_BYTES 0x4
  210. #define RTL81_TRANSMIT_CONFIGURATION_MAX_DMA_BURST_512_BYTES 0x5
  211. #define RTL81_TRANSMIT_CONFIGURATION_MAX_DMA_BURST_1024_BYTES 0x6
  212. #define RTL81_TRANSMIT_CONFIGURATION_MAX_DMA_BURST_2048_BYTES 0x7
  213. #define RTL81_TRANSMIT_CONFIGURATION_RETRY_COUNT_MASK (0xF << 4)
  214. #define RTL81_TRANSMIT_CONFIGURATION_RETRY_COUNT_SHIFT 4
  215. #define RTL81_TRANSMIT_CONFIGURATION_CLEAR_ABORT (1 << 0)
  216. #define RTL81_TRANSMIT_CONFIGURATION_DEFAULT_OPTIONS \
  217. (RTL81_TRANSMIT_CONFIGURATION_MAX_DMA_BURST_2048_BYTES << \
  218. RTL81_TRANSMIT_CONFIGURATION_MAX_DMA_BURST_SHIFT) | \
  219. (RTL81_TRANSMIT_CONFIGURATION_INTERFRAME_GAP_DEFAULT << \
  220. RTL81_TRANSMIT_CONFIGURATION_INTERFRAME_GAP_SHIFT)
  221. //
  222. // Define various hardware versions for the RTL81xx chips.
  223. //
  224. #define RTL81_HARDWARE_VERSION_8101 0x74C00000
  225. #define RTL81_HARDWARE_VERSION_8102EL 0x24800000
  226. #define RTL81_HARDWARE_VERSION_8130 0x7C000000
  227. #define RTL81_HARDWARE_VERSION_8139 0x60000000
  228. #define RTL81_HARDWARE_VERSION_8139A 0x70000000
  229. #define RTL81_HARDWARE_VERSION_8139AG 0x70800000
  230. #define RTL81_HARDWARE_VERSION_8139B 0x78000000
  231. #define RTL81_HARDWARE_VERSION_8139C 0x74000000
  232. #define RTL81_HARDWARE_VERSION_8139CPLUS 0x74800000
  233. #define RTL81_HARDWARE_VERSION_8168E_VL 0x2C800000
  234. //
  235. // Define the receive configuration register bits.
  236. //
  237. #define RTL81_RECEIVE_CONFIGURATION_EARLY_TRESHOLD_MASK (0xF << 24)
  238. #define RTL81_RECEIVE_CONFIGURATION_EARLY_TRESHOLD_SHIFT 24
  239. #define RTL81_RECEIVE_CONFIGURATION_DEFAULT_EARLY_THRESHOLD 0xF
  240. #define RTL81_RECEIVE_CONFIGURATION_MULTIPLE_EARLY_INTERRUPT (1 << 17)
  241. #define RTL81_RECEIVE_CONFIGURATION_8_BYTE_ERROR_PACKETS (1 << 16)
  242. #define RTL81_RECEIVE_CONFIGURATION_FIFO_THRESHOLD_MASK (0x7 << 13)
  243. #define RTL81_RECEIVE_CONFIGURATION_FIFO_THRESHOLD_SHIFT 13
  244. #define RTL81_RECEIVE_CONFIGURATION_FIFO_THRESHOLD_16_BYTES 0x0
  245. #define RTL81_RECEIVE_CONFIGURATION_FIFO_THRESHOLD_32_BYTES 0x1
  246. #define RTL81_RECEIVE_CONFIGURATION_FIFO_THRESHOLD_64_BYTES 0x2
  247. #define RTL81_RECEIVE_CONFIGURATION_FIFO_THRESHOLD_128_BYTES 0x3
  248. #define RTL81_RECEIVE_CONFIGURATION_FIFO_THRESHOLD_256_BYTES 0x4
  249. #define RTL81_RECEIVE_CONFIGURATION_FIFO_THRESHOLD_512_BYTES 0x5
  250. #define RTL81_RECEIVE_CONFIGURATION_FIFO_THRESHOLD_1024_BYTES 0x6
  251. #define RTL81_RECEIVE_CONFIGURATION_FIFO_NO_THRESHOLD 0x7
  252. #define RTL81_RECEIVE_CONFIGURATION_BUFFER_LENGTH_MASK (0x3 << 11)
  253. #define RTL81_RECEIVE_CONFIGURATION_BUFFER_LENGTH_SHIFT 11
  254. #define RTL81_RECEIVE_CONFIGURATION_BUFFER_LENGTH_8K 0x0
  255. #define RTL81_RECEIVE_CONFIGURATION_BUFFER_LENGTH_16K 0x1
  256. #define RTL81_RECEIVE_CONFIGURATION_BUFFER_LENGTH_32K 0x2
  257. #define RTL81_RECEIVE_CONFIGURATION_BUFFER_LENGTH_64K 0x3
  258. #define RTL81_RECEIVE_CONFIGURATION_MAX_DMA_BURST_MASK (0x7 << 8)
  259. #define RTL81_RECEIVE_CONFIGURATION_MAX_DMA_BURST_SHIFT 8
  260. #define RTL81_RECEIVE_CONFIGURATION_MAX_DMA_BURST_32_BYTES 0x1
  261. #define RTL81_RECEIVE_CONFIGURATION_MAX_DMA_BURST_64_BYTES 0x2
  262. #define RTL81_RECEIVE_CONFIGURATION_MAX_DMA_BURST_128_BYTES 0x3
  263. #define RTL81_RECEIVE_CONFIGURATION_MAX_DMA_BURST_256_BYTES 0x4
  264. #define RTL81_RECEIVE_CONFIGURATION_MAX_DMA_BURST_512_BYTES 0x5
  265. #define RTL81_RECEIVE_CONFIGURATION_MAX_DMA_BURST_1024_BYTES 0x6
  266. #define RTL81_RECEIVE_CONFIGURATION_MAX_DMA_BURST_UNLIMITED 0x7
  267. #define RTL81_RECEIVE_CONFIGURATION_NO_WRAP (1 << 7)
  268. #define RTL81_RECEIVE_CONFIGURATION_EEPROM_9356 (1 << 6)
  269. #define RTL81_RECEIVE_CONFIGURATION_ACCEPT_ERROR_PACKETS (1 << 5)
  270. #define RTL81_RECEIVE_CONFIGURATION_ACCEPT_RUNT_PACKETS (1 << 4)
  271. #define RTL81_RECEIVE_CONFIGURATION_ACCEPT_BROADCAST_PACKETS (1 << 3)
  272. #define RTL81_RECEIVE_CONFIGURATION_ACCEPT_MULTICAST_PACKETS (1 << 2)
  273. #define RTL81_RECEIVE_CONFIGURATION_ACCEPT_PHYSICAL_MATCH_PACKETS (1 << 1)
  274. #define RTL81_RECEIVE_CONFIGURATION_ACCEPT_PHYSICAL_ADDRESS_PACKETS (0 << 1)
  275. #define RTL81_RECEIVE_CONFIGURATION_DEFAULT_OPTIONS \
  276. (RTL81_RECEIVE_CONFIGURATION_ACCEPT_PHYSICAL_MATCH_PACKETS | \
  277. RTL81_RECEIVE_CONFIGURATION_ACCEPT_BROADCAST_PACKETS | \
  278. (RTL81_RECEIVE_CONFIGURATION_MAX_DMA_BURST_UNLIMITED << \
  279. RTL81_RECEIVE_CONFIGURATION_MAX_DMA_BURST_SHIFT) | \
  280. (RTL81_RECEIVE_CONFIGURATION_BUFFER_LENGTH_64K << \
  281. RTL81_RECEIVE_CONFIGURATION_BUFFER_LENGTH_SHIFT) | \
  282. (RTL81_RECEIVE_CONFIGURATION_FIFO_NO_THRESHOLD << \
  283. RTL81_RECEIVE_CONFIGURATION_FIFO_THRESHOLD_SHIFT))
  284. //
  285. // Define the EEPROM command register bits.
  286. //
  287. #define RTL81_EEPROM_COMMAND_MODE_MASK (0x3 << 6)
  288. #define RTL81_EEPROM_COMMAND_MODE_SHIFT 6
  289. #define RTL81_EEPROM_COMMAND_MODE_NORMAL 0x0
  290. #define RTL81_EEPROM_COMMAND_MODE_AUTO_LOAD 0x1
  291. #define RTL81_EEPROM_COMMAND_MODE_93C46 0x2
  292. #define RTL81_EEPROM_COMMAND_MODE_CONFIGURATION_WRITE_ENABLED 0x3
  293. #define RTL81_EEPROM_COMMAND_EECS_PIN (1 << 3)
  294. #define RTL81_EEPROM_COMMAND_EESK_PIN (1 << 2)
  295. #define RTL81_EEPROM_COMMAND_EEDI_PIN (1 << 1)
  296. #define RTL81_EEPROM_COMMAND_EEDO_PIN (1 << 0)
  297. //
  298. // Define the media status register bits.
  299. //
  300. #define RTL81_MEDIA_STATUS_TRANSMIT_FLOW_CONTROL_ENABLED 0x80
  301. #define RTL81_MEDIA_STATUS_RECEIVE_FLOW_CONTROL_ENABLED 0x40
  302. #define RTL81_MEDIA_STATUS_AUX_POWER_PRESENT 0x10
  303. #define RTL81_MEDIA_STATUS_SPEED_10 0x08
  304. #define RTL81_MEDIA_STATUS_LINK_DOWN 0x04
  305. #define RTL81_MEDIA_STATUS_TRANSMIT_PAUSE 0x02
  306. #define RTL81_MEDIA_STATUS_RECEIVE_PAUSE 0x01
  307. //
  308. // Define the MII access register bits.
  309. //
  310. #define RTL81_MII_ACCESS_COMPLETE_MASK 0x80000000
  311. #define RTL81_MII_ACCESS_WRITE_COMPLETE 0x00000000
  312. #define RTL81_MII_ACCESS_READ_COMPLETE 0x80000000
  313. #define RTL81_MII_ACCESS_WRITE 0x80000000
  314. #define RTL81_MII_ACCESS_READ 0x00000000
  315. #define RTL81_MII_ACCESS_REGISTER_MASK 0x001F0000
  316. #define RTL81_MII_ACCESS_REGISTER_SHIFT 16
  317. #define RTL81_MII_ACCESS_DATA_MASK 0x0000FFFF
  318. #define RTL81_MII_ACCESS_DATA_SHIFT 0
  319. //
  320. // Define the basic mode control register bits.
  321. //
  322. #define RTL81_BASIC_MODE_CONTROL_RESET 0x8000
  323. #define RTL81_BASIC_MODE_CONTROL_SPEED_SET_100 0x2000
  324. #define RTL81_BASIC_MODE_CONTROL_AUTO_NEGOTIATION_ENABLE 0x1000
  325. #define RTL81_BASIC_MODE_CONTROL_RESTART_AUTO_NEGOTIATION 0x0200
  326. #define RTL81_BASIC_MODE_CONTROL_DUPLEX_MODE 0x0100
  327. #define RTL81_BASIC_MODE_CONTROL_INITIAL_VALUE \
  328. (RTL81_BASIC_MODE_CONTROL_RESET | \
  329. RTL81_BASIC_MODE_CONTROL_AUTO_NEGOTIATION_ENABLE | \
  330. RTL81_BASIC_MODE_CONTROL_RESTART_AUTO_NEGOTIATION)
  331. //
  332. // Define the basic mode status register bits.
  333. //
  334. #define RTL81_BASIC_MODE_STATUS_100_BASE_T4 0x8000
  335. #define RTL81_BASIC_MODE_STATUS_100_BASE_TX_FULL_DUPLEX 0x4000
  336. #define RTL81_BASIC_MODE_STATUS_100_BASE_TX_HALF_DUPLEX 0x2000
  337. #define RTL81_BASIC_MODE_STATUS_10_BASE_T_FULL_DUPLEX 0x1000
  338. #define RTL81_BASIC_MODE_STATUS_10_BASE_T_HALF_DUPLEX 0x0800
  339. #define RTL81_BASIC_MODE_STATUS_MEDIUM_MODE_1 0x0080
  340. #define RTL81_BASIC_MODE_STATUS_MEDIUM_MODE_0 0x0040
  341. #define RTL81_BASIC_MODE_STATUS_AUTO_NEGOTIATION_COMPLETE 0x0020
  342. #define RTL81_BASIC_MODE_STATUS_REMOTE_FAULT 0x0010
  343. #define RTL81_BASIC_MODE_STATUS_AUTO_NEGOTIATION 0x0008
  344. #define RTL81_BASIC_MODE_STATUS_LINK 0x0004
  345. #define RTL81_BASIC_MODE_STATUS_JABBER_DETECT 0x0002
  346. #define RTL81_BASIC_MODE_STATUS_EXTENDED_CAPABILITY 0x0001
  347. //
  348. // Define the PHY status register bits.
  349. //
  350. #define RTL81_PHY_STATUS_TBI_ENABLED 0x80
  351. #define RTL81_PHY_STATUS_TRANSMIT_FLOW_CONTROL 0x40
  352. #define RTL81_PHY_STATUS_RECEIVE_FLOW_CONTROL 0x20
  353. #define RTL81_PHY_STATUS_SPEED_1000 0x10
  354. #define RTL81_PHY_STATUS_SPEED_100 0x08
  355. #define RTL81_PHY_STATUS_SPEED_10 0x04
  356. #define RTL81_PHY_STATUS_LINK_UP 0x02
  357. #define RTL81_PHY_STATUS_FULL_DUPLEX 0x01
  358. //
  359. // Define the transmit priority polling register bits.
  360. //
  361. #define RTL81_TRANSMIT_PRIORITY_POLLING_HIGH 0x80
  362. #define RTL81_TRANSMIT_PRIORITY_POLLING_NORMAL 0x40
  363. #define RTL81_TRANSMIT_PRIORITY_POLLING_FORCE_SOFTWARE_INTERRUPT 0x01
  364. //
  365. // Define the 2nd command register's bits.
  366. //
  367. #define RTL81_COMMAND_2_REGISTER_RECEIVE_VLAN_DETAGGING 0x0040
  368. #define RTL81_COMMAND_2_REGISTER_RECEIVE_CHECKSUM_OFFLOAD 0x0020
  369. #define RTL81_COMMAND_2_REGISTER_DUAL_ADDRESS_CYCLE 0x0010
  370. #define RTL81_COMMAND_2_REGISTER_MULTIPLE_READ_WRITE 0x0008
  371. #define RTL81_COMMAND_2_REGISTER_RECEIVE_ENABLE 0x0002
  372. #define RTL81_COMMAND_2_REGISTER_TRANSMIT_ENABLE 0x0001
  373. #define RTL81_COMMAND_2_REGISTER_DEFAULT \
  374. (RTL81_COMMAND_2_REGISTER_TRANSMIT_ENABLE | \
  375. RTL81_COMMAND_2_REGISTER_RECEIVE_ENABLE | \
  376. RTL81_COMMAND_2_REGISTER_MULTIPLE_READ_WRITE)
  377. //
  378. // Define the default value to write to the early transmit threshold register.
  379. //
  380. #define RTL81_EARLY_TRANSMIT_THRESHOLD_DEFAULT 0x3F
  381. //
  382. // Define the receive packet header flags.
  383. //
  384. #define RTL81_RECEIVE_PACKET_STATUS_MULTICAST_ADDRESS 0x8000
  385. #define RTL81_RECEIVE_PACKET_STATUS_PHYSICAL_ADDRESS_MATCHED 0x4000
  386. #define RTL81_RECEIVE_PACKET_STATUS_BROADCAST_ADDRESS 0x2000
  387. #define RTL81_RECEIVE_PACKET_STATUS_INVALID_SYMBOL_ERROR 0x0020
  388. #define RTL81_RECEIVE_PACKET_STATUS_RUNT_PACKET 0x0010
  389. #define RTL81_RECEIVE_PACKET_STATUS_LONG_PACKET 0x0008
  390. #define RTL81_RECEIVE_PACKET_STATUS_CRC_ERROR 0x0004
  391. #define RTL81_RECEIVE_PACKET_STATUS_FRAME_ALIGNMENT_ERROR 0x0002
  392. #define RTL81_RECEIVE_PACKET_STATUS_OK 0x0001
  393. //
  394. // Define the mask of receive packet errors.
  395. //
  396. #define RTL81_RECEIVE_PACKET_ERROR_MASK \
  397. (RTL81_RECEIVE_PACKET_STATUS_FRAME_ALIGNMENT_ERROR | \
  398. RTL81_RECEIVE_PACKET_STATUS_CRC_ERROR | \
  399. RTL81_RECEIVE_PACKET_STATUS_LONG_PACKET | \
  400. RTL81_RECEIVE_PACKET_STATUS_RUNT_PACKET | \
  401. RTL81_RECEIVE_PACKET_STATUS_INVALID_SYMBOL_ERROR)
  402. //
  403. // Define the transmit descriptor command bits.
  404. //
  405. #define RTL81_TRANSMIT_DESCRIPTOR_COMMAND_OWN (1 << 31)
  406. #define RTL81_TRANSMIT_DESCRIPTOR_COMMAND_END_OF_RING (1 << 30)
  407. #define RTL81_TRANSMIT_DESCRIPTOR_COMMAND_FIRST_SEGMENT (1 << 29)
  408. #define RTL81_TRANSMIT_DESCRIPTOR_COMMAND_LAST_SEGMENT (1 << 28)
  409. #define RTL81_TRANSMIT_DESCRIPTOR_COMMAND_LARGE_SEND (1 << 27)
  410. #define RTL81_TRANSMIT_DESCRIPTOR_COMMAND_LARGE_SEND_SIZE_MASK (0x7FF << 16)
  411. #define RTL81_TRANSMIT_DESCRIPTOR_COMMAND_LARGE_SEND_SIZE_SHIFT 16
  412. #define RTL81_TRANSMIT_DESCRIPTOR_COMMAND_FIFO_UNDERRUN (1 << 25)
  413. #define RTL81_TRANSMIT_DESCRIPTOR_COMMAND_ERROR_SUMMARY (1 << 23)
  414. #define RTL81_TRANSMIT_DESCRIPTOR_COMMAND_OUT_OF_WINDOW_COLLISION (1 << 22)
  415. #define RTL81_TRANSMIT_DESCRIPTOR_COMMAND_LINK_FAILURE (1 << 21)
  416. #define RTL81_TRANSMIT_DESCRIPTOR_COMMAND_EXCESSIVE_COLLISIONS (1 << 20)
  417. #define RLT81_TRANSMIT_DESCRIPTOR_COMMAND_COLLISION_COUNT_MASK (0xF << 16)
  418. #define RLT81_TRANSMIT_DESCRIPTOR_COMMAND_COLLISION_COUNT_SHIFT 16
  419. #define RTL81_TRANSMIT_DESCRIPTOR_COMMAND_IP_CHECKSUM_OFFLOAD (1 << 18)
  420. #define RTL81_TRANSMIT_DESCRIPTOR_COMMAND_UDP_CHECKSUM_OFFLOAD (1 << 17)
  421. #define RTL81_TRANSMIT_DESCRIPTOR_COMMAND_TCP_CHECKSUM_OFFLOAD (1 << 16)
  422. #define RTL81_TRANSMIT_DESCRIPTOR_COMMAND_SIZE_MASK (0xFFFF << 0)
  423. #define RTL81_TRANSMIT_DESCRIPTOR_COMMAND_SIZE_SHIFT 0
  424. //
  425. // Define the transmit descriptor VLAN bits.
  426. //
  427. #define RTL81_TRANSMIT_DESCRIPTOR_VLAN_UDP_CHECKSUM_OFFLOAD (1 << 31)
  428. #define RTL81_TRANSMIT_DESCRIPTOR_VLAN_TCP_CHECKSUM_OFFLOAD (1 << 30)
  429. #define RTL81_TRANSMIT_DESCRIPTOR_VLAN_IP_CHECKSUM_OFFLOAD (1 << 29)
  430. //
  431. // Define the receive descriptor command bits.
  432. //
  433. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_OWN (1 << 31)
  434. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_END_OF_RING (1 << 30)
  435. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_FIRST_SEGMENT (1 << 29)
  436. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_LAST_SEGMENT (1 << 28)
  437. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_FRAME_ALIGNMENT_ERROR (1 << 27)
  438. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_MULTICAST (1 << 26)
  439. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_PHYSICAL_MATCH (1 << 25)
  440. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_BROADCAST (1 << 24)
  441. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_BUFFER_OVERFLOW (1 << 23)
  442. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_FIFO_OVERFLOW (1 << 22)
  443. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_WATCHDOG_TIMER_EXPIRED (1 << 21)
  444. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_ERROR_SUMMARY (1 << 20)
  445. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_RUNT (1 << 19)
  446. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_CRC_ERROR (1 << 18)
  447. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_PROTOCOL_MASK (0x3 << 16)
  448. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_PROTOCOL_SHIFT 16
  449. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_PROTOCOL_NON_IP 0x0
  450. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_PROTOCOL_TCP_IP 0x1
  451. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_PROTOCOL_UDP_IP 0x2
  452. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_PROTOCOL_IP 0x3
  453. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_IP_CHECKSUM_FAILURE (1 << 15)
  454. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_UDP_CHECKSUM_FAILURE (1 << 14)
  455. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_TCP_CHECKSUM_FAILURE (1 << 13)
  456. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_LARGE_SIZE_MASK (0x1FFF << 0)
  457. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_LARGE_SIZE_SHIFT 0
  458. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_SIZE_MASK (0xFFF << 0)
  459. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_SIZE_SHIFT 0
  460. //
  461. // Define the default state of a receive descriptor.
  462. //
  463. #define RTL81_RECEIVE_DESCRIPTOR_DEFAULT_COMMAND \
  464. (RTL81_RECEIVE_DESCRIPTOR_COMMAND_OWN | \
  465. ((RTL81_RECEIVE_BUFFER_DATA_SIZE << \
  466. RTL81_RECEIVE_DESCRIPTOR_COMMAND_SIZE_SHIFT) & \
  467. RTL81_RECEIVE_DESCRIPTOR_COMMAND_SIZE_MASK))
  468. //
  469. // Define the receive descriptor VLAN bits.
  470. //
  471. #define RTL81_RECEIVE_DESCRIPTOR_VLAN_IP4 (1 << 30)
  472. //
  473. // Define the mask and shift of the RTL8168 and above values that needs to be
  474. // shifted by 1 to match those of the RTL8139C+.
  475. //
  476. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_MASK 0x0FFFE000
  477. #define RTL81_RECEIVE_DESCRIPTOR_COMMAND_SHIFT 1
  478. //
  479. // Define MII Basic Control register bits.
  480. //
  481. #define RTL81_MII_BASIC_CONTROL_SPEED_1000 0x0040
  482. #define RTL81_MII_BASIC_CONTROL_COLLISION_TEST 0x0080
  483. #define RTL81_MII_BASIC_CONTROL_FULL_DUPLEX 0x0100
  484. #define RTL81_MII_BASIC_CONTROL_RESTART_AUTONEGOTIATION 0x0200
  485. #define RTL81_MII_BASIC_CONTROL_ISOLATE 0x0400
  486. #define RTL81_MII_BASIC_CONTROL_POWER_DOWN 0x0800
  487. #define RTL81_MII_BASIC_CONTROL_ENABLE_AUTONEGOTIATION 0x1000
  488. #define RTL81_MII_BASIC_CONTROL_SPEED_100 0x2000
  489. #define RTL81_MII_BASIC_CONTROL_LOOPBACK 0x4000
  490. #define RTL81_MII_BASIC_CONTROL_RESET 0x8000
  491. //
  492. // Define MII Basic Status register bits.
  493. //
  494. #define RTL81_MII_BASIC_STATUS_EXTENDED_CAPABILITY 0x0001
  495. #define RTL81_MII_BASIC_STATUS_JABBER_DETECTED 0x0002
  496. #define RTL81_MII_BASIC_STATUS_LINK_STATUS 0x0004
  497. #define RTL81_MII_BASIC_STATUS_AUTONEGOTIATE_CAPABLE 0x0008
  498. #define RTL81_MII_BASIC_STATUS_REMOTE_FAULT 0x0010
  499. #define RTL81_MII_BASIC_STATUS_AUTONEGOTIATE_COMPLETE 0x0020
  500. #define RTL81_MII_BASIC_STATUS_EXTENDED_STATUS 0x0100
  501. #define RTL81_MII_BASIC_STATUS_100_HALF2 0x0200
  502. #define RTL81_MII_BASIC_STATUS_100_FULL2 0x0400
  503. #define RTL81_MII_BASIC_STATUS_10_HALF 0x0800
  504. #define RTL81_MII_BASIC_STATUS_10_FULL 0x1000
  505. #define RTL81_MII_BASIC_STATUS_100_HALF 0x2000
  506. #define RTL81_MII_BASIC_STATUS_100_FULL 0x4000
  507. #define RTL81_MII_BASIC_STATUS_100_BASE4 0x8000
  508. //
  509. // Define MII Advertise register bits.
  510. //
  511. #define RTL81_MII_ADVERTISE_SELECT_MASK 0x001F
  512. #define RTL81_MII_ADVERTISE_CSMA 0x0001
  513. #define RTL81_MII_ADVERTISE_10_HALF 0x0020
  514. #define RTL81_MII_ADVERTISE_1000X_FULL 0x0020
  515. #define RTL81_MII_ADVERTISE_10_FULL 0x0040
  516. #define RTL81_MII_ADVERTISE_1000X_HALF 0x0040
  517. #define RTL81_MII_ADVERTISE_100_HALF 0x0080
  518. #define RTL81_MII_ADVERTISE_1000X_PAUSE 0x0080
  519. #define RTL81_MII_ADVERTISE_100_FULL 0x0100
  520. #define RTL81_MII_ADVERTISE_1000X_PAUSE_ASYMMETRIC 0x0100
  521. #define RTL81_MII_ADVERTISE_100_BASE4 0x0200
  522. #define RTL81_MII_ADVERTISE_PAUSE 0x0400
  523. #define RTL81_MII_ADVERTISE_PAUSE_ASYMMETRIC 0x0800
  524. #define RTL81_MII_ADVERTISE_REMOTE_FAULT 0x2000
  525. #define RTL81_MII_ADVERTISE_LINK_PARTNER 0x4000
  526. #define RTL81_MII_ADVERTISE_NEXT_PAGE 0x8000
  527. #define RTL81_MII_ADVERTISE_FULL \
  528. (RTL81_MII_ADVERTISE_100_FULL | \
  529. RTL81_MII_ADVERTISE_10_FULL | \
  530. RTL81_MII_ADVERTISE_CSMA)
  531. #define RTL81_MII_ADVERTISE_ALL \
  532. (RTL81_MII_ADVERTISE_10_HALF | \
  533. RTL81_MII_ADVERTISE_10_FULL | \
  534. RTL81_MII_ADVERTISE_100_HALF | \
  535. RTL81_MII_ADVERTISE_100_FULL | \
  536. RTL81_MII_ADVERTISE_CSMA)
  537. //
  538. // Define MII Gigabit control register bits.
  539. //
  540. #define RTL81_MII_GIGABIT_CONTROL_MANUAL_MASTER 0x1000
  541. #define RTL81_MII_GIGABIT_CONTROL_ADVANCED_MASTER 0x0800
  542. #define RTL81_MII_GIGABIT_CONTROL_ADVERTISE_1000_FULL 0x0200
  543. #define RTL81_MII_GIGABIT_CONTROL_ADVERTISE_1000_HALF 0x0100
  544. //
  545. // Define the flags used to describe an RTL81xx device.
  546. //
  547. #define RTL81_FLAG_TRANSMIT_MODE_LEGACY 0x00000001
  548. #define RTL81_FLAG_REGISTER_SET_LEGACY 0x00000002
  549. #define RTL81_FLAG_DESCRIPTOR_LIMIT_64 0x00000004
  550. #define RTL81_FLAG_MULTI_SEGMENT_SUPPORT 0x00000008
  551. #define RTL81_FLAG_RECEIVE_COMMAND_LEGACY 0x00000010
  552. #define RTL81_FLAG_CHECKSUM_OFFLOAD_DEFAULT 0x00000020
  553. #define RTL81_FLAG_CHECKSUM_OFFLOAD_VLAN 0x00000040
  554. //
  555. // Define the mask of different checksum offload types supported.
  556. //
  557. #define RTL81_FLAG_CHECKSUM_OFFLOAD_MASK \
  558. (RTL81_FLAG_CHECKSUM_OFFLOAD_DEFAULT | \
  559. RTL81_FLAG_CHECKSUM_OFFLOAD_VLAN)
  560. //
  561. // ------------------------------------------------------ Data Type Definitions
  562. //
  563. typedef enum _RTL81_REGISTER {
  564. Rtl81RegisterId0 = 0x0,
  565. Rtl81RegisterId1 = 0x1,
  566. Rtl81RegisterId2 = 0x2,
  567. Rtl81RegisterId3 = 0x3,
  568. Rtl81RegisterId4 = 0x4,
  569. Rtl81RegisterId5 = 0x5,
  570. Rtl81RegisterMulticast0 = 0x8,
  571. Rtl81RegisterMulticast1 = 0x9,
  572. Rtl81RegisterMulticast2 = 0xA,
  573. Rtl81RegisterMulticast3 = 0xB,
  574. Rtl81RegisterMulticast4 = 0xC,
  575. Rtl81RegisterMulticast5 = 0xD,
  576. Rtl81RegisterMulticast6 = 0xE,
  577. Rtl81RegisterMulticast7 = 0xF,
  578. RTL81RegisterDumpTallyCommand = 0x10,
  579. Rtl81RegisterTransmitStatus0 = 0x10,
  580. Rtl81RegisterTransmitStatus1 = 0x14,
  581. Rtl81RegisterTransmitStatus2 = 0x18,
  582. Rtl81RegisterTransmitStatus3 = 0x1C,
  583. Rtl81RegisterTransmitDescriptorBaseLow = 0x20,
  584. Rtl81RegisterTransmitAddress0 = 0x20,
  585. Rtl81RegisterTransmitDescriptorBaseHigh = 0x24,
  586. Rtl81RegisterTransmitAddress1 = 0x24,
  587. Rtl81RegisterUrgentTransmitDescriptorBaseLow = 0x28,
  588. Rtl81RegisterTransmitAddress2 = 0x28,
  589. Rtl81RegisterUrgentTransmitDescriptorBaseHigh = 0x2C,
  590. Rtl81RegisterTransmitAddress3 = 0x2C,
  591. Rtl81RegisterReceiveBufferStart = 0x30,
  592. Rtl81RegisterEarlyReceiveStatus = 0x36,
  593. Rtl81RegisterCommand = 0x37,
  594. Rtl81RegisterReadPacketAddress = 0x38,
  595. Rtl81RegisterTransmitPriorityPolling1 = 0x38,
  596. Rtl81RegisterReceiveBufferCurrent = 0x3A,
  597. Rtl81RegisterInterruptMask = 0x3C,
  598. Rtl81RegisterInterruptStatus = 0x3E,
  599. Rtl81RegisterTransmitConfiguration = 0x40,
  600. Rtl81RegisterReceiveConfiguration = 0x44,
  601. Rtl81RegisterTimeCount = 0x48,
  602. Rtl81RegisterMissedPacketCounter = 0x4C,
  603. Rtl81RegisterEepromCommand = 0x50,
  604. Rtl81RegisterLegacyConfiguration0 = 0x51,
  605. Rtl81RegisterConfiguration0 = 0x51,
  606. Rtl81RegisterLegacyConfiguration1 = 0x52,
  607. Rtl81RegisterConfiguration1 = 0x52,
  608. Rtl81RegisterConfiguration2 = 0x53,
  609. Rtl81RegisterConfiguration3 = 0x54,
  610. Rtl81RegisterTimerInterrupt = 0x54,
  611. Rtl81RegisterConfiguration4 = 0x55,
  612. Rtl81RegisterConfiguration5 = 0x56,
  613. Rtl81RegisterMediaStatus = 0x58,
  614. Rtl81RegisterLegacyConfiguration3 = 0x59,
  615. Rtl81RegisterLegacyConfiguration4 = 0x5A,
  616. Rtl81RegisterMultipleInterruptSelect = 0x5C,
  617. Rtl81RegisterPciRevision = 0x5E,
  618. Rtl81RegisterTransmitStatusAll = 0x60,
  619. Rtl81RegisterMiiAccess = 0x60,
  620. Rtl81RegisterBasicModeControl = 0x62,
  621. Rtl81RegisterBasicModeStatus = 0x64,
  622. Rtl81RegisterAutoNegotiationAdvertisement = 0x66,
  623. Rtl81RegisterAutoNegotiationLinkPartner = 0x68,
  624. Rtl81RegisterAutoNegotiationExpansion = 0x6A,
  625. Rtl81RegisterDisconnectCounter = 0x6C,
  626. Rtl81RegisterPhyStatus = 0x6C,
  627. Rtl81RegisterFalseCarrierSenseCounter = 0x6E,
  628. Rtl81RegisterNwayTest = 0x70,
  629. Rtl81RegisterReceiveErrorCounter = 0x72,
  630. Rtl81RegisterCsConfiguration = 0x74,
  631. Rtl81RegisterPhyParameter1 = 0x78,
  632. Rtl81RegisterTwisterParameter = 0x7C,
  633. Rtl81RegisterPhyParameter2 = 0x80,
  634. Rtl81RegisterLegacyConfiguration5 = 0xD8,
  635. Rtl81RegisterTransmitPriorityPolling2 = 0xD9,
  636. Rtl81RegisterReceiveMaxPacketSize = 0xDA,
  637. Rtl81RegisterCommand2 = 0xE0,
  638. Rtl81RegisterReceiveDescriptorBaseLow = 0xE4,
  639. Rtl81RegisterReceiveDescriptorBaseHigh = 0xE8,
  640. Rtl81RegisterEarlyTransmitThreshold = 0xEC
  641. } RTL81_REGISTER, *PRTL81_REGISTER;
  642. //
  643. // TODO: Refactor the generic MII registers and bit definitions to use mii.h.
  644. //
  645. typedef enum _RTL81_MII_REGISTER {
  646. Rtl81MiiRegisterBasicControl = 0x00, // BMCR
  647. Rtl81MiiRegisterBasicStatus = 0x01, // BMSR
  648. Rtl81MiiRegisterPhysicalId1 = 0x02, // PHYSID1
  649. Rtl81MiiRegisterPhysicalId2 = 0x03, // PHYSID2
  650. Rtl81MiiRegisterAdvertise = 0x04, // ADVERTISE
  651. Rtl81MiiRegisterLinkPartnerAbility = 0x05, // LPA
  652. Rtl81MiiRegisterExpansion = 0x06, // EXPANSION
  653. Rtl81MiiRegisterGigabitControl = 0x09, // CTRL1000
  654. Rtl81MiiRegisterGigabitStatus = 0x0A, // STAT1000
  655. Rtl81MiiRegisterExtendedStatus = 0x0F, // ESTATUS
  656. Rtl81MiiRegisterDisconnectCounter = 0x12, // DCOUNTER
  657. Rtl81MiiRegisterFalseCarrierCounter = 0x13, // FCSCOUNTER
  658. Rtl81MiiRegisterNWayTest = 0x14, // NWAYTEST
  659. Rtl81MiiRegisterReceiveErrorCounter = 0x15, // RERRCOUNTER
  660. Rtl81MiiRegisterSiliconRevision = 0x16, // SREVISION
  661. Rtl81MiiRegisterLoopbackReceiveBypassError = 0x18, // LBRERROR
  662. Rtl81MiiRegisterPhyAddress = 0x19, // PHYADDR
  663. Rtl81MiiRegisterTpiStatus = 0x1B, // TPISTATUS
  664. Rtl81MiiRegisterNetworkConfiguration = 0x1C, // NCONFIG
  665. Rtl81MiiRegisterMax = 0x1F
  666. } RTL81_MII_REGISTER, *PRTL81_MII_REGISTER;
  667. /*++
  668. Structure Description:
  669. This structure defines an RTL81xx received packet header.
  670. Members:
  671. Status - Stores the received packet status.
  672. Length - Stores the length of the received packet.
  673. --*/
  674. typedef struct _RTL81_PACKET_HEADER {
  675. USHORT Status;
  676. USHORT Length;
  677. } RTL81_PACKET_HEADER, *PRTL81_PACKET_HEADER;
  678. /*++
  679. Structure Description:
  680. This structure defines a transmit descriptor for newer RTL81xx chips,
  681. including RTL8139C+, RTL8168, and RTL8169.
  682. Members:
  683. Command - Stores the command flags that indicate the descriptor's status.
  684. VlanTag - Stores the VLAN tag associated with the packet.
  685. PhysicalAddress - Stores the physical address of the buffer to send out the
  686. wire.
  687. --*/
  688. typedef struct _RTL81_TRANSMIT_DESCRIPTOR {
  689. ULONG Command;
  690. ULONG VlanTag;
  691. ULONGLONG PhysicalAddress;
  692. } PACKED RTL81_TRANSMIT_DESCRIPTOR, *PRTL81_TRANSMIT_DESCRIPTOR;
  693. /*++
  694. Structure Description:
  695. This structure defines a receive descriptor for newer RTL81xx chips,
  696. including RTL8139C+, RTL8168, and RTL8169.
  697. Members:
  698. Command - Stores the command flags that indicate the descriptor's status.
  699. VlanTag - Stores the VLAN tag associated with the packet.
  700. PhysicalAddress - Stores the physical address of the buffer to send out the
  701. wire.
  702. --*/
  703. typedef struct _RTL81_RECEIVE_DESCRIPTOR {
  704. ULONG Command;
  705. ULONG VlanTag;
  706. ULONGLONG PhysicalAddress;
  707. } PACKED RTL81_RECEIVE_DESCRIPTOR, *PRTL81_RECEIVE_DESCRIPTOR;
  708. /*++
  709. Structure Description:
  710. This structure defines the extra data required to transmit and receive on
  711. an RTL8139 device.
  712. Members:
  713. ReceiveIoBuffer - Stores a pointer to the I/O buffer used to store received
  714. data.
  715. ActiveTransmitPackets - Stores the array of transmit packets that are
  716. active in the RTL81xx controller.
  717. TransmitNextToUse - Stores the index of the next transmit descriptor to use
  718. when sending a new packet.
  719. TransmitNextToClean - Stores the index of the oldest in-flight packet, the
  720. first one to check to see if transmission is done.
  721. --*/
  722. typedef struct _RTL81_LEGACY_DATA {
  723. PIO_BUFFER ReceiveIoBuffer;
  724. PNET_PACKET_BUFFER
  725. ActiveTransmitPackets[RTL81_TRANSMIT_DESCRIPTOR_COUNT_LEGACY];
  726. BYTE TransmitNextToUse;
  727. BYTE TransmitNextToClean;
  728. } RTL81_LEGACY_DATA, *PRTL81_LEGACY_DATA;
  729. /*++
  730. Structure Description:
  731. This structure defines the extra data required to transmit and receive on
  732. an RTL8139C+, RTL8168, and RTL8169 device.
  733. Members:
  734. DescriptorIoBuffer - Supplies a pointer to the I/O buffer taht holds the
  735. transmit descriptor array, received descriptor array, array of transmit
  736. buffer virtual addresses, and the array of received packet memory.
  737. TransmitDescriptor - Stores the array of transmit descriptor heads. Must be
  738. 256-byte aligned.
  739. TransmitBuffer - Stores an array of points to the virtual addresses of the
  740. transmitted network packets. This is used when freeing packets that
  741. have successfully been sent.
  742. ReceiveDescriptor - Stores the array of receive descriptor heads. Must be
  743. 256-byte aligned.
  744. ReceivePacketData - Stores the virtual address of the first receive
  745. descriptor's packet data.
  746. TransmitNextToUse - Stores the index of the next transmit descriptor to use
  747. when sending a new packet.
  748. TransmitNextToClean - Stores the index of the oldest in-flight packet, the
  749. first one to check to see if transmission is done.
  750. TransmitDescriptorCount - Stores the number of transmit descriptors.
  751. ReceiveNextToReap - Stores the index of the next receive descriptor to
  752. check for data.
  753. ReceiveDescriptorCount - Stores the number of receive descriptors.
  754. --*/
  755. typedef struct _RTL81_DEFAULT_DATA {
  756. PIO_BUFFER DescriptorIoBuffer;
  757. PRTL81_TRANSMIT_DESCRIPTOR TransmitDescriptor;
  758. PNET_PACKET_BUFFER *TransmitBuffer;
  759. PRTL81_RECEIVE_DESCRIPTOR ReceiveDescriptor;
  760. PVOID ReceivePacketData;
  761. USHORT TransmitNextToUse;
  762. USHORT TransmitNextToClean;
  763. USHORT TransmitDescriptorCount;
  764. USHORT ReceiveNextToReap;
  765. USHORT ReceiveDescriptorCount;
  766. } RTL81_DEFAULT_DATA, *PRTL81_DEFAULT_DATA;
  767. /*++
  768. Structure Description:
  769. This structure defines an RTL81xx LAN device.
  770. Members:
  771. Flags - Stores a bitmask of flags indicating the type of device described
  772. by this structure. See RTL81_FLAG_* for definitions.
  773. OsDevice - Stores a pointer to the OS device object.
  774. ControllerBase - Stores the virtual address of the memory mapping to the
  775. RTL81xx's registers.
  776. NetworkLink - Stores a pointer to the core networking link.
  777. InterruptLine - Stores the interrupt line that this controller's interrupt
  778. comes in on.
  779. InterruptVector - Stores the interrupt vector that this controller's
  780. interrupt comes in on.
  781. InterruptResourcesFound - Stores a boolean indicating whether or not the
  782. interrupt line and interrupt vector fields are valid.
  783. InterruptHandle - Stores a pointer to the handle received when the
  784. interrupt was connected.
  785. TransmitLock - Stores a queued lock that protects access to the transmit
  786. packet list and various other values.
  787. ReceiveLock - Stores a queued lock that protects access to the receive
  788. descriptors.
  789. TransmitInterruptMask - Stores a mask of interrupt status bits that trigger
  790. the processing of the transmit descriptors.
  791. ReceiveInterruptMask - Stores a mask of interrupt status bits that trigger
  792. the processing of received frames.
  793. PendingInterrupts - Stores the bitmask of pending interrupts. See
  794. RTL81_INTERRUPT_* for definitions.
  795. MacAddress - Stores the default MAC address of the device.
  796. TransmitPacketList - Stores the list of network packets waiting to be sent.
  797. MaxTransmitPacketListCount - Stores the maximum number of packets to remain
  798. on the list of packets waiting to be sent.
  799. ChecksumFlags - Stores a bitmask of checksum feature flags. See
  800. NET_LINK_CHECKSUM_FLAG_* for definitions. Updates to this flag are
  801. protected by the receive lock. There is nothing for the RTL81xx devices
  802. to do when the transmit bits change.
  803. LegacyData - Stores the extra data required to transmit and receive packets
  804. on a legacy device.
  805. DefaultData - Stores the extra data required to transmit and receive
  806. packets on the newer RTL8139C+, RTL8168, and RTL8169 devices.
  807. --*/
  808. typedef struct _RTL81_DEVICE {
  809. ULONG Flags;
  810. PDEVICE OsDevice;
  811. PVOID ControllerBase;
  812. PNET_LINK NetworkLink;
  813. ULONGLONG InterruptLine;
  814. ULONGLONG InterruptVector;
  815. BOOL InterruptResourcesFound;
  816. HANDLE InterruptHandle;
  817. PQUEUED_LOCK TransmitLock;
  818. PQUEUED_LOCK ReceiveLock;
  819. USHORT TransmitInterruptMask;
  820. USHORT ReceiveInterruptMask;
  821. ULONG PciMsiFlags;
  822. INTERFACE_PCI_MSI PciMsiInterface;
  823. volatile ULONG PendingInterrupts;
  824. BYTE MacAddress[ETHERNET_ADDRESS_SIZE];
  825. NET_PACKET_LIST TransmitPacketList;
  826. ULONG MaxTransmitPacketListCount;
  827. ULONG ChecksumFlags;
  828. union {
  829. RTL81_LEGACY_DATA LegacyData;
  830. RTL81_DEFAULT_DATA DefaultData;
  831. } U;
  832. } RTL81_DEVICE, *PRTL81_DEVICE;
  833. //
  834. // -------------------------------------------------------------------- Globals
  835. //
  836. //
  837. // -------------------------------------------------------- Function Prototypes
  838. //
  839. KSTATUS
  840. Rtl81Send (
  841. PVOID DeviceContext,
  842. PNET_PACKET_LIST PacketList
  843. );
  844. /*++
  845. Routine Description:
  846. This routine sends data through the network.
  847. Arguments:
  848. DeviceContext - Supplies a pointer to the device context associated with
  849. the link down which this data is to be sent.
  850. PacketList - Supplies a pointer to a list of network packets to send. Data
  851. in these packets may be modified by this routine, but must not be used
  852. once this routine returns.
  853. Return Value:
  854. STATUS_SUCCESS if all packets were sent.
  855. STATUS_RESOURCE_IN_USE if some or all of the packets were dropped due to
  856. the hardware being backed up with too many packets to send.
  857. Other failure codes indicate that none of the packets were sent.
  858. --*/
  859. KSTATUS
  860. Rtl81GetSetInformation (
  861. PVOID DeviceContext,
  862. NET_LINK_INFORMATION_TYPE InformationType,
  863. PVOID Data,
  864. PUINTN DataSize,
  865. BOOL Set
  866. );
  867. /*++
  868. Routine Description:
  869. This routine gets or sets the network device layer's link information.
  870. Arguments:
  871. DeviceContext - Supplies a pointer to the device context associated with
  872. the link for which information is being set or queried.
  873. InformationType - Supplies the type of information being queried or set.
  874. Data - Supplies a pointer to the data buffer where the data is either
  875. returned for a get operation or given for a set operation.
  876. DataSize - Supplies a pointer that on input contains the size of the data
  877. buffer. On output, contains the required size of the data buffer.
  878. Set - Supplies a boolean indicating if this is a get operation (FALSE) or a
  879. set operation (TRUE).
  880. Return Value:
  881. Status code.
  882. --*/
  883. KSTATUS
  884. Rtl81pInitializeDeviceStructures (
  885. PRTL81_DEVICE Device
  886. );
  887. /*++
  888. Routine Description:
  889. This routine performs housekeeping preparation for resetting and enabling
  890. an RTL81xx device.
  891. Arguments:
  892. Device - Supplies a pointer to the device.
  893. Return Value:
  894. Status code.
  895. --*/
  896. VOID
  897. Rtl81pDestroyDeviceStructures (
  898. PRTL81_DEVICE Device
  899. );
  900. /*++
  901. Routine Description:
  902. This routine performs destroy any device structures allocated for the
  903. RTL81xx device.
  904. Arguments:
  905. Device - Supplies a pointer to the device.
  906. Return Value:
  907. None.
  908. --*/
  909. KSTATUS
  910. Rtl81pInitialize (
  911. PRTL81_DEVICE Device
  912. );
  913. /*++
  914. Routine Description:
  915. This routine initializes and enables the RTL81xx device.
  916. Arguments:
  917. Device - Supplies a pointer to the device.
  918. Return Value:
  919. Status code.
  920. --*/
  921. INTERRUPT_STATUS
  922. Rtl81pInterruptService (
  923. PVOID Context
  924. );
  925. /*++
  926. Routine Description:
  927. This routine implements the RTL81xx interrupt service routine.
  928. Arguments:
  929. Context - Supplies the context pointer given to the system when the
  930. interrupt was connected. In this case, this points to the e100 device
  931. structure.
  932. Return Value:
  933. Interrupt status.
  934. --*/
  935. INTERRUPT_STATUS
  936. Rtl81pInterruptServiceWorker (
  937. PVOID Parameter
  938. );
  939. /*++
  940. Routine Description:
  941. This routine processes interrupts for the RTL81xx controller at low level.
  942. Arguments:
  943. Parameter - Supplies an optional parameter passed in by the creator of the
  944. work item.
  945. Return Value:
  946. Interrupt status.
  947. --*/
  948. //
  949. // Administrative functions called by the hardware side.
  950. //
  951. KSTATUS
  952. Rtl81pAddNetworkDevice (
  953. PRTL81_DEVICE Device
  954. );
  955. /*++
  956. Routine Description:
  957. This routine adds the device to core networking's available links.
  958. Arguments:
  959. Device - Supplies a pointer to the device to add.
  960. Return Value:
  961. Status code.
  962. --*/