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smsc95.h 13 KB

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  1. /*++
  2. Copyright (c) 2013 Minoca Corp. All Rights Reserved
  3. Module Name:
  4. smsc95.h
  5. Abstract:
  6. This header contains definitions for the SMSC95xx family of USB Ethernet
  7. Controllers.
  8. Author:
  9. Evan Green 7-Nov-2013
  10. --*/
  11. //
  12. // ------------------------------------------------------------------- Includes
  13. //
  14. #include <minoca/net/mii.h>
  15. //
  16. // ---------------------------------------------------------------- Definitions
  17. //
  18. #define SM95_ALLOCATION_TAG 0x35396D53 // '59mS'
  19. //
  20. // Define the maximum size of the control transfer data.
  21. //
  22. #define SM95_MAX_CONTROL_TRANSFER_SIZE (sizeof(USB_SETUP_PACKET) + 8)
  23. //
  24. // Define the maximum size of interrupt transfer data. Align up to cache size.
  25. //
  26. #define SM95_MAX_INTERRUPT_TRANSFER_SIZE 32
  27. //
  28. // Define the number of bytes needed at the front of every transmit packet.
  29. //
  30. #define SM95_TRANSMIT_HEADER_SIZE 8
  31. //
  32. // Define how long to wait for the PHY to finish before timing out, in seconds.
  33. //
  34. #define SM95_DEVICE_TIMEOUT 1
  35. //
  36. // Define how long to wait for the EEPROM to finish before timing out, in
  37. // seconds.
  38. //
  39. #define SM95_EEPROM_TIMEOUT 1
  40. //
  41. // Define the fixed device ID of the PHY on the internal bus of the SMSC95xx.
  42. //
  43. #define SM95_PHY_ID 1
  44. //
  45. // Define the offset in the EEPROM where the MAC address is stored.
  46. //
  47. #define SM95_EEPROM_MAC_ADDRESS 0x01
  48. //
  49. // Define the status bits coming from the interrupt endpoint.
  50. //
  51. #define SM95_INTERRUPT_STATUS_PHY 0x00008000
  52. #define SM95_INTERRUPT_MASK 0xFFFFFFFF
  53. //
  54. // Define the maximum size of single packet, including any headers and footers.
  55. //
  56. #define SM95_MAX_PACKET_SIZE 2048
  57. //
  58. // Define the maximum burst size for high speed and full speed devices.
  59. //
  60. #define SM95_HIGH_SPEED_TRANSFER_SIZE 512
  61. #define SM95_FULL_SPEED_TRANSFER_SIZE 64
  62. #define SM95_HIGH_SPEED_BURST_SIZE \
  63. ((16 * 1024) + (5 * SM95_HIGH_SPEED_TRANSFER_SIZE))
  64. #define SM95_FULL_SPEED_BURST_SIZE \
  65. ((6 * 1024) + (33 * SM95_FULL_SPEED_TRANSFER_SIZE))
  66. #define SM95_DEFAULT_BULK_IN_DELAY 0x00002000
  67. //
  68. // Define vendor-specific requests on the control endpoint.
  69. //
  70. #define SM95_VENDOR_REQUEST_WRITE_REGISTER 0xA0
  71. #define SM95_VENDOR_REQUEST_READ_REGISTER 0xA1
  72. //
  73. // Define transmit control register bits.
  74. //
  75. #define SM95_TRANSMIT_CONTROL_ENABLE 0x00000004
  76. //
  77. // Define Hardware Configuration register bits.
  78. //
  79. #define SM95_HARDWARE_CONFIG_LITE_RESET 0x00000008
  80. #define SM95_HARDWARE_CONFIG_BURST_CAP_ENABLED 0x00000002
  81. #define SM95_HARDWARE_CONFIG_MULTIPLE_ETHERNET_FRAMES 0x00000020
  82. #define SM95_HARDWARE_CONFIG_RX_DATA_OFFSET_MASK 0x00000600
  83. #define SM95_HARDWARE_CONFIG_RX_DATA_OFFSET_SHIFT 9
  84. #define SM95_HARDWARE_CONFIG_BULK_IN_EMPTY_RESPONSE 0x00001000
  85. //
  86. // Define the offset after the SM95 receive header at which the Ethernet frame
  87. // should begin.
  88. //
  89. #define SM95_RECEIVE_DATA_OFFSET 2
  90. //
  91. // Define Power Control register bits.
  92. //
  93. #define SM95_POWER_CONTROL_PHY_RESET 0x00000010
  94. //
  95. // Define LED GPIO Configuration register bits.
  96. //
  97. #define SM95_LED_GPIO_CONFIG_SPEED_LED 0x01000000
  98. #define SM95_LED_GPIO_CONFIG_LINK_LED 0x00100000
  99. #define SM95_LED_GPIO_CONFIG_FULL_DUPLEX_LED 0x00010000
  100. //
  101. // Define Interrupt Endpoint Control register bits.
  102. //
  103. #define SM95_INTERRUPT_ENDPOINT_CONTROL_PHY_INTERRUPTS 0x00008000
  104. //
  105. // Define an auto-flow control default with a high water mark of 15.5KB, a
  106. // low water mark of 3KB, and a backpressure duration of about 350us.
  107. //
  108. #define SM95_AUTO_FLOW_CONTROL_DEFAULT 0x00F830A1
  109. //
  110. // Define MAC control register bits.
  111. //
  112. #define SM95_MAC_CONTROL_PROMISCUOUS 0x80000000
  113. #define SM95_MAC_CONTROL_RECEIVE_OWN 0x00800000
  114. #define SM95_MAC_CONTROL_LOOPBACK 0x00200000
  115. #define SM95_MAC_CONTROL_FULL_DUPLEX 0x00100000
  116. #define SM95_MAC_CONTROL_MULTICAST_PAS 0x00080000
  117. #define SM95_MAC_CONTROL_PRMS 0x00040000
  118. #define SM95_MAC_CONTROL_PASS_BAD 0x00010000
  119. #define SM95_MAC_CONTROL_HP_FILTER 0x00002000
  120. #define SM95_MAC_CONTROL_ENABLE_TRANSMIT 0x00000008
  121. #define SM95_MAC_CONTROL_ENABLE_RECEIVE 0x00000004
  122. //
  123. // Define MII address register bits.
  124. //
  125. #define SM95_MII_ADDRESS_BUSY 0x00000001
  126. #define SM95_MII_ADDRESS_WRITE 0x00000002
  127. #define SM95_MII_ADDRESS_PHY_ID_SHIFT 11
  128. #define SM95_MII_ADDRESS_INDEX_SHIFT 6
  129. //
  130. // Define EEPROM command register bits.
  131. //
  132. #define SM95_EEPROM_COMMAND_BUSY 0x80000000
  133. #define SM95_EEPROM_COMMAND_TIMEOUT 0x00000400
  134. #define SM95_EEPROM_COMMAND_LOADED 0x00000200
  135. #define SM95_EEPROM_COMMAND_ADDRESS_MASK 0x000001FF
  136. //
  137. // Define checksum offload control register bits.
  138. //
  139. #define SM95_CHECKSUM_CONTROL_TRANSMIT_ENABLE 0x00010000
  140. #define SM95_CHECKSUM_CONTROL_RECEIVE_ENABLE 0x00000001
  141. //
  142. // Define the VLAN1 register value for 802.1Q extended headers.
  143. //
  144. #define SM95_VLAN_8021Q 0x8100
  145. //
  146. // Define PHY Interrupt mask bits.
  147. //
  148. #define SM95_PHY_INTERRUPT_AUTONEGOTIATION_COMPLETE 0x0040
  149. #define SM95_PHY_INTERRUPT_LINK_DOWN 0x0010
  150. //
  151. // Define transmit packet flags.
  152. //
  153. #define SM95_TRANSMIT_FLAG_FIRST_SEGMENT 0x00002000
  154. #define SM95_TRANSMIT_FLAG_LAST_SEGMENT 0x00001000
  155. //
  156. // Define receive packet flags.
  157. //
  158. #define SM95_RECEIVE_FLAG_CRC_ERROR 0x00000002
  159. #define SM95_RECEIVE_FLAG_DRIBBLING_BIT 0x00000004
  160. #define SM95_RECEIVE_FLAG_MII_ERROR 0x00000008
  161. #define SM95_RECEIVE_FLAG_WATCHDOG_TIMEOUT 0x00000010
  162. #define SM95_RECEIVE_FLAG_ETHERNET_FRAME 0x00000020
  163. #define SM95_RECEIVE_FLAG_COLLISION 0x00000040
  164. #define SM95_RECEIVE_FLAG_FRAME_TOO_LONG 0x00000080
  165. #define SM95_RECEIVE_FLAG_MULTICAST_FRAME 0x00000400
  166. #define SM95_RECEIVE_FLAG_RUNT_FRAME 0x00000800
  167. #define SM95_RECEIVE_FLAG_LENGTH_ERROR 0x00001000
  168. #define SM95_RECEIVE_FLAG_BROADCAST_FRAME 0x00002000
  169. #define SM95_RECEIVE_FLAG_ERROR_SUMMARY 0x00008000
  170. #define SM95_RECEIVE_FRAME_LENGTH_MASK 0x3FFF0000
  171. #define SM95_RECEIVE_FRAME_LENGTH_SHIFT 16
  172. //
  173. // Define the number of bulk IN transfer to allocate.
  174. //
  175. #define SM95_BULK_IN_TRANSFER_COUNT 5
  176. //
  177. // ------------------------------------------------------ Data Type Definitions
  178. //
  179. //
  180. // Define PHY registers specific to the SMSC95xx device.
  181. //
  182. typedef enum _SM95_PHY_REGISTER {
  183. Sm95PhyRegisterInterruptSource = 0x1D,
  184. Sm95PhyRegisterInterruptMask = 0x1E,
  185. } SM95_PHY_REGISTER, *PSM95_PHY_REGISTER;
  186. typedef enum _SM95_REGISTER {
  187. Sm95RegisterIdRevision = 0x00,
  188. Sm95RegisterInterruptStatus = 0x08,
  189. Sm95RegisterTransmitControl = 0x10,
  190. Sm95RegisterHardwareConfig = 0x14,
  191. Sm95RegisterPowerControl = 0x20,
  192. Sm95RegisterLedGpioConfig = 0x24,
  193. Sm95RegisterAutoFlowControl = 0x2C,
  194. Sm95RegisterEepromCommand = 0x30,
  195. Sm95RegisterEepromData = 0x34,
  196. Sm95RegisterBurstCapability = 0x38,
  197. Sm95RegisterInterruptEndpointControl = 0x68,
  198. Sm95RegisterBulkInDelay = 0x6C,
  199. Sm95RegisterMacControl = 0x100,
  200. Sm95RegisterMacAddressHigh = 0x104,
  201. Sm95RegisterMacAddressLow = 0x108,
  202. Sm95RegisterMiiAddress = 0x114,
  203. Sm95RegisterMiiData = 0x118,
  204. Sm95RegisterFlowControl = 0x11C,
  205. Sm95RegisterVlan1 = 0x120,
  206. Sm95RegisterChecksumOffloadControl = 0x130,
  207. } SM95_REGISTER, *PSM95_REGISTER;
  208. /*++
  209. Structure Description:
  210. This structure defines an SMSC95xx LAN device.
  211. Members:
  212. OsDevice - Stores a pointer to the system device object.
  213. NetworkLink - Stores a pointer to the core networking link.
  214. UsbCoreHandle - Stores the handle returned by the USB core.
  215. ReferenceCount - Stores the reference count for the device.
  216. IoBuffer - Stores a pointer to the I/O buffer used for both the bulk
  217. receive and the control transfers.
  218. ControlTransfer - Stores a pointer to the control transfer used for
  219. register reads and writes.
  220. InterruptTransfer - Stores a pointer to the interrupt transfer used to get
  221. notifications from the device.
  222. BulkInTransfer - Stores an array of pointers to transfers used to receive
  223. packets.
  224. BulkOutFreeTransferList - Stores the head of the list of free transfers to
  225. use to send data.
  226. BulkOutTransferCount - Stores the number of currently submitted bulk out
  227. transfers.
  228. BulkOutListLock - Stores a pointer to a lock that protects the list of free
  229. bulk OUT transfers.
  230. PhyId - Stores the device ID of the PHY on the controller's internal
  231. interconnect bus.
  232. MacControl - Stores a shadow copy of the MAC control register so that it
  233. does not have to be read constantly.
  234. InterfaceClaimed - Stores a boolean indicating if the interface has
  235. already been claimed.
  236. InterfaceNumber - Stores the number of the interface this device interacts
  237. on.
  238. BulkInEndpoint - Stores the endpoint number for the bulk in endpoint.
  239. BulkOutEndpoint - Stores the endpoint number for the bulk out endpoint.
  240. InterruptEndpoint - Stores the endpoint number for the interrupt (in)
  241. endpoint.
  242. MacAddress - Stores the default MAC address of the device.
  243. --*/
  244. typedef struct _SM95_DEVICE {
  245. PDEVICE OsDevice;
  246. PNET_LINK NetworkLink;
  247. HANDLE UsbCoreHandle;
  248. volatile ULONG ReferenceCount;
  249. PIO_BUFFER IoBuffer;
  250. PUSB_TRANSFER ControlTransfer;
  251. PUSB_TRANSFER InterruptTransfer;
  252. PUSB_TRANSFER BulkInTransfer[SM95_BULK_IN_TRANSFER_COUNT];
  253. LIST_ENTRY BulkOutFreeTransferList;
  254. volatile ULONG BulkOutTransferCount;
  255. PQUEUED_LOCK BulkOutListLock;
  256. ULONG PhyId;
  257. ULONG MacControl;
  258. BOOL InterfaceClaimed;
  259. UCHAR InterfaceNumber;
  260. UCHAR BulkInEndpoint;
  261. UCHAR BulkOutEndpoint;
  262. UCHAR InterruptEndpoint;
  263. BYTE MacAddress[ETHERNET_ADDRESS_SIZE];
  264. } SM95_DEVICE, *PSM95_DEVICE;
  265. //
  266. // -------------------------------------------------------------------- Globals
  267. //
  268. //
  269. // -------------------------------------------------------- Function Prototypes
  270. //
  271. KSTATUS
  272. Sm95Send (
  273. PVOID DeviceContext,
  274. PNET_PACKET_LIST PacketList
  275. );
  276. /*++
  277. Routine Description:
  278. This routine sends data through the network.
  279. Arguments:
  280. DeviceContext - Supplies a pointer to the device context associated with
  281. the link down which this data is to be sent.
  282. PacketList - Supplies a pointer to a list of network packets to send. Data
  283. in these packets may be modified by this routine, but must not be used
  284. once this routine returns.
  285. Return Value:
  286. STATUS_SUCCESS if all packets were sent.
  287. STATUS_RESOURCE_IN_USE if some or all of the packets were dropped due to
  288. the hardware being backed up with too many packets to send.
  289. Other failure codes indicate that none of the packets were sent.
  290. --*/
  291. KSTATUS
  292. Sm95GetSetInformation (
  293. PVOID DeviceContext,
  294. NET_LINK_INFORMATION_TYPE InformationType,
  295. PVOID Data,
  296. PUINTN DataSize,
  297. BOOL Set
  298. );
  299. /*++
  300. Routine Description:
  301. This routine gets or sets the network device layer's link information.
  302. Arguments:
  303. DeviceContext - Supplies a pointer to the device context associated with
  304. the link for which information is being set or queried.
  305. InformationType - Supplies the type of information being queried or set.
  306. Data - Supplies a pointer to the data buffer where the data is either
  307. returned for a get operation or given for a set operation.
  308. DataSize - Supplies a pointer that on input contains the size of the data
  309. buffer. On output, contains the required size of the data buffer.
  310. Set - Supplies a boolean indicating if this is a get operation (FALSE) or a
  311. set operation (TRUE).
  312. Return Value:
  313. Status code.
  314. --*/
  315. VOID
  316. Sm95InterruptTransferCompletion (
  317. PUSB_TRANSFER Transfer
  318. );
  319. /*++
  320. Routine Description:
  321. This routine is called when the interrupt transfer returns. It processes
  322. the notification from the device.
  323. Arguments:
  324. Transfer - Supplies a pointer to the transfer that completed.
  325. Return Value:
  326. None.
  327. --*/
  328. VOID
  329. Sm95BulkInTransferCompletion (
  330. PUSB_TRANSFER Transfer
  331. );
  332. /*++
  333. Routine Description:
  334. This routine is called when the bulk in transfer returns. It processes
  335. the notification from the device.
  336. Arguments:
  337. Transfer - Supplies a pointer to the transfer that completed.
  338. Return Value:
  339. None.
  340. --*/
  341. KSTATUS
  342. Sm95pInitialize (
  343. PSM95_DEVICE Device
  344. );
  345. /*++
  346. Routine Description:
  347. This routine initializes and enables the SMSC95xx device.
  348. Arguments:
  349. Device - Supplies a pointer to the device.
  350. Return Value:
  351. Status code.
  352. --*/
  353. VOID
  354. Sm95pDestroyBulkOutTransfers (
  355. PSM95_DEVICE Device
  356. );
  357. /*++
  358. Routine Description:
  359. This routine destroys the SMSC95xx device's bulk out tranfers.
  360. Arguments:
  361. Device - Supplies a pointer to the device.
  362. Return Value:
  363. None.
  364. --*/
  365. KSTATUS
  366. Sm95pAddNetworkDevice (
  367. PSM95_DEVICE Device
  368. );
  369. /*++
  370. Routine Description:
  371. This routine adds the device to core networking's available links.
  372. Arguments:
  373. Device - Supplies a pointer to the device to add.
  374. Return Value:
  375. Status code.
  376. --*/