Minoca-os/include/minoca/soc/am335x.h

/*++

Copyright (c) 2015 Minoca Corp. All Rights Reserved

Module Name:

    am335x.h

Abstract:

    This header contains hardware definitions for the TI AM335x SoCs.

Author:

    Evan Green 6-Jan-2015

--*/

//
// ------------------------------------------------------------------- Includes
//

//
// --------------------------------------------------------------------- Macros
//

#define AM335_PAD_GPMC_AD(_Index) (0x800 + ((_Index) * 4))
#define AM335_PAD_GPMC_A(_Index) (0x840 + ((_Index) * 4))
#define AM335_PAD_LCD_DATA(_Index) (0x8A0 + ((_Index) * 4))
#define AM335_PAD_UART_RXD(_Index) (0x970 + ((_Index) * 0x10))
#define AM335_PAD_UART_TXD(_Index) (0x974 + ((_Index) * 0x10))
#define AM335_SOC_CONTROL_DDR_CMD_IO_CONTROL(_Index) (0x1404 + ((_Index) * 4))
#define AM335_SOC_CONTROL_DDR_DATA_IO_CONTROL(_Index) (0x1440 + ((_Index) * 4))
#define AM335_PAD_MUXCODE(_Code) (_Code)

//
// These macros access interrupt controller registers.
//

#define AM335_INTC_LINE_TO_INDEX(_Line) ((_Line) >> 5)
#define AM335_INTC_LINE_TO_MASK(_Line) (1 << ((_Line) & 0x1F))
#define AM335_INTC_MASK(_Index) (Am335IntcMask + ((_Index) * 0x20))
#define AM335_INTC_MASK_CLEAR(_Index) (Am335IntcMaskClear + ((_Index) * 0x20))
#define AM335_INTC_MASK_SET(_Index) (Am335IntcMaskSet + ((_Index) * 0x20))
#define AM335_INTC_LINE(_Line) (Am335IntcLine + ((_Line) * 0x4))

//
// This macro fills in the bits of the raster timing 0 register given a number
// of pixels per line (which is the horizontal resolution minus one).
//

#define AM335_LCD_RESOLUTION_X_TO_TIMING_0(_PixelsPerLine) \
    (((_PixelsPerLine) & 0x000003F0) | (((_PixelsPerLine) & 0x00000400) >> 7))

//
// These macros convert a vertical lines per panel to timing 1 and 2 values.
// Lines per panel is the vertical resolution minus one.
//

#define AM335_LCD_RESOLUTION_Y_TO_TIMING_1(_LinesPerPanel) \
    ((_LinesPerPanel) & 0x000003FF)

#define AM335_LCD_RESOLUTION_Y_TO_TIMING_2(_LinesPerPanel)  \
    ((((_LinesPerPanel) & 0x00000400) >> 10) <<             \
     AM335_LCD_RASTER_TIMING_2_LINES_PER_PANEL_BIT_10_SHIFT)

//
// ---------------------------------------------------------------- Definitions
//

//
// Define the number of timers in the SoC.
//

#define AM335X_TIMER_COUNT 8

//
// Define attributes of the timers.
//

#define AM335_TIMER_BIT_WIDTH 32
#define AM335_TIMER_FREQUENCY_32KHZ 32768
#define AM335_TIMER_CONTROLLER_SIZE 0x1000
#define AM335_WATCHDOG_SIZE 0x1000

//
// Define the size of the interrupt controller register space.
//

#define AM335_INTC_CONTROLLER_SIZE 0x1000

//
// Define the number of unique interrupt priorities in the INTC controller.
//

#define AM335_INTC_PRIORITY_COUNT 63

#define AM335_MAX_INTERRUPT_LINES (32 * 4)
#define AM335_MAX_INTERRUPT_LINE_BLOCKS \
    AM335_INTC_LINE_TO_INDEX(AM335_MAX_INTERRUPT_LINES)

//
// Define the fixed 32.768kHz frequency floating around the SoC in various
// locations.
//

#define AM335_32KHZ_FREQUENCY 32768

//
// Define the interrupt map.
//

#define AM335_IRQ_DMTIMER0 66
#define AM335_IRQ_DMTIMER1 67
#define AM335_IRQ_DMTIMER2 68
#define AM335_IRQ_DMTIMER3 69
#define AM335_IRQ_DMTIMER4 92
#define AM335_IRQ_DMTIMER5 93
#define AM335_IRQ_DMTIMER6 94
#define AM335_IRQ_DMTIMER7 95

//
// Define peripheral bases.
//

#define AM335_OCMC_BASE 0x40300000
#define AM335_PRCM_REGISTERS 0x44E00000
#define AM335_DMTIMER0_BASE 0x44E05000
#define AM335_GPIO_0_BASE 0x44E07000
#define AM335_UART_0_BASE 0x44E09000
#define AM335_UART_1_BASE 0x44E0A000
#define AM335_I2C_0_BASE 0x44E0B000
#define AM335_SOC_CONTROL_REGISTERS 0x44E10000
#define AM335_DMTIMER1_BASE 0x44E31000
#define AM335_WATCHDOG_BASE 0x44E35000
#define AM335_RTC_BASE 0x44E3E000
#define AM335_DMTIMER2_BASE 0x48040000
#define AM335_DMTIMER3_BASE 0x48042000
#define AM335_DMTIMER4_BASE 0x48044000
#define AM335_DMTIMER5_BASE 0x48046000
#define AM335_DMTIMER6_BASE 0x48048000
#define AM335_DMTIMER7_BASE 0x4804A000
#define AM335_GPIO_1_BASE 0x4804C000
#define AM335_HSMMC_0_BASE 0x48060000
#define AM335_GPIO_2_BASE 0x481AC000
#define AM335_GPIO_3_BASE 0x481AE000
#define AM335_HSMMC_1_BASE 0x481D8000
#define AM335_INTC_BASE 0x48200000
#define AM335_LCD_REGISTERS 0x4830E000
#define AM335_EMIF_0_REGISTERS 0x4C000000

#define AM335_CORTEX_M3_CODE_SIZE 0x4000
#define AM335_CORTEX_M3_DATA_SIZE 0x2000
#define AM335_MAILBOX_SIZE 0x1000
#define AM335_RTC_SIZE 0x1000
#define AM335_OCMC_SIZE 0x10000
#define AM335_EMIF_SIZE 0x1000

//
// Define PRCM offsets.
//

#define AM335_PRCM_SIZE 0x2000
#define AM335_CM_PER_OFFSET 0x0000
#define AM335_CM_WAKEUP_OFFSET 0x0400
#define AM335_CM_DPLL_OFFSET 0x0500
#define AM335_CM_MPU_OFFSET 0x0600
#define AM335_CM_DEVICE_OFFSET 0x0700
#define AM335_CM_RTC_OFFSET 0x0800
#define AM335_CM_GFX_OFFSET 0x0900
#define AM335_CM_CEFUSE_OFFSET 0x0A00
#define AM335_PRM_IRQ_OFFSET 0x0B00
#define AM335_PRM_PER_OFFSET 0x0C00
#define AM335_PRM_WAKEUP_OFFSET 0x0D00
#define AM335_PRM_MPU_OFFSET 0x0E00
#define AM335_PRM_DEVICE_OFFSET 0x0F00
#define AM335_PRM_RTC_OFFSET 0x1000
#define AM335_PRM_GFX_OFFSET 0x1100
#define AM335_PRM_CEFUSE_OFFSET 0x1200

#define AM335_CM_PER_REGISTERS (AM335_PRCM_REGISTERS + AM335_CM_PER_OFFSET)
#define AM335_CM_WAKEUP_REGISTERS \
    (AM335_PRCM_REGISTERS + AM335_CM_WAKEUP_OFFSET)

#define AM335_SOC_CM_DPLL_REGISTERS \
    (AM335_PRCM_REGISTERS + AM335_CM_DPLL_OFFSET)

#define AM335_PRM_DEVICE_REGISTERS \
    (AM335_PRCM_REGISTERS + AM335_PRM_DEVICE_OFFSET)

//
// CM wakeup registers.
//

#define AM335_CM_WAKEUP_CLOCK_STATE_CONTROL 0x000
#define AM335_CM_WAKEUP_CONTROL_CLOCK_CONTROL 0x004
#define AM335_CM_WAKEUP_L4WKUP_CLOCK_CONTROL 0x00C
#define AM335_CM_WAKEUP_TIMER0_CLOCK_CONTROL 0x10
#define AM335_CM_WAKEUP_L3_AON_CLOCK_STATE_CONTROL 0x018
#define AM335_CM_WAKEUP_IDLE_STATUS_DPLL_MPU 0x020
#define AM335_CM_WAKEUP_CLOCK_SELECT_DPLL_MPU 0x02C
#define AM335_CM_WAKEUP_IDLE_STATUS_DPLL_DDR 0x034
#define AM335_CM_WAKEUP_CLOCK_SELECT_DPLL_DDR 0x040
#define AM335_CM_WAKEUP_IDLE_STATUS_DPLL_DISP 0x048
#define AM335_CM_WAKEUP_CLOCK_SELECT_DPLL_DISP 0x054
#define AM335_CM_WAKEUP_IDLE_STATUS_DPLL_CORE 0x05C
#define AM335_CM_WAKEUP_CLOCK_SELECT_DPLL_CORE 0x068
#define AM335_CM_WAKEUP_IDLE_STATUS_DPLL_PER 0x070
#define AM335_CM_WAKEUP_CLOCK_DCO_LDO_DPLL_PER 0x7C
#define AM335_CM_WAKEUP_DIV_M4_DPLL_CORE 0x080
#define AM335_CM_WAKEUP_DIV_M5_DPLL_CORE 0x084
#define AM335_CM_WAKEUP_CLOCK_MODE_DPLL_MPU 0x088
#define AM335_CM_WAKEUP_CLOCK_MODE_DPLL_PER 0x08C
#define AM335_CM_WAKEUP_CLOCK_MODE_DPLL_CORE 0x090
#define AM335_CM_WAKEUP_CLOCK_MODE_DPLL_DDR 0x094
#define AM335_CM_WAKEUP_CLOCK_MODE_DPLL_DISP 0x098
#define AM335_CM_WAKEUP_CLOCK_SELECT_DPLL_PER 0x09C
#define AM335_CM_WAKEUP_DIV_M2_DPLL_DDR 0x0A0
#define AM335_CM_WAKEUP_DIV_M2_DPLL_DISP 0x0A4
#define AM335_CM_WAKEUP_DIV_M2_DPLL_MPU 0x0A8
#define AM335_CM_WAKEUP_DIV_M2_DPLL_PER 0x0AC
#define AM335_CM_WAKEUP_UART0_CLOCK_CONTROL 0x0B4
#define AM335_CM_WAKEUP_I2C0_CLOCK_CONTROL 0x0B8
#define AM335_CM_WAKEUP_TIMER1_CLOCK_CONTROL 0x0C4
#define AM335_CM_WAKEUP_L4WKUP_AON_CLOCK_STATE_CONTROL 0x0CC
#define AM335_CM_WAKEUP_DIV_M6_DPLL_CORE 0x0D8

//
// CM wakeup clock state control register bits.
//

#define AM335_CM_WAKEUP_CLOCK_STATE_SOFTWARE_WAKEUP 0x00000002
#define AM335_CM_WAKEUP_CLOCK_STATE_TRANSITION_MASK 0x00000003
#define AM335_CM_WAKEUP_CLOCK_STATE_L4WAKEUP_ACTIVE 0x00000004
#define AM335_CM_WAKEUP_CLOCK_STATE_I2C0_ACTIVE 0x00000800
#define AM335_CM_WAKEUP_CLOCK_STATE_UART0_ACTIVE 0x00001000

//
// CM wakeup control clock control bits.
//

#define AM335_CM_WAKEUP_CONTROL_CLOCK_ENABLE 0x00000002
#define AM335_CM_WAKEUP_CONTROL_CLOCK_MODE_MASK 0x00000003
#define AM335_CM_WAKEUP_CONTROL_CLOCK_IDLE_STATE_FUNCTIONAL (0x0 << 16)
#define AM335_CM_WAKEUP_CONTROL_CLOCK_IDLE_STATE_MASK (0x3 << 16)

//
// CM wakeup L4 wakeup clock control register bits.
//

#define AM335_CM_WAKEUP_L4WKUP_CLOCK_IDLE_STATE_FUNCTIONAL (0x0 << 16)
#define AM335_CM_WAKEUP_L4WKUP_CLOCK_IDLE_STATE_MASK (0x3 << 16)

//
// CM wakeup L3 always on clock state register bits.
//

#define AM335_CM_WAKEUP_L3_AON_CLOCK_STATE_SOFTWARE_WAKEUP 0x00000002
#define AM335_CM_WAKEUP_L3_AON_CLOCK_STATE_TRANSITION_MASK 0x00000003
#define AM335_CM_WAKEUP_L3_AON_CLOCK_STATE_ACTIVE 0x00000008

//
// CM wakeup UART0 clock control register bits.
//

#define AM335_CM_WAKEUP_UART0_CONTROL_CLOCK_ENABLE 0x00000002
#define AM335_CM_WAKEUP_UART0_CLOCK_MODE_MASK 0x00000003
#define AM335_CM_WAKEUP_UART0_CLOCK_IDLE_STATE_FUNCTIONAL (0x0 << 16)
#define AM335_CM_WAKEUP_UART0_CLOCK_IDLE_STATE_MASK (0x3 << 16)

//
// CM wakeup I2C0 clock control register bits.
//

#define AM335_CM_WAKEUP_I2C0_CONTROL_CLOCK_ENABLE 0x00000002
#define AM335_CM_WAKEUP_I2C0_CLOCK_MODE_MASK 0x00000003
#define AM335_CM_WAKEUP_I2C0_CLOCK_IDLE_STATE_FUNCTIONAL (0x0 << 16)
#define AM335_CM_WAKEUP_I2C0_CLOCK_IDLE_STATE_MASK (0x3 << 16)

//
// CM wakeup L4 wakeup always on clock state register bits.
//

#define AM335_CM_WAKEUP_L4WKUP_AON_CLOCK_STATE_ACTIVE 0x00000004

//
// CM Wakeup DDR PLL clock mode register bits.
//

#define AM335_CM_WAKEUP_CLOCK_MODE_DPLL_DDR_ENABLE_MN_BYPASS 0x00000004
#define AM335_CM_WAKEUP_CLOCK_MODE_DPLL_DDR_ENABLE 0x0000007

//
// CM Wakeup DDR PLL idle status register bits.
//

#define AM335_CM_WAKEUP_IDLE_STATUS_DPLL_DDR_MN_BYPASS 0x00000100
#define AM335_CM_WAKEUP_IDLE_STATUS_DPLL_DDR_CLOCK 0x00000001

//
// CM Wakeup MPU PLL clock select register bits.
//

#define AM335_CM_WAKEUP_CLOCK_SELECT_DPLL_DDR_DIV_MASK 0x0000007F
#define AM335_CM_WAKEUP_CLOCK_SELECT_DPLL_DDR_DIV_SHIFT 0
#define AM335_CM_WAKEUP_CLOCK_SELECT_DPLL_DDR_MULT_MASK 0x0007FF00
#define AM335_CM_WAKEUP_CLOCK_SELECT_DPLL_DDR_MULT_SHIFT 8

//
// CM Wakeup MPU PLL M2 divisor register bits.
//

#define AM335_CM_WAKEUP_DIV_M2_DPLL_DDR_CLOCK_OUT_MASK 0x0000001F

//
// CM Wakeup PER PLL clock mode register bits.
//

#define AM335_CM_WAKEUP_CLOCK_MODE_DPLL_PER_ENABLE_MN_BYPASS 0x00000004
#define AM335_CM_WAKEUP_CLOCK_MODE_DPLL_PER_ENABLE 0x0000007

//
// CM Wakeup PER PLL idle status register bits.
//

#define AM335_CM_WAKEUP_IDLE_STATUS_DPLL_PER_MN_BYPASS 0x00000100
#define AM335_CM_WAKEUP_IDLE_STATUS_DPLL_PER_CLOCK 0x00000001

//
// CM Wakeup PER PLL clock select register bits.
//

#define AM335_CM_WAKEUP_CLOCK_SELECT_DPLL_PER_MULT_SHIFT 8
#define AM335_CM_WAKEUP_CLOCK_SELECT_DPLL_PER_DIV_SHIFT 0

//
// CM Wakeup PER PLL M2 divider register bits.
//

#define AM335_CM_WAKEUP_DIV_M2_DPLL_PER_CLOCK_OUT_DIV_MASK 0x0000007F
#define AM335_CM_WAKEUP_DIV_M2_DPLL_PER_CLOCK_OUT_DIV_SHIFT 0

//
// CM Wakeup CORE PLL clock mode register bits.
//

#define AM335_CM_WAKEUP_CLOCK_MODE_DPLL_CORE_ENABLE_MN_BYPASS 0x00000004
#define AM335_CM_WAKEUP_CLOCK_MODE_DPLL_CORE_ENABLE 0x0000007

//
// CM Wakeup CORE PLL idle status register bits.
//

#define AM335_CM_WAKEUP_IDLE_STATUS_DPLL_CORE_MN_BYPASS 0x00000100
#define AM335_CM_WAKEUP_IDLE_STATUS_DPLL_CORE_CLOCK 0x00000001

//
// CM Wakeup CORE PLL clock select register bits.
//

#define AM335_CM_WAKEUP_CLOCK_SELECT_DPLL_CORE_DIV_SHIFT 0
#define AM335_CM_WAKEUP_CLOCK_SELECT_DPLL_CORE_MULT_SHIFT 8

//
// CM Wakeup CORE PLL M4 divider register bits.
//

#define AM335_CM_WAKEUP_DIV_M4_DPLL_CORE_HSDIVIDER_CLOCK_OUT1_DIV_MASK \
    0x0000001F

#define AM335_CM_WAKEUP_DIV_M4_DPLL_CORE_HSDIVIDER_CLOCK_OUT1_DIV_SHIFT 0

//
// CM Wakeup CORE PLL M5 divider register bits.
//

#define AM335_CM_WAKEUP_DIV_M5_DPLL_CORE_HSDIVIDER_CLOCK_OUT2_DIV_MASK \
    0x0000001F

#define AM335_CM_WAKEUP_DIV_M5_DPLL_CORE_HSDIVIDER_CLOCK_OUT2_DIV_SHIFT 0

//
// CM Wakeup CORE PLL M6 divider register bits.
//

#define AM335_CM_WAKEUP_DIV_M6_DPLL_CORE_HSDIVIDER_CLOCK_OUT3_DIV_MASK \
    0x0000001F

#define AM335_CM_WAKEUP_DIV_M6_DPLL_CORE_HSDIVIDER_CLOCK_OUT3_DIV_SHIFT 0

//
// Define CM DPLL registers.
//

#define AM335_CM_DPLL_CLOCK_SELECT_TIMER7 0x04
#define AM335_CM_DPLL_CLOCK_SELECT_TIMER2 0x08
#define AM335_CM_DPLL_CLOCK_SELECT_TIMER3 0x0C
#define AM335_CM_DPLL_CLOCK_SELECT_TIMER4 0x10
#define AM335_CM_DPLL_CLOCK_SELECT_TIMER5 0x18
#define AM335_CM_DPLL_CLOCK_SELECT_TIMER6 0x1C
#define AM335_CM_DPLL_CLOCK_SELECT_TIMER1 0x28
#define AM335_CM_DPLL_CLOCK_SELECT_LCD 0x34

//
// CM DPLL clock select timer register bits (any timer except 1).
//

#define AM335_CM_DPLL_CLOCK_SELECT_TIMER_MASK 0x00000003
#define AM335_CM_DPLL_CLOCK_SELECT_TIMER_TCLKIN 0x0
#define AM335_CM_DPLL_CLOCK_SELECT_TIMER_SYSTEM_CLOCK 0x1
#define AM335_CM_DPLL_CLOCK_SELECT_TIMER_32KHZ 0x2

#define AM335_CM_PER_TIMER2_CLOCK_ENABLE 0x00000002

#define AM335_CM_WAKEUP_TIMER0_CLOCK_ENABLE 0x00000002

//
// CM Wakeup Timer1 PLL clock select register bits.
//

#define AM335_CM_DPLL_CLOCK_SELECT_TIMER1_32KHZ 0x00000001

//
// Define CM PER registers.
//

#define AM335_CM_PER_L4LS_CLOCK_STATE_CONTROL 0x000
#define AM335_CM_PER_L3S_CLOCK_STATE_CONTROL 0x004
#define AM335_CM_PER_L4FW_CLOCK_STATE_CONTROL 0x008
#define AM335_CM_PER_L3_CLOCK_STATE_CONTROL 0x00C
#define AM335_CM_PER_CPGMAC0_CLOCK_CONTROL 0x014
#define AM335_CM_PER_LCD_CLOCK_CONTROL 0x018
#define AM335_CM_PER_USB0_CLOCK_CONTROL 0x1C
#define AM335_CM_PER_TPTC0_CLOCK_CONTROL 0x024
#define AM335_CM_PER_EMIF_CLOCK_CONTROL 0x028
#define AM335_CM_PER_MMC0_CLOCK_CONTROL 0x03C
#define AM335_CM_PER_L4LS_CLOCK_CONTROL 0x060
#define AM335_CM_PER_L4FW_CLOCK_CONTROL 0x064
#define AM335_CM_PER_TIMER7_CLOCK_CONTROL 0x07C
#define AM335_CM_PER_TIMER2_CLOCK_CONTROL 0x080
#define AM335_CM_PER_TIMER3_CLOCK_CONTROL 0x084
#define AM335_CM_PER_TIMER4_CLOCK_CONTROL 0x088
#define AM335_CM_PER_GPIO1_CLOCK_CONTROL 0x0AC
#define AM335_CM_PER_TPCC_CLOCK_CONTROL 0x0BC
#define AM335_CM_PER_MMC1_CLOCK_CONTROL 0x0F4
#define AM335_CM_PER_CPSW_CLOCK_STATE_CONTROL 0x144
#define AM335_CM_PER_EMIF_FW_CLOCK_CONTROL 0x0D0
#define AM335_CM_PER_L3_INSTR_CLOCK_CONTROL 0x0DC
#define AM335_CM_PER_L3_CLOCK_CONTROL 0x0E0
#define AM335_CM_PER_TIMER5_CLOCK_CONTROL 0x0EC
#define AM335_CM_PER_TIMER6_CLOCK_CONTROL 0x0F0
#define AM335_CM_PER_TPTC1_CLOCK_CONTROL 0x0FC
#define AM335_CM_PER_TPTC2_CLOCK_CONTROL 0x100
#define AM335_CM_PER_MAILBOX_CLOCK_CONTROL 0x110
#define AM335_CM_PER_L4HS_CLOCK_CONTROL 0x120
#define AM335_CM_PER_OCPWP_L3_CLOCK_STATE_CONTROL 0x12C

//
// CM Per MMC0 clock control register bits.
//

#define AM335_CM_PER_MMC0_CLOCK_ENABLE 0x00000002

//
// CM Per MMC0 clock control register bits.
//

#define AM335_CM_PER_MMC1_CLOCK_ENABLE 0x00000002

//
// L4LS clock state control register bits.
//

#define AM335_CM_PER_L4LS_CLOCK_STATE_ACTIVITY_GPIO1 (1 << 19)
#define AM335_CM_PER_L4LS_CLOCK_STATE_SOFTWARE_WAKEUP 0x00000002

//
// L4FW clock state control register bits.
//

#define AM335_CM_PER_L4FW_CLOCK_STATE_SOFTWARE_WAKEUP 0x00000002

//
// TPTC0 clock control register bits.
//

#define AM335_CM_PER_TPTC0_CLOCK_ENABLE 0x00000002

//
// TPTC1 clock control register bits.
//

#define AM335_CM_PER_TPTC1_CLOCK_ENABLE 0x00000002

//
// TPTC2 clock control register bits.
//

#define AM335_CM_PER_TPTC2_CLOCK_ENABLE 0x00000002

//
// GPIO1 CM PER Clock control register bits.
//

#define AM335_CM_PER_GPIO1_CLOCK_ENABLE 0x2
#define AM335_CM_PER_GPIO1_CLOCK_MODE_MASK 0x3
#define AM335_CM_PER_GPIO1_CLOCK_IDLE_STATE_FUNCTIONAL (0x0 << 16)
#define AM335_CM_PER_GPIO1_CLOCK_IDLE_STATE_MASK (0x3 << 16)
#define AM335_CM_PER_GPIO1_CLOCK_FUNCTIONAL_CLOCK_ENABLE (1 << 18)

//
// TPCC CM PER Clock control register bits.
//

#define AM335_CM_PER_TPCC_CLOCK_ENABLE 0x2
#define AM335_CM_PER_TPCC_CLOCK_MODE_MASK 0x3
#define AM335_CM_PER_TPCC_CLOCK_IDLE_STATE_FUNCTIONAL (0x0 << 16)
#define AM335_CM_PER_TPCC_CLOCK_IDLE_STATE_MASK (0x3 << 16)
#define AM335_CM_PER_TPCC_CLOCK_FUNCTIONAL_CLOCK_ENABLE (1 << 18)

//
// L3 clock control register bits.
//

#define AM335_CM_PER_L3_CLOCK_ENABLE 0x00000002
#define AM335_CM_PER_L3_CLOCK_MODE_MASK 0x00000003
#define AM335_CM_PER_L3_CLOCK_IDLE_STATE_FUNCTIONAL (0x0 << 16)
#define AM335_CM_PER_L3_CLOCK_IDLE_STATE_MASK (0x3 << 16)

//
// CM Per CPGMAC0 clock control register bits.
//

#define AM335_CM_PER_CPGMAC0_CLOCK_ENABLE 0x00000002
#define AM335_CM_PER_CPGMAC0_CLOCK_IDLE_STATE_FUNCTIONAL 0x00000000
#define AM335_CM_PER_CPGMAC0_CLOCK_IDLE_STATE_MASK 0x00030000

//
// L3 Instr clock control bits.
//

#define AM335_CM_PER_L3_INSTR_CLOCK_ENABLE 0x00000002
#define AM335_CM_PER_L3_INSTR_CLOCK_MODE_MASK 0x00000003
#define AM335_CM_PER_L3_INSTR_CLOCK_IDLE_STATE_FUNCTIONAL (0x0 << 16)
#define AM335_CM_PER_L3_INSTR_CLOCK_IDLE_STATE_MASK (0x3 << 16)

//
// LCD clock control register bits.
//

#define AM335_CM_PER_LCD_CLOCK_ENABLE 0x00000002
#define AM335_CM_PER_LCD_CLOCK_MODE_MASK 0x00000003

//
// USB0 clock control register bits.
//

#define AM335_CM_PER_USB0_CLOCK_ENABLE 0x00000002
#define AM335_CM_PER_USB0_CLOCK_MODE_MASK 0x00000003

//
// Mailbox clock control register bits.
//

#define AM335_CM_PER_MAILBOX_CLOCK_ENABLE 0x00000002
#define AM335_CM_PER_MAILBOX_CLOCK_MODE_MASK 0x00000003

//
// CM PER EMIF Fw clock control register bits.
//

#define AM335_CM_PER_EMIF_FW_CLOCK_MODE_MASK 0x00000003
#define AM335_CM_PER_EMIF_FW_CLOCK_ENABLE 0x00000002

//
// CM PER EMIF Fw clock control register bits.
//

#define AM335_CM_PER_EMIF_CLOCK_MODE_MASK 0x00000003
#define AM335_CM_PER_EMIF_CLOCK_ENABLE 0x00000002

//
// L3 clock state control register bits.
//

#define AM335_CM_PER_L3_CLOCK_STATE_SOFTWARE_WAKEUP 0x00000002
#define AM335_CM_PER_L3_CLOCK_STATE_TRANSITION_MASK 0x00000003
#define AM335_CM_PER_L3_CLOCK_STATE_EMIF_ACTIVE 0x00000004
#define AM335_CM_PER_L3_CLOCK_STATE_ACTIVE 0x00000010

//
// OCPWP L3 clock state register bits.
//

#define AM335_CM_PER_OCPWP_L3_CLOCK_STATE_SOFTWARE_WAKEUP 0x00000002
#define AM335_CM_PER_OCPWP_L3_CLOCK_STATE_TRANSITION_MASK 0x00000003
#define AM335_CM_PER_OCPWP_L3_CLOCK_STATE_ACTIVE 0x00000010

//
// L3S clock state register bits.
//

#define AM335_CM_PER_L3S_CLOCK_STATE_SOFTWARE_WAKEUP 0x00000002
#define AM335_CM_PER_L3S_CLOCK_STATE_TRANSITION_MASK 0x00000003
#define AM335_CM_PER_L3S_CLOCK_STATE_ACTIVE 0x00000008

//
// L4LS clock control register bits.
//

#define AM335_CM_PER_L4LS_CLOCK_ENABLE 0x00000002
#define AM335_CM_PER_L4LS_CLOCK_MODE_MASK 0x00000003
#define AM335_CM_PER_L4LS_CLOCK_IDLE_STATE_FUNCTIONAL (0x0 << 16)
#define AM335_CM_PER_L4LS_CLOCK_IDLE_STATE_MASK (0x3 << 16)

//
// L4FW clock control register bits.
//

#define AM335_CM_PER_L4FW_CLOCK_ENABLE 0x00000002
#define AM335_CM_PER_L4FW_CLOCK_MODE_MASK 0x00000003
#define AM335_CM_PER_L4FW_CLOCK_IDLE_STATE_FUNCTIONAL (0x0 << 16)
#define AM335_CM_PER_L4FW_CLOCK_IDLE_STATE_MASK (0x3 << 16)

//
// CM Per CPSW clock state control register bits.
//

#define AM335_CM_PER_CPSW_CLOCK_STATE_SOFTWARE_WAKEUP 0x00000002
#define AM335_CM_PER_CPSW_CLOCK_STATE_CPSW_125MHZ_GCLK 0x00000010

//
// L4HS clock control register bits.
//

#define AM335_CM_PER_L4HS_CLOCK_ENABLE 0x00000002
#define AM335_CM_PER_L4HS_CLOCK_MODE_MASK 0x00000003
#define AM335_CM_PER_L4HS_CLOCK_IDLE_STATE_FUNCTIONAL (0x0 << 16)
#define AM335_CM_PER_L4HS_CLOCK_IDLE_STATE_MASK (0x3 << 16)

//
// CM Wakeup L4FW clock control register bits.
//

#define AM335_CM_WAKEUP_L4FW_CLOCK_ENABLE 0x00000002
#define AM335_CM_WAKEUP_L4FW_CLOCK_MODE_MASK 0x00000003
#define AM335_CM_WAKEUP_L4FW_CLOCK_IDLE_STATE_FUNCTIONAL (0x0 << 16)
#define AM335_CM_WAKEUP_L4FW_CLOCK_IDLE_STATE_MASK (0x3 << 16)

//
// CM DPLL LCD clock select register bits.
//

#define AM335_CM_DPLL_CLOCK_SELECT_LCD_DISP_PLL_CLKOUT_M2 0x0
#define AM335_CM_DPLL_CLOCK_SELECT_LCD_CORE_PLL_CLKOUT_M5 0x1
#define AM335_CM_DPLL_CLOCK_SELECT_LCD_PER_PLL_CLKOUT_M2 0x2

//
// Define EMIF registers.
//

#define AM335_EMIF_SDRAM_CONFIG 0x08
#define AM335_EMIF_SDRAM_REF_CONTROL 0x10
#define AM335_EMIF_SDRAM_REF_CONTROL_SHADOW 0x14
#define AM335_EMIF_SDRAM_TIM_1 0x18
#define AM335_EMIF_SDRAM_TIM_1_SHADOW 0x1C
#define AM335_EMIF_SDRAM_TIM_2 0x20
#define AM335_EMIF_SDRAM_TIM_2_SHADOW 0x24
#define AM335_EMIF_SDRAM_TIM_3 0x28
#define AM335_EMIF_SDRAM_TIM_3_SHADOW 0x2C
#define AM335_EMIF_ZQ_CONFIG 0xC8
#define AM335_EMIF_DDR_PHY_CONTROL_1 0xE4
#define AM335_EMIF_DDR_PHY_CONTROL_1_SHADOW 0xE8
#define AM335_EMIF_DDR_PHY_CONTROL_2 0xEC

//
// DDR3 CKE control register definitions.
//

#define AM335_DDR3_CONTROL_DDR_CKE_CONTROL 0x00000001

//
// Define SoC control registers.
//

#define AM335_SOC_CONTROL_STATUS 0x0040
#define AM335_SOC_CONTROL_SECURE_EMIF_SDRAM_CONFIG 0x0110
#define AM335_SOC_CONTROL_DEVICE_ID 0x0600
#define AM335_SOC_CONTROL_USB_CONTROL1 0x628
#define AM335_SOC_CONTROL_MAC_ID0_LOW 0x0630
#define AM335_SOC_CONTROL_MAC_ID0_HIGH 0x0634
#define AM335_SOC_CONTROL_MAC_ID1_LOW 0x0638
#define AM335_SOC_CONTROL_MAC_ID1_HIGH 0x063C
#define AM335_SOC_CONTROL_GMII_SEL 0x650
#define AM335_SOC_CONTROL_EFUSE_SMA 0x07FC
#define AM335_SOC_CONTROL_CONF_GPMC_AD0 0x800
#define AM335_SOC_CONTROL_CONF_GPMC_AD1 0x804
#define AM335_SOC_CONTROL_CONF_GPMC_AD2 0x808
#define AM335_SOC_CONTROL_CONF_GPMC_AD3 0x80C
#define AM335_SOC_CONTROL_CONF_GPMC_AD4 0x810
#define AM335_SOC_CONTROL_CONF_GPMC_AD5 0x814
#define AM335_SOC_CONTROL_CONF_GPMC_AD6 0x818
#define AM335_SOC_CONTROL_CONF_GPMC_AD7 0x81C
#define AM335_SOC_CONTROL_CONF_GPMC_CSN1 0x880
#define AM335_SOC_CONTROL_CONF_GPMC_CSN2 0x884
#define AM335_SOC_CONTROL_CONF_LCD_VSYNC 0x8E0
#define AM335_SOC_CONTROL_CONF_LCD_HSYNC 0x8E4
#define AM335_SOC_CONTROL_CONF_LCD_PCLK 0x8E8
#define AM335_SOC_CONTROL_CONF_LCD_AC_BIAS_EN 0x8EC
#define AM335_SOC_CONTROL_CONF_MMC0_DAT3 0x8F0
#define AM335_SOC_CONTROL_CONF_MMC0_DAT2 0x8F4
#define AM335_SOC_CONTROL_CONF_MMC0_DAT1 0x8F8
#define AM335_SOC_CONTROL_CONF_MMC0_DAT0 0x8FC
#define AM335_SOC_CONTROL_CONF_MMC0_CLK 0x900
#define AM335_SOC_CONTROL_CONF_MMC0_CMD 0x904
#define AM335_SOC_CONTROL_CONF_MII1_COL 0x908
#define AM335_SOC_CONTROL_CONF_MII1_CRS 0x90C
#define AM335_SOC_CONTROL_CONF_MII1_RXERR 0x910
#define AM335_SOC_CONTROL_CONF_MII1_TXEN 0x914
#define AM335_SOC_CONTROL_CONF_MII1_RXDV 0x918
#define AM335_SOC_CONTROL_CONF_MII1_TXD3 0x91C
#define AM335_SOC_CONTROL_CONF_MII1_TXD2 0x920
#define AM335_SOC_CONTROL_CONF_MII1_TXD1 0x924
#define AM335_SOC_CONTROL_CONF_MII1_TXD0 0x928
#define AM335_SOC_CONTROL_CONF_MII1_TXCLK 0x92C
#define AM335_SOC_CONTROL_CONF_MII1_RXCLK 0x930
#define AM335_SOC_CONTROL_CONF_MII1_RXD3 0x934
#define AM335_SOC_CONTROL_CONF_MII1_RXD2 0x938
#define AM335_SOC_CONTROL_CONF_MII1_RXD1 0x93C
#define AM335_SOC_CONTROL_CONF_MII1_RXD0 0x940
#define AM335_SOC_CONTROL_CONF_RMII1_REFCLK 0x944
#define AM335_SOC_CONTROL_CONF_MDIO_DATA 0x948
#define AM335_SOC_CONTROL_CONF_MDIO_CLK 0x94C
#define AM335_SOC_CONTROL_CONF_SPI0_CS1 0x960
#define AM335_SOC_CONTROL_I2C0_SDA 0x0988
#define AM335_SOC_CONTROL_I2C0_SCL 0x098C
#define AM335_SOC_CONTROL_CONF_XDMA_EVENT_INTR0 0x9B0
#define AM335_SOC_CONTROL_VTP_CONTROL 0x0E0C
#define AM335_SOC_CONTROL_DDR_IO_CONTROL 0x0E04
#define AM335_SOC_CONTROL_DDR_CKE_CONTROL 0x131C

//
// Define SoC control status register bits.
//

#define AM335_SOC_STATUS_SYSBOOT0_MASK 0x000000FF

//
// Define USB0/1 control register bits.
//

#define AM335_SOC_USB_CONTROL_SESSION_END_DETECT 0x00100000
#define AM335_SOC_USB_CONTROL_VBUS_DETECT 0x00080000
#define AM335_SOC_USB_CONTROL_OTG_PHY_POWER_DOWN 0x00000002
#define AM335_SOC_USB_CONTROL_CM_PHY_POWER_DOWN 0x00000001

//
// Define UART0 RXD pad control register bits.
//

#define AM335_SOC_CONTROL_UART0_RXD_PULLUP 0x00000010
#define AM335_SOC_CONTROL_UART0_RXD_RX_ACTIVE 0x00000020

//
// Define UART0 TXD pad control register bits.
//

#define AM335_SOC_CONTROL_UART0_TXD_PULLUP 0x00000010

//
// Generic SoC control pad configuration register bits.
//

#define AM335_SOC_CONF_MUX_MMODE_SHIFT 0
#define AM335_SOC_CONF_MUX_PUDEN_SHIFT 3
#define AM335_SOC_CONF_MUX_PUTYPESEL_SHIFT 4
#define AM335_SOC_CONF_MUX_RXACTIVE_SHIFT 5
#define AM335_SOC_CONF_MUX_SLEWCTRL_SHIFT 6

//
// SoC control VTP control register bits (used for DDR initialization).
//

#define AM335_SOC_CONTROL_VTP_CONTROL_CLRZ 0x00000001
#define AM335_SOC_CONTROL_VTP_CONTROL_READY 0x00000020
#define AM335_SOC_CONTROL_VTP_CONTROL_ENABLE 0x00000040

//
// Define GPIO registers.
//

#define AM335_GPIO_CONFIGURATION 0x010
#define AM335_GPIO_SYSTEM_STATUS 0x114
#define AM335_GPIO_CONTROL 0x130
#define AM335_GPIO_OUTPUT_ENABLE 0x134
#define AM335_GPIO_CLEAR_DATA_OUT 0x190
#define AM335_GPIO_SET_DATA_OUT 0x194

//
// Define GPIO system configuration register bits.
//

#define AM335_GPIO_CONFIGURATION_RESET_DONE 0x00000001
#define AM335_GPIO_CONFIGURATION_SOFT_RESET 0x00000002

//
// Define GPIO control register bits.
//

#define AM335_GPIO_CONTROL_DISABLE_MODULE 0x00000001

//
// Define AM335 timer register bits.
//

//
// Idle bits.
//

#define AM335_TIMER_IDLEMODE_NOIDLE 0x00000004
#define AM335_TIMER_IDLEMODE_SMART 0x00000008

//
// Mode bits.
//

#define AM335_TIMER_STARTED 0x00000001
#define AM335_TIMER_OVERFLOW_TRIGGER 0x00000400
#define AM335_TIMER_OVERFLOW_AND_MATCH_TRIGGER 0x00000800
#define AM335_TIMER_COMPARE_ENABLED 0x00000040
#define AM335_TIMER_AUTORELOAD 0x00000002

//
// Interrupt enable bits.
//

#define AM335_TIMER_MATCH_INTERRUPT 0x00000001
#define AM335_TIMER_OVERFLOW_INTERRUPT 0x00000002

#define AM335_TIMER_INTERRUPT_MASK 0x7

//
// Define AM335 interrupt controller register bits.
//

//
// Interrupt system configuration register bits.
//

#define AM335_INTC_SYSTEM_CONFIG_AUTO_IDLE 0x00000001
#define AM335_INTC_SYSTEM_CONFIG_SOFT_RESET 0x00000002

//
// Interrupt system status register bits.
//

#define AM335_INTC_SYSTEM_STATUS_RESET_DONE 0x00000001

//
// Interrupt sorted IRQ/FIQ register bits.
//

#define AM335_INTC_SORTED_ACTIVE_MASK 0x0000007F
#define AM335_INTC_SORTED_SPURIOUS 0x00000080

//
// Protection register bits.
//

#define AM335_INTC_PROTECTION_ENABLE 0x00000001

//
// Idle register bits.
//

#define AM335_INTC_IDLE_INPUT_AUTO_GATING 0x00000002

//
// Interrupt line register bits.
//

#define AM335_INTC_LINE_IRQ 0x00000000
#define AM335_INTC_LINE_FIQ 0x00000001
#define AM335_INTC_LINE_PRIORITY_SHIFT 2

//
// Interrupt control register bits.
//

#define AM335_INTC_CONTROL_NEW_IRQ_AGREEMENT 0x00000001
#define AM335_INTC_CONTROL_NEW_FIQ_AGREEMENT 0x00000002

//
// Define PRM Device registers.
//

#define AM335_PRM_DEVICE_RESET_CONTROL 0x00

//
// Define PRM Device Reset Control register bits.
//

#define AM335_PRM_DEVICE_RESET_CONTROL_WARM_RESET 0x00000001
#define AM335_PRM_DEVICE_RESET_CONTROL_COLD_RESET 0x00000002

//
// Define UART registers.
//

#define AM335_UART_RBR 0x00
#define AM335_UART_THR 0x00
#define AM335_UART_DLL 0x00
#define AM335_UART_IER 0x04
#define AM335_UART_DLM 0x04
#define AM335_UART_FCR 0x08
#define AM335_UART_IIR 0x08
#define AM335_UART_LCR 0x0C
#define AM335_UART_MCR 0x10
#define AM335_UART_LSR 0x14
#define AM335_UART_MSR 0x18
#define AM335_UART_SCR 0x1C
#define AM335_UART_MDR1 0x20
#define AM335_UART_SYSTEM_CONTROL 0x54
#define AM335_UART_SYSTEM_STATUS 0x58

//
// Define UART system control register bits.
//

#define AM335_UART_SYSTEM_CONTROL_RESET 0x00000002

//
// Define UART system status register bits.
//

#define AM335_UART_SYSTEM_STATUS_RESET_DONE 0x00000001

//
// SoC control definitions
//

#define AM335_SOC_CONTROL_SIZE 0x2000

//
// Define SoC control device ID register bits.
//

#define AM335_SOC_CONTROL_DEVICE_ID_REVISION_SHIFT 0x1C
#define AM335_SOC_DEVICE_VERSION_1_0 0
#define AM335_SOC_DEVICE_VERSION_2_0 1
#define AM335_SOC_DEVICE_VERSION_2_1 2

//
// EFuse bit for OPP100 275MHz, 1.1v.
//

#define AM335_EFUSE_OPP100_275_MASK 0x00000001
#define AM335_EFUSE_OPP100_275 0

//
// EFuse bit for OPP100 500MHz, 1.1v.
//

#define AM335_EFUSE_OPP100_500_MASK 0x00000002
#define AM335_EFUSE_OPP100_500 1

//
// EFuse bit for OPP100 600MHz, 1.2v.
//

#define AM335_EFUSE_OPP120_600_MASK 0x00000004
#define AM335_EFUSE_OPP120_600 2

//
// EFuse bit for OPP Turbo 720MHz, 1.26v.
//

#define AM335_EFUSE_OPPTB_720_MASK 0x00000008
#define AM335_EFUSE_OPPTB_720 3

//
// EFuse bit for OPP50 300MHz, 1.1v.
//

#define AM335_EFUSE_OPP50_300_MASK 0x00000010
#define AM335_EFUSE_OPP50_300 4

//
// EFuse bit for OPP100 300MHz, 1.1v.
//

#define AM335_EFUSE_OPP100_300_MASK 0x00000020
#define AM335_EFUSE_OPP100_300 5

//
// EFuse bit for OPP100 600MHz, 1.1v.
//

#define AM335_EFUSE_OPP100_600_MASK 0x00000040
#define AM335_EFUSE_OPP100_600 6

//
// EFuse bit for OPP120 700MHz, 1.2v.
//

#define AM335_EFUSE_OPP120_720_MASK 0x00000080
#define AM335_EFUSE_OPP120_720 7

//
// EFuse bit for OPP Turbo 800MHz, 1.26v.
//

#define AM335_EFUSE_OPPTB_800_MASK 0x00000100
#define AM335_EFUSE_OPPTB_800 8

//
// EFuse bit for OPP Turbo 1000MHz, 1.325v.
//

#define AM335_EFUSE_OPPNT_1000_MASK 0x00000200
#define AM335_EFUSE_OPPNT_1000 9
#define AM335_SOC_CONTROL_EFUSE_OPP_MASK 0x00001FFF
#define AM335_EFUSE_OPP_MAX (AM335_EFUSE_OPPNT_1000 + 1)

//
// Define types of OPP.
//

#define AM335_OPP_NONE 0
#define AM335_OPP50 1
#define AM335_OPP100 2
#define AM335_OPP120 3
#define AM335_OPP_SR_TURBO 4
#define AM335_OPP_NITRO 5

//
// MPU PLL configurations.
//

#define AM335_MPU_PLL_M_275MHZ 275
#define AM335_MPU_PLL_M_300MHZ 300
#define AM335_MPU_PLL_M_500MHZ 500
#define AM335_MPU_PLL_M_600MHZ 600
#define AM335_MPU_PLL_M_720MHZ 720
#define AM335_MPU_PLL_M_800MHZ 800
#define AM335_MPU_PLL_M_1000MHZ 1000

//
// Define PMIC voltage configurations.
//

#define AM335_PMIC_VOLTAGE_950MV TPS65217_DCDC_VOLTAGE_950MV
#define AM335_PMIC_VOLTAGE_1100MV TPS65217_DCDC_VOLTAGE_1100MV
#define AM335_PMIC_VOLTAGE_1200MV TPS65217_DCDC_VOLTAGE_1200MV
#define AM335_PMIC_VOLTAGE_1260MV TPS65217_DCDC_VOLTAGE_1275MV
#define AM335_PMIC_VOLTAGE_1325MV 0x11

//
// Define TPS65217 PMIC registers.
//

#define TPS65217_POWER_PATH 0x01
#define TPS65217_STATUS 0x0A
#define TPS65217_PASSWORD 0x0B
#define TPS65217_PGOOD 0x0C
#define TPS65217_DEFDCDC2 0x0F
#define TPS65217_DEFSLEW 0x11
#define TPS65217_DEFLS1 0x14
#define TPS65217_DEFLS2 0x15

//
// Define PMIC power path register bits.
//

#define TPS65217_POWER_PATH_USB_INPUT_CURRENT_LIMIT_MASK 0x03
#define TPS65217_POWER_PATH_USB_INPUT_CURRENT_LIMIT_100MA 0x00
#define TPS65217_POWER_PATH_USB_INPUT_CURRENT_LIMIT_500MA 0x01
#define TPS65217_POWER_PATH_USB_INPUT_CURRENT_LIMIT_1300MA 0x02
#define TPS65217_POWER_PATH_USB_INPUT_CURRENT_LIMIT_1800MA 0x03

#define TPS65217_DCDC_VOLTAGE_1275MV 0x0F
#define TPS65217_DCDC_VOLTAGE_1200MV 0x0C
#define TPS65217_DCDC_VOLTAGE_1100MV 0x08
#define TPS65217_DCDC_VOLTAGE_950MV 0x02

#define TPS65217_PROTECTION_NONE 0
#define TPS65217_PROTECTION_LEVEL_1 1
#define TPS65217_PROTECTION_LEVEL_2 2

#define TPS65217_PASSWORD_UNLOCK 0x7D
#define TPS65217_DCDC_GO 0x80

#define TPS65217_LDO_VOLTAGE_OUT_1_8 0x06
#define TPS65217_LDO_VOLTAGE_OUT_3_3 0x1F
#define TPS65217_LDO_MASK 0x1F

//
// Define DDR PHY control registers.
//

#define AM335_DDR_PHY_REGISTERS (AM335_SOC_CONTROL_REGISTERS + 0x2000)
#define AM335_DDR_CMD0_SLAVE_RATIO_0 (AM335_DDR_PHY_REGISTERS + 0x01C)
#define AM335_DDR_CMD0_SLAVE_FORCE_0 (AM335_DDR_PHY_REGISTERS + 0x020)
#define AM335_DDR_CMD0_SLAVE_DELAY_0 (AM335_DDR_PHY_REGISTERS + 0x024)
#define AM335_DDR_CMD0_LOCK_DIFF_0 (AM335_DDR_PHY_REGISTERS + 0x028)
#define AM335_DDR_CMD0_INVERT_CLKOUT_0 (AM335_DDR_PHY_REGISTERS + 0x02C)
#define AM335_DDR_CMD1_SLAVE_RATIO_0 (AM335_DDR_PHY_REGISTERS + 0x050)
#define AM335_DDR_CMD1_SLAVE_FORCE_0 (AM335_DDR_PHY_REGISTERS + 0x054)
#define AM335_DDR_CMD1_SLAVE_DELAY_0 (AM335_DDR_PHY_REGISTERS + 0x058)
#define AM335_DDR_CMD1_LOCK_DIFF_0 (AM335_DDR_PHY_REGISTERS + 0x5C)
#define AM335_DDR_CMD1_INVERT_CLKOUT_0 (AM335_DDR_PHY_REGISTERS + 0x060)
#define AM335_DDR_CMD2_SLAVE_RATIO_0 (AM335_DDR_PHY_REGISTERS + 0x084)
#define AM335_DDR_CMD2_SLAVE_FORCE_0 (AM335_DDR_PHY_REGISTERS + 0x088)
#define AM335_DDR_CMD2_SLAVE_DELAY_0 (AM335_DDR_PHY_REGISTERS + 0x08C)
#define AM335_DDR_CMD2_LOCK_DIFF_0 (AM335_DDR_PHY_REGISTERS + 0x090)
#define AM335_DDR_CMD2_INVERT_CLKOUT_0 (AM335_DDR_PHY_REGISTERS + 0x094)
#define AM335_DDR_DATA0_RD_DQS_SLAVE_RATIO_0 (AM335_DDR_PHY_REGISTERS + 0x0C8)
#define AM335_DDR_DATA0_RD_DQS_SLAVE_RATIO_1 (AM335_DDR_PHY_REGISTERS + 0x0CC)
#define AM335_DDR_DATA0_WR_DQS_SLAVE_RATIO_0 (AM335_DDR_PHY_REGISTERS + 0x0DC)
#define AM335_DDR_DATA0_WR_DQS_SLAVE_RATIO_1 (AM335_DDR_PHY_REGISTERS + 0x0E0)
#define AM335_DDR_DATA0_WRLVL_INIT_RATIO_0 (AM335_DDR_PHY_REGISTERS + 0x0F0)
#define AM335_DDR_DATA0_WRLVL_INIT_RATIO_1 (AM335_DDR_PHY_REGISTERS + 0x0F4)
#define AM335_DDR_DATA0_GATELVL_INIT_RATIO_0 (AM335_DDR_PHY_REGISTERS + 0x0FC)
#define AM335_DDR_DATA0_GATELVL_INIT_RATIO_1 (AM335_DDR_PHY_REGISTERS + 0x100)
#define AM335_DDR_DATA0_FIFO_WE_SLAVE_RATIO_0 (AM335_DDR_PHY_REGISTERS + 0x108)
#define AM335_DDR_DATA0_FIFO_WE_SLAVE_RATIO_1 (AM335_DDR_PHY_REGISTERS + 0x10C)
#define AM335_DDR_DATA0_WR_DATA_SLAVE_RATIO_0 (AM335_DDR_PHY_REGISTERS + 0x120)
#define AM335_DDR_DATA0_WR_DATA_SLAVE_RATIO_1 (AM335_DDR_PHY_REGISTERS + 0x124)
#define AM335_DDR_DATA0_USE_RANK0_DELAYS_0 (AM335_DDR_PHY_REGISTERS + 0x134)
#define AM335_DDR_DATA0_LOCK_DIFF_0 (AM335_DDR_PHY_REGISTERS + 0x138)
#define AM335_DDR_DATA1_RD_DQS_SLAVE_RATIO_0 (AM335_DDR_PHY_REGISTERS + 0x16C)
#define AM335_DDR_DATA1_RD_DQS_SLAVE_RATIO_1 (AM335_DDR_PHY_REGISTERS + 0x170)
#define AM335_DDR_DATA1_WR_DQS_SLAVE_RATIO_0 (AM335_DDR_PHY_REGISTERS + 0x180)
#define AM335_DDR_DATA1_WR_DQS_SLAVE_RATIO_1 (AM335_DDR_PHY_REGISTERS + 0x184)
#define AM335_DDR_DATA1_WRLVL_INIT_RATIO_0 (AM335_DDR_PHY_REGISTERS + 0x194)
#define AM335_DDR_DATA1_WRLVL_INIT_RATIO_1 (AM335_DDR_PHY_REGISTERS + 0x198)
#define AM335_DDR_DATA1_GATELVL_INIT_RATIO_0 (AM335_DDR_PHY_REGISTERS + 0x1A0)
#define AM335_DDR_DATA1_GATELVL_INIT_RATIO_1 (AM335_DDR_PHY_REGISTERS + 0x1A4)
#define AM335_DDR_DATA1_FIFO_WE_SLAVE_RATIO_0 (AM335_DDR_PHY_REGISTERS + 0x1AC)
#define AM335_DDR_DATA1_FIFO_WE_SLAVE_RATIO_1 (AM335_DDR_PHY_REGISTERS + 0x1B0)
#define AM335_DDR_DATA1_WR_DATA_SLAVE_RATIO_0 (AM335_DDR_PHY_REGISTERS + 0x1C4)
#define AM335_DDR_DATA1_WR_DATA_SLAVE_RATIO_1 (AM335_DDR_PHY_REGISTERS + 0x1C8)
#define AM335_DDR_DATA1_USE_RANK0_DELAYS_0 (AM335_DDR_PHY_REGISTERS + 0x1D8)
#define AM335_DDR_DATA1_LOCK_DIFF_0 (AM335_DDR_PHY_REGISTERS + 0x1DC)

//
// Define DDR3 parameters. These are specific to the BeagleBone Black, and
// there needs to be a different set for the BeagleBone (white).
//

#define AM335_DDR3_CMD0_SLAVE_RATIO_0 0x80
#define AM335_DDR3_CMD0_INVERT_CLKOUT_0 0x0
#define AM335_DDR3_CMD1_SLAVE_RATIO_0 0x80
#define AM335_DDR3_CMD1_INVERT_CLKOUT_0 0x0
#define AM335_DDR3_CMD2_SLAVE_RATIO_0 0x80
#define AM335_DDR3_CMD2_INVERT_CLKOUT_0 0x0

#define AM335_DDR3_DATA0_RD_DQS_SLAVE_RATIO_0 0x38
#define AM335_DDR3_DATA0_WR_DQS_SLAVE_RATIO_0 0x44
#define AM335_DDR3_DATA0_FIFO_WE_SLAVE_RATIO_0 0x94
#define AM335_DDR3_DATA0_WR_DATA_SLAVE_RATIO_0 0x7D

#define AM335_DDR3_DATA0_RD_DQS_SLAVE_RATIO_1 0x38
#define AM335_DDR3_DATA0_WR_DQS_SLAVE_RATIO_1 0x44
#define AM335_DDR3_DATA0_FIFO_WE_SLAVE_RATIO_1 0x94
#define AM335_DDR3_DATA0_WR_DATA_SLAVE_RATIO_1 0x7D

#define AM335_DDR3_CONTROL_DDR_CMD_IOCTRL_0 0x18B
#define AM335_DDR3_CONTROL_DDR_CMD_IOCTRL_1 0x18B
#define AM335_DDR3_CONTROL_DDR_CMD_IOCTRL_2 0x18B

#define AM335_DDR3_CONTROL_DDR_DATA_IOCTRL_0 0x18B
#define AM335_DDR3_CONTROL_DDR_DATA_IOCTRL_1 0x18B

#define AM335_DDR3_CONTROL_DDR_IO_CTRL 0xEFFFFFFF

#define AM335_DDR3_EMIF_DDR_PHY_CTRL_1 0x06
#define AM335_DDR3_EMIF_DDR_PHY_CTRL_1_DY_PWRDN 0x00100000
#define AM335_DDR3_EMIF_DDR_PHY_CTRL_1_SHDW 0x06
#define AM335_DDR3_EMIF_DDR_PHY_CTRL_1_SHDW_DY_PWRDN 0x00100000
#define AM335_DDR3_EMIF_DDR_PHY_CTRL_2 0x06

#define AM335_DDR3_EMIF_SDRAM_TIM_1 0x0AAAD4DB
#define AM335_DDR3_EMIF_SDRAM_TIM_1_SHDW 0x0AAAD4DB

#define AM335_DDR3_EMIF_SDRAM_TIM_2 0x266B7FDA
#define AM335_DDR3_EMIF_SDRAM_TIM_2_SHDW 0x266B7FDA

#define AM335_DDR3_EMIF_SDRAM_TIM_3 0x501F867F
#define AM335_DDR3_EMIF_SDRAM_TIM_3_SHDW 0x501F867F

#define AM335_DDR3_EMIF_SDRAM_REF_CTRL_VAL1 0x00000C30
#define AM335_DDR3_EMIF_SDRAM_REF_CTRL_SHDW_VAL1 0x00000C30

#define AM335_DDR3_EMIF_ZQ_CONFIG_VAL 0x50074BE4

//
// Termination = 1 RZQ / 4
// Dynamic ODT = 2 RZQ / 2
// SDRAM Drive = 0 RZQ / 6
// CWL = 0 CAS write latency of 5
// CL = 2 CAS latency of 5
// Row Size = 7 16 row bits
// Page Size = 2 10 column bits
//

#define AM335_DDR3_EMIF_SDRAM_CONFIG 0x61C04BB2

//
// CM Wakeup MPU PLL clock mode register bits.
//

#define AM335_CM_WAKEUP_CLOCK_MODE_DPLL_MPU_ENABLE_MN_BYPASS 0x00000004
#define AM335_CM_WAKEUP_CLOCK_MODE_DPLL_MPU_ENABLE 0x00000007

//
// CM Wakeup MPU PLL idle status register bits.
//

#define AM335_CM_WAKEUP_IDLE_STATUS_DPLL_MPU_CLOCK 0x00000001
#define AM335_CM_WAKEUP_IDLE_STATUS_DPLL_MPU_MN_BYPASS 0x00000100

//
// CM Wakeup MPU PLL clock select register bits.
//

#define AM335_CM_WAKEUP_CLOCK_SELECT_DPLL_MPU_DIV_MASK 0x0000007F
#define AM335_CM_WAKEUP_CLOCK_SELECT_DPLL_MPU_DIV_SHIFT 0
#define AM335_CM_WAKEUP_CLOCK_SELECT_DPLL_MPU_MULT_MASK 0x0007FF00
#define AM335_CM_WAKEUP_CLOCK_SELECT_DPLL_MPU_MULT_SHIFT 8

//
// CM Wakeup MPU PLL M2 divisor register bits.
//

#define AM335_CM_WAKEUP_DIV_M2_DPLL_MPU_CLOCK_OUT_MASK 0x0000001F

//
// CM Wakeup Display PLL clock mode register bits.
//

#define AM335_CM_WAKEUP_CLOCK_MODE_DPLL_DISP_ENABLE_MN_BYPASS 0x00000004
#define AM335_CM_WAKEUP_CLOCK_MODE_DPLL_DISP_ENABLE 0x0000007

//
// CM Wakeup DCO LDO Peripheral DPLL register bits.
//

#define AM335_CM_WAKEUP_DCO_LDO_PER_DPLL_GATE_CONTROL 0x00000100

//
// CM Wakeup Display PLL idle status register bits.
//

#define AM335_CM_WAKEUP_IDLE_STATUS_DPLL_DISP_MN_BYPASS 0x00000100
#define AM335_CM_WAKEUP_IDLE_STATUS_DPLL_DISP_CLOCK 0x00000001

//
// CM Wakeup Display PLL clock select register bits.
//

#define AM335_CM_WAKEUP_CLOCK_SELECT_DPLL_DISP_DIV_MASK 0x0000007F
#define AM335_CM_WAKEUP_CLOCK_SELECT_DPLL_DISP_DIV_SHIFT 0
#define AM335_CM_WAKEUP_CLOCK_SELECT_DPLL_DISP_MULT_MASK 0x0007FF00
#define AM335_CM_WAKEUP_CLOCK_SELECT_DPLL_DISP_MULT_SHIFT 8

//
// CM Wakeup Display PLL M2 divider register bits.
//

#define AM335_CM_WAKEUP_DIV_M2_DPLL_DISP_CLOCK_OUT_MASK 0x0000001F

//
// Hardcoded PLL values.
//

#define AM335_MPU_PLL_N 23
#define AM335_MPU_PLL_M2 1

#define AM335_CORE_PLL_M 1000
#define AM335_CORE_PLL_N 23
#define AM335_CORE_PLL_HSDIVIDER_M4 10
#define AM335_CORE_PLL_HSDIVIDER_M5 8
#define AM335_CORE_PLL_HSDIVIDER_M6 4

#define AM335_PER_PLL_M 960
#define AM335_PER_PLL_N 23
#define AM335_PER_PLL_M2 5

#define AM335_DDR_PLL_M_DDR2 266
#define AM335_DDR_PLL_M_DDR3 303
#define AM335_DDR_PLL_N 23
#define AM335_DDR_PLL_M2 1

#define AM335_DISP_PLL_M 25
#define AM335_DISP_PLL_N 2
#define AM335_DISP_PLL_M2 1

//
// Define PRM wake up reset control register bits.
//

#define AM335_RM_WAKEUP_RESET_CONTROL_RESET_CORTEX_M3 (1 << 3)

//
// Define SOC Control M3 TXEV End of interrupt bits.
//

#define AM335_CONTROL_M3_TXEV_EOI_ENABLE 0x00000000
#define AM335_CONTROL_M3_TXEV_EOI 0x00000001

//
// Define the size of the entire USB subsystem region.
//

#define AM335_USB_REGION_SIZE 0x8000

//
// Define register offsets within the USB subsystem.
//

#define AM3_USB_USBSS_OFFSET 0x0000
#define AM3_USB_USB0_OFFSET 0x1000
#define AM3_USB_USB0_PHY_OFFSET 0x1300
#define AM3_USB_USB0_CORE_OFFSET 0x1400
#define AM3_USB_USB1_OFFSET 0x1800
#define AM3_USB_USB1_PHY_OFFSET 0x1B00
#define AM3_USB_USB1_CORE_OFFSET 0x1C00
#define AM3_USB_CPPI_DMA_OFFSET 0x2000
#define AM3_USB_CPPI_DMA_SCHEDULER_OFFSET 0x3000

//
// USBSS sysconfig register bits
//

#define AM335_USBSS_SYSCONFIG_SOFT_RESET 0x00000001

//
// Define EMIF power control registers.
//

#define AM335_EMIF_POWER_CONTROL_SELF_REFRESH_64 (0x3 << 4)
#define AM335_EMIF_POWER_CONTROL_SELF_REFRESH_8192 (0xA << 4)
#define AM335_EMIF_POWER_CONTROL_CLOCK_STOP (0x1 << 8)
#define AM335_EMIF_POWER_CONTROL_SELF_REFRESH (0x2 << 8)
#define AM335_EMIF_POWER_CONTROL_POWER_DOWN (0x4 << 8)

//
// LCD controller registers.
//

#define AM335_LCD_CONTROL 0x04
#define AM335_LCD_STATUS 0x08
#define AM335_LCD_LIDD_CONTROL 0x0C
#define AM335_LCD_LIDD_CS0_CONF 0x10
#define AM335_LCD_LIDD_CS0_ADDR 0x14
#define AM335_LCD_LIDD_CS0_DATA 0x18
#define AM335_LCD_LIDD_CS1_CONF 0x1C
#define AM335_LCD_LIDD_CS1_ADDR 0x20
#define AM335_LCD_LIDD_CS1_DATA 0x24
#define AM335_LCD_RASTER_CONTROL 0x28
#define AM335_LCD_RASTER_TIMING_0 0x2C
#define AM335_LCD_RASTER_TIMING_1 0x30
#define AM335_LCD_RASTER_TIMING_2 0x34
#define AM335_LCD_SUBPANEL 0x38
#define AM335_LCD_SUBPANEL2 0x3C
#define AM335_LCD_DMA_CONTROL 0x40
#define AM335_LCD_FB0_BASE 0x44
#define AM335_LCD_FB0_CEILING 0x48
#define AM335_LCD_FB1_BASE 0x4C
#define AM335_LCD_FB1_CEILING 0x50
#define AM335_LCD_SYSTEM_CONFIG 0x54
#define AM335_LCD_IRQSTATUS_RAW 0x58
#define AM335_LCD_IRQSTATUS 0x5C
#define AM335_LCD_IRQENABLE_SET 0x60
#define AM335_LCD_IRQENABLE_CLEAR 0x64
#define AM335_LCD_IRQEOI_VECTOR 0x68
#define AM335_LCD_CLOCK_ENABLE 0x6C
#define AM335_LCD_CLOCK_RESET 0x70

//
// LCD clock enable register bits.
//

#define AM335_LCD_CLOCK_ENABLE_CORE 0x00000001
#define AM335_LCD_CLOCK_ENABLE_LIDD 0x00000002
#define AM335_LCD_CLOCK_ENABLE_DMA 0x00000004

//
// LCD raster control register bits.
//

#define AM335_LCD_RASTER_CONTROL_ENABLE 0x00000001
#define AM335_LCD_RASTER_CONTROL_TFT 0x00000080
#define AM335_LCD_RASTER_CONTROL_FIFO_DMA_DELAY_MASK 0x000FF000
#define AM335_LCD_RASTER_CONTROL_FIFO_DMA_DELAY_SHIFT 12
#define AM335_LCD_RASTER_CONTROL_PALETTE_LOAD_MASK 0x00300000
#define AM335_LCD_RASTER_CONTROL_PALETTE_LOAD_DATA_ONLY 0x00200000
#define AM335_LCD_RASTER_CONTROL_TFT24 0x02000000
#define AM335_LCD_RASTER_CONTROL_TFT24_UNPACKED 0x04000000

//
// LCD control register bits.
//

#define AM335_LCD_CONTROL_RASTER_MODE 0x00000001
#define AM335_LCD_CONTROL_DIVISOR_SHIFT 8

//
// LCD DMA control register bits.
//

#define AM335_LCD_DMA_BURST_SIZE_16 (0x4 << 4)
#define AM335_LCD_DMA_FIFO_THRESHOLD_8 (0x0 << 8)

//
// General LCD timing definitions.
//

#define AM335_LCD_RASTER_TIMING_PORCH_LOW_MASK 0xFF
#define AM335_LCD_RASTER_TIMING_PORCH_HIGH_SHIFT 8
#define AM335_LCD_RASTER_TIMING_PORCH_HIGH_MASK 0x3
#define AM335_LCD_RASTER_TIMING_HSYNC_HIGH_SHIFT 6
#define AM335_LCD_RASTER_TIMING_HSYNC_HIGH_MASK 0xF

//
// LCD timing 0 register bits.
//

#define AM335_LCD_RASTER_TIMING_0_HSYNC_SHIFT 10
#define AM335_LCD_RASTER_TIMING_0_HORIZONTAL_FRONT_PORCH_SHIFT 16
#define AM335_LCD_RASTER_TIMING_0_HORIZONTAL_BACK_PORCH_SHIFT 24
#define AM335_LCD_RASTER_TIMING_0_HSYNC_MASK 0x3F

//
// LCD timing 1 register bits.
//

#define AM335_LCD_RASTER_TIMING_1_VSYNC_SHIFT 10
#define AM335_LCD_RASTER_TIMING_1_VERTICAL_FRONT_PORCH_SHIFT 16
#define AM335_LCD_RASTER_TIMING_1_VERTICAL_BACK_PORCH_SHIFT 24

//
// LCD Raster timing 2 register bits.
//

#define AM335_LCD_RASTER_TIMING_2_INVERT_VERTICAL_SYNC 0x00100000
#define AM335_LCD_RASTER_TIMING_2_INVERT_HORIZONTAL_SYNC 0x00200000
#define AM335_LCD_RASTER_TIMING_2_SYNC_CONTROL 0x02000000
#define AM335_LCD_RASTER_TIMING_2_AC_BIAS_FREQUENCY_SHIFT 8
#define AM335_LCD_RASTER_TIMING_2_LINES_PER_PANEL_BIT_10_SHIFT 26
#define AM335_LCD_RASTER_TIMING_2_LINES_PER_PANEL_BIT_10 0x04000000
#define AM335_LCD_RASTER_TIMING_2_HORIZONTAL_FRONT_PORCH_HIGH_SHIFT 0
#define AM335_LCD_RASTER_TIMING_2_HORIZONTAL_BACK_PORCH_HIGH_SHIFT 4
#define AM335_LCD_RASTER_TIMING_2_HORIZONTAL_SYNC_HIGH_SHIFT 27

//
// LCD system configuration register bits.
//

#define AM335_LCD_SYSTEM_CONFIG_STANDBY_SMART (0x2 << 4)
#define AM335_LCD_SYSTEM_CONFIG_IDLE_SMART (0x2 << 2)

//
// LCD clock reset register bits.
//

#define AM335_LCD_CLOCK_RESET_MAIN 0x00000008

//
// Define Ethernet PORT register offsets.
//

#define AM335_CPSW_PORT_REGISTERS 0x4A100100
#define AM335_CPSW_PORT1_SOURCE_ADDRESS_LOW 0x120
#define AM335_CPSW_PORT1_SOURCE_ADDRESS_HIGH 0x124
#define AM335_CPSW_PORT2_SOURCE_ADDRESS_LOW 0x220
#define AM335_CPSW_PORT2_SOURCE_ADDRESS_HIGH 0x224

//
// Define RTC control register bits.
//

#define AM335_RTC_CONTROL_RUN 0x00000001
#define AM335_RTC_CONTROL_ROUND_30S 0x00000002
#define AM335_RTC_CONTROL_AUTO_COMPENSATION 0x00000004
#define AM335_RTC_CONTROL_12_HOUR_MODE 0x00000008
#define AM335_RTC_CONTROL_TEST_MODE 0x00000010
#define AM335_RTC_CONTROL_SET_32_MOUNTER 0x00000020
#define AM335_RTC_CONTROL_RTC_DISABLE 0x00000040

//
// Define RTC status register bits.
//

#define AM335_RTC_STATUS_BUSY 0x00000001
#define AM335_RTC_STATUS_RUN 0x00000002
#define AM335_RTC_STATUS_SECOND_EVENT 0x00000004
#define AM335_RTC_STATUS_MINUTE_EVENT 0x00000008
#define AM335_RTC_STATUS_HOUR_EVENT 0x00000010
#define AM335_RTC_STATUS_DAY_EVENT 0x00000020
#define AM335_RTC_STATUS_ALARM 0x00000040
#define AM335_RTC_STATUS_ALARM2 0x00000080

//
// Define RTC interrupt enable bits.
//

#define AM335_RTC_INTERRUPT_EVERY_SECOND 0x0
#define AM335_RTC_INTERRUPT_EVERY_MINUTE 0x1
#define AM335_RTC_INTERRUPT_EVERY_HOUR 0x2
#define AM335_RTC_INTERRUPT_EVERY_DAY 0x3
#define AM335_RTC_INTERRUPT_EVERY_MASK 0x3
#define AM335_RTC_INTERRUPT_TIMER 0x00000004
#define AM335_RTC_INTERRUPT_ALARM 0x00000008
#define AM335_RTC_INTERRUPT_ALARM2 0x00000010

#define AM335_RTC_HOURS_PM 0x80

//
// Define RTC system configuration register bits.
//

#define AM335_RTC_SYS_CONFIG_IDLE_MODE_FORCE_IDLE 0x0
#define AM335_RTC_SYS_CONFIG_IDLE_MODE_NO_IDLE 0x1
#define AM335_RTC_SYS_CONFIG_IDLE_MODE_SMART 0x2
#define AM335_RTC_SYS_CONFIG_IDLE_MODE_SMART_WAKEUP 0x3

//
// Define the kick values to write to enable write access to the RTC.
//

#define AM335_RTC_KICK0_KEY 0x83E70B13
#define AM335_RTC_KICK1_KEY 0x95A4F1E0

//
// Define RTC oscillator register bits.
//

#define AM335_RTC_OSCILLATOR_SW1 0x00000001
#define AM335_RTC_OSCILLATOR_SW2 0x00000002
#define AM335_RTC_OSCILLATOR_EXTERNAL_RESISTOR 0x00000004
#define AM335_RTC_OSCILLATOR_SOURCE_EXTERNAL 0x00000008
#define AM335_RTC_OSCILLATOR_DISABLE_OSCILLATOR 0x00000010
#define AM335_RTC_OSCILLATOR_ENABLE 0x00000040

#define AM335_WATCHDOG_FREQUENCY 32768

//
// Define the number of 32kHz clock ticks per interrupt. A value of 512 creates
// a timer rate of 15.625ms, or about 64 interrupts per second.
//

#define BEAGLEBONE_TIMER_TICK_COUNT 512

//
// Idle bits.
//

#define AM335_TIMER_IDLEMODE_NOIDLE 0x00000004
#define AM335_TIMER_IDLEMODE_SMART 0x00000008

//
// Mode bits.
//

#define AM335_TIMER_STARTED 0x00000001
#define AM335_TIMER_OVERFLOW_TRIGGER 0x00000400
#define AM335_TIMER_OVERFLOW_AND_MATCH_TRIGGER 0x00000800
#define AM335_TIMER_COMPARE_ENABLED 0x00000040
#define AM335_TIMER_AUTORELOAD 0x00000002

//
// Interrupt enable bits.
//

#define AM335_TIMER_MATCH_INTERRUPT 0x00000001
#define AM335_TIMER_OVERFLOW_INTERRUPT 0x00000002

#define AM335_TIMER_INTERRUPT_MASK 0x7

//
// Define the two step sequence needed for disabling or enabling the watchdog
// timer.
//

#define AM335_WATCHDOG_DISABLE1 0x0000AAAA
#define AM335_WATCHDOG_DISABLE2 0x00005555
#define AM335_WATCHDOG_ENABLE1  0x0000BBBB
#define AM335_WATCHDOG_ENABLE2  0x00004444

#define AM335_WATCHDOG_INTERRUPT_OVERFLOW 0x00000001
#define AM335_WATCHDOG_INTERRUPT_DELAY 0x00000002

//
// I2C system status register bits.
//

#define AM335_I2C_SYSTEM_STATUS_RESET_DONE 0x00000001

//
// Define the I2C slave address of the TPS65217 PMIC.
//

#define AM335_TPS65217_I2C_ADDRESS 0x24

//
// Define I2C control register bits.
//

#define AM335_I2C_CONTROL_START (1 << 0)
#define AM335_I2C_CONTROL_STOP (1 << 1)
#define AM335_I2C_CONTROL_EXPAND_OWN_ADDRESS_3 (1 << 4)
#define AM335_I2C_CONTROL_EXPAND_OWN_ADDRESS_2 (1 << 5)
#define AM335_I2C_CONTROL_EXPAND_OWN_ADDRESS_1 (1 << 6)
#define AM335_I2C_CONTROL_EXPAND_OWN_ADDRESS_0 (1 << 7)
#define AM335_I2C_CONTROL_EXPAND_SLAVE_ADDRESS (1 << 8)
#define AM335_I2C_CONTROL_TRANSMIT (1 << 9)
#define AM335_I2C_CONTROL_MASTER (1 << 10)
#define AM335_I2C_CONTROL_START_BYTE_MODE (1 << 11)
#define AM335_I2C_CONTROL_ENABLE (1 << 15)

//
// I2C system control register bits.
//

#define AM335_I2C_SYSTEM_CONTROL_AUTO_IDLE 0x00000001
#define AM335_I2C_SYSTEM_CONTROL_SOFT_RESET 0x00000002

//
// Define I2C buffer (FIFO) control bits.
//

#define AM335_I2C_BUFFER_TX_THRESHOLD_SHIFT 0
#define AM335_I2C_BUFFER_TX_FIFO_CLEAR (1 << 6)
#define AM335_I2C_BUFFER_TX_DMA_ENABLE (1 << 7)
#define AM335_I2C_BUFFER_RX_THRESHOLD_SHIFT 8
#define AM335_I2C_BUFFER_RX_FIFO_CLEAR (1 << 14)
#define AM335_I2C_BUFFER_RX_DMA_ENABLE (1 << 15)

//
// Define buffer status register bits.
//

#define AM335_I2C_BUFFER_STATUS_TX_MASK (0x3F << 0)
#define AM335_I2C_BUFFER_STATUS_TX_SHIFT 0
#define AM335_I2C_BUFFER_STATUS_RX_MASK (0x3F << 8)
#define AM335_I2C_BUFFER_STATUS_RX_SHIFT 8
#define AM335_I2C_BUFFER_STATUS_DEPTH_8 (0x0 << 14)
#define AM335_I2C_BUFFER_STATUS_DEPTH_16 (0x1 << 14)
#define AM335_I2C_BUFFER_STATUS_DEPTH_32 (0x2 << 14)
#define AM335_I2C_BUFFER_STATUS_DEPTH_64 (0x3 << 14)
#define AM335_I2C_BUFFER_STATUS_DEPTH_MASK (0x3 << 14)

#define AM335_I2C_MAX_FIFO_DEPTH 64

//
// Define I2C interrupt status/enable register bits.
//

#define AM335_I2C_INTERRUPT_ARBITRATION_LOST 0x00000001
#define AM335_I2C_INTERRUPT_NACK 0x00000002
#define AM335_I2C_INTERRUPT_ACCESS_READY 0x00000004
#define AM335_I2C_INTERRUPT_RX_READY 0x00000008
#define AM335_I2C_INTERRUPT_TX_READY 0x00000010
#define AM335_I2C_INTERRUPT_GENERAL_CALL 0x00000020
#define AM335_I2C_INTERRUPT_START 0x00000040
#define AM335_I2C_INTERRUPT_ACCESS_ERROR 0x00000080
#define AM335_I2C_INTERRUPT_BUS_FREE 0x00000100
#define AM335_I2C_INTERRUPT_ADDRESS_RECOGNIZED 0x00000200
#define AM335_I2C_INTERRUPT_TX_UNDERFLOW 0x00000400
#define AM335_I2C_INTERRUPT_RX_OVERFLOW 0x00000800
#define AM335_I2C_INTERRUPT_BUS_BUSY 0x00001000
#define AM335_I2C_INTERRUPT_RX_DRAIN 0x00002000
#define AM335_I2C_INTERRUPT_TX_DRAIN 0x00004000

#define AM335_I2C_INTERRUPT_ERROR_MASK \
    (AM335_I2C_INTERRUPT_ACCESS_ERROR | AM335_I2C_INTERRUPT_RX_OVERFLOW)

#define AM335_I2C_INTERRUPT_DEFAULT_MASK \
    (AM335_I2C_INTERRUPT_NACK | AM335_I2C_INTERRUPT_ACCESS_ERROR)

#define AM335_I2C_INTERRUPT_STATUS_MASK 0x000007FF

//
// Define internal I2C parameters (recommended convention).
//

#define AM335_I2C_SYSTEM_CLOCK_SPEED 48000000
#define AM335_I2C_INTERNAL_CLOCK_SPEED 12000000
#define AM335_I2C_OUTPUT_CLOCK_SPEED 100000

//
// ------------------------------------------------------ Data Type Definitions
//

//
// Define the DM timer register offsets.
//

typedef enum _AM335_DM_TIMER_REGISTER {
    Am335TimerId                            = 0x00,
    Am335TimerOcpConfig                     = 0x10,
    Am335TimerEndOfInterrupt                = 0x14,
    Am335TimerRawInterruptStatus            = 0x24,
    Am335TimerInterruptStatus               = 0x28,
    Am335TimerInterruptEnableSet            = 0x2C,
    Am335TimerInterruptEnableClear          = 0x30,
    Am335TimerInterruptWakeEnable           = 0x34,
    Am335TimerControl                       = 0x38,
    Am335TimerCount                         = 0x3C,
    Am335TimerLoad                          = 0x40,
    Am335TimerTrigger                       = 0x44,
    Am335TimerWritePosting                  = 0x48,
    Am335TimerMatch                         = 0x4C,
    Am335TimerCapture1                      = 0x50,
    Am335TimerSynchronousInterfaceControl   = 0x54,
    Am335TimerCapture2                      = 0x58
} AM335_DM_TIMER_REGISTER, *PAM335_DM_TIMER_REGISTER;

//
// Define INTC register offsets.
//

typedef enum _AM335_INTC_REGISTER {
    Am335IntcRevision                       = 0x000,
    Am335IntcSystemConfig                   = 0x010,
    Am335IntcSystemStatus                   = 0x014,
    Am335IntcSortedIrq                      = 0x040,
    Am335IntcSortedFiq                      = 0x044,
    Am335IntcControl                        = 0x048,
    Am335IntcProtection                     = 0x04C,
    Am335IntcIdle                           = 0x050,
    Am335IntcIrqPriority                    = 0x060,
    Am335IntcFiqPriority                    = 0x064,
    Am335IntcThreshold                      = 0x068,
    Am335IntcMask                           = 0x084,
    Am335IntcMaskClear                      = 0x088,
    Am335IntcMaskSet                        = 0x08C,
    Am335IntcLine                           = 0x100,
} AM335_INTC_REGISTER, *PAM335_INTC_REGISTER;

//
// Define the watchdog timer registers, offsets in bytes.
//

typedef enum _AM335_WATCHDOG_REGISTER {
    Am335WatchdogRevision               = 0x00,
    Am335WatchdogInterfaceConfiguration = 0x10,
    Am335WatchdogInterfaceStatus        = 0x14,
    Am335WatchdogInterruptStatus        = 0x18,
    Am335WatchdogInterruptEnable        = 0x1C,
    Am335WatchdogWakeEventEnable        = 0x20,
    Am335WatchdogPrescaler              = 0x24,
    Am335WatchdogCurrentCount           = 0x28,
    Am335WatchdogLoadCount              = 0x2C,
    Am335WatchdogTrigger                = 0x30,
    Am335WatchdogWritePostStatus        = 0x34,
    Am335WatchdogDelay                  = 0x44,
    Am335WatchdogStartStop              = 0x48,
    Am335WatchdogRawInterruptStatus     = 0x54,
    Am335WatchdogInterruptEnableSet     = 0x5C,
    Am335WatchdogInterruptEnableClear   = 0x60,
    Am335WatchdogWakeEnable             = 0x64
} AM335_WATCHDOG_REGISTER, *PAM335_WATCHDOG_REGISTER;

typedef enum _AM335_RTC_REGISTER {
    Am335RtcSeconds = 0x00,
    Am335RtcMinutes = 0x04,
    Am335RtcHours = 0x08,
    Am335RtcDays = 0x0C,
    Am335RtcMonths = 0x10,
    Am335RtcYears = 0x14,
    Am335RtcWeekdays = 0x18,
    Am335RtcAlarmSeconds = 0x20,
    Am335RtcAlarmMinutes = 0x24,
    Am335RtcAlarmHours = 0x28,
    Am335RtcAlarmDays = 0x2C,
    Am335RtcAlarmMonths = 0x30,
    Am335RtcAlarmYears = 0x34,
    Am335RtcControl = 0x40,
    Am335RtcStatus = 0x44,
    Am335RtcInterruptEnable = 0x48,
    Am335RtcCompensationLow = 0x4C,
    Am335RtcCompensationHigh = 0x50,
    Am335RtcOscillator = 0x54,
    Am335RtcScratch0 = 0x60,
    Am335RtcScratch1 = 0x64,
    Am335RtcScratch2 = 0x68,
    Am335RtcKick0 = 0x6C,
    Am335RtcKick1 = 0x70,
    Am335RtcRevision = 0x74,
    Am335RtcSysConfig = 0x78,
    Am335RtcWakeEnable = 0x7C,
    Am335RtcAlarm2Seconds = 0x80,
    Am335RtcAlarm2Minutes = 0x84,
    Am335RtcAlarm2Hours = 0x88,
    Am335RtcAlarm2Days = 0x8C,
    Am335RtcAlarm2Months = 0x90,
    Am335RtcAlarm2Years = 0x94,
    Am335RtcPmic = 0x98,
    Am335RtcDebounce = 0x9C
} AM335_RTC_REGISTER, *PAM335_RTC_REGISTER;

typedef enum _AM335_I2C_REGISTER {
    Am3I2cRevisionLow = 0x00,
    Am3I2cRevisionHigh = 0x04,
    Am3I2cSysControl = 0x10,
    Am3I2cInterruptStatusRaw = 0x24,
    Am3I2cInterruptStatus = 0x28,
    Am3I2cInterruptEnableSet = 0x2C,
    Am3I2cInterruptEnableClear = 0x30,
    Am3I2cWakeEnable = 0x34,
    Am3I2cDmaRxEnableSet = 0x38,
    Am3I2cDmaTxEnableSet = 0x3C,
    Am3I2cDmaRxEnableClear = 0x40,
    Am3I2cDmaTxEnableClear = 0x44,
    Am3I2cDmaRxWakeEnable = 0x48,
    Am3I2cDmaTxWakeEnable = 0x4C,
    Am3I2cSysStatus = 0x90,
    Am3I2cBuffer = 0x94,
    Am3I2cCount = 0x98,
    Am3I2cData = 0x9C,
    Am3I2cControl = 0xA4,
    Am3I2cOwnAddress = 0xA8,
    Am3I2cSlaveAddress = 0xAC,
    Am3I2cPrescale = 0xB0,
    Am3I2cSclLowTime = 0xB4,
    Am3I2cSclHighTime = 0xB8,
    Am3I2cSysTest = 0xBC,
    Am3I2cBufferStatus = 0xC0,
    Am3I2cOwnAddress1 = 0xC4,
    Am3I2cOwnAddress2 = 0xC8,
    Am3I2cOwnAddress3 = 0xCC,
    Am3I2cActiveOwnAddress = 0xD0,
    Am3I2cClockBlock = 0xD4,
} AM335_I2C_REGISTER, *PAM335_I2C_REGISTER;

//
// -------------------------------------------------------------------- Globals
//

//
// -------------------------------------------------------- Function Prototypes
//