archsup.S 2.9 KB

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  1. /*++
  2. Copyright (c) 2013 Minoca Corp. All Rights Reserved
  3. Module Name:
  4. archsup.S
  5. Abstract:
  6. This module implements assembly-based architecture support routines for the
  7. ARMv6 platform.
  8. Author:
  9. Chris Stevens 2-Feb-2014
  10. Environment:
  11. Boot
  12. --*/
  13. ##
  14. ## ------------------------------------------------------------------- Includes
  15. ##
  16. #include <minoca/kernel/arm.inc>
  17. ##
  18. ## ---------------------------------------------------------------- Definitions
  19. ##
  20. ##
  21. ## ---------------------------------------------------------------------- Code
  22. ##
  23. ASSEMBLY_FILE_HEADER
  24. ##
  25. ## VOID
  26. ## BoInvalidateEntireCache (
  27. ## VOID
  28. ## )
  29. ##
  30. /*++
  31. Routine Description:
  32. This routine invalidates the entire data cache.
  33. Arguments:
  34. None.
  35. Return Value:
  36. None.
  37. --*/
  38. FUNCTION BoInvalidateEntireCache
  39. mov %r1, #0
  40. mcr p15, 0, %r1, %cr7, %cr6, 0 @ Invalidate entire data cache.
  41. mcr p15, 0, %r1, %cr7, %cr10, 4 @ Data Synchronization barrier.
  42. bx %lr
  43. END_FUNCTION BoInvalidateEntireCache
  44. ##
  45. ## ULONG
  46. ## ArGetMultiprocessorIdRegister (
  47. ## VOID
  48. ## )
  49. ##
  50. /*++
  51. Routine Description:
  52. This routine gets the Multiprocessor ID register (MPIDR).
  53. Arguments:
  54. None.
  55. Return Value:
  56. Returns the value of the MPIDR.
  57. --*/
  58. FUNCTION ArGetMultiprocessorIdRegister
  59. ##
  60. ## The MPIDR does not exist on ARMv6; return 0.
  61. ##
  62. mov %r0, #0
  63. bx %lr
  64. END_FUNCTION ArGetMultiprocessorIdRegister
  65. ##
  66. ## ULONG
  67. ## ArGetPerformanceControlRegister (
  68. ## VOID
  69. ## )
  70. ##
  71. /*++
  72. Routine Description:
  73. This routine retrieves the PMCR (Performance Monitor Control Register).
  74. Arguments:
  75. None.
  76. Return Value:
  77. Returns the value of the PMCR.
  78. --*/
  79. FUNCTION ArGetPerformanceControlRegister
  80. mrc p15, 0, %r0, %c15, %c12, 0 @ Get the PMCR.
  81. bx %lr @
  82. END_FUNCTION ArGetPerformanceControlRegister
  83. ##
  84. ## VOID
  85. ## ArSetPerformanceControlRegister (
  86. ## ULONG Value
  87. ## )
  88. ##
  89. /*++
  90. Routine Description:
  91. This routine sets the PMCR (Performance Monitor Control Register).
  92. Arguments:
  93. Value - Supplies the value to set in the PMCR.
  94. Return Value:
  95. None.
  96. --*/
  97. FUNCTION ArSetPerformanceControlRegister
  98. mcr p15, 0, %r0, %c15, %c12, 0 @ Set the PMCR.
  99. bx %lr @
  100. END_FUNCTION ArSetPerformanceControlRegister
  101. ##
  102. ## ULONG
  103. ## ArGetCycleCountRegister (
  104. ## VOID
  105. ## )
  106. ##
  107. /*++
  108. Routine Description:
  109. This routine retrieves the PMCCNTR (Performance Monitor Cycle Counter)
  110. register.
  111. Arguments:
  112. None.
  113. Return Value:
  114. Returns the value of the PMCCNTR.
  115. --*/
  116. FUNCTION ArGetCycleCountRegister
  117. mrc p15, 0, %r0, %c15, %c12, 1 @ Get the PMCCNTR register.
  118. bx %lr @
  119. END_FUNCTION ArGetCycleCountRegister
  120. ##
  121. ## --------------------------------------------------------- Internal Functions
  122. ##