sdrk32.c 121 KB

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  1. /*++
  2. Copyright (c) 2015 Minoca Corp. All rights reserved.
  3. Module Name:
  4. sdrk32.c
  5. Abstract:
  6. This module implements the SD/MMC driver for Rk32xx SoCs. The Rockchip SD
  7. controller is based on the Synopsis DesignWare controller.
  8. Author:
  9. Chris Stevens 29-Jul-2015
  10. Environment:
  11. Kernel
  12. --*/
  13. //
  14. // ------------------------------------------------------------------- Includes
  15. //
  16. #include <minoca/kernel/driver.h>
  17. #include <minoca/kernel/acpi.h>
  18. #include "sdrk32.h"
  19. //
  20. // --------------------------------------------------------------------- Macros
  21. //
  22. //
  23. // These macros read and write SD controller registers.
  24. //
  25. #define SD_DWC_READ_REGISTER(_Device, _Register) \
  26. HlReadRegister32((_Device)->ControllerBase + (_Register))
  27. #define SD_DWC_WRITE_REGISTER(_Device, _Register, _Value) \
  28. HlWriteRegister32((_Device)->ControllerBase + (_Register), (_Value))
  29. #define SD_RK32_READ_CRU(_Device, _Register) \
  30. HlReadRegister32((_Device)->Cru + (_Register))
  31. #define SD_RK32_WRITE_CRU(_Device, _Register, _Value) \
  32. HlWriteRegister32((_Device)->Cru + (_Register), (_Value))
  33. //
  34. // ---------------------------------------------------------------- Definitions
  35. //
  36. //
  37. // ------------------------------------------------------ Data Type Definitions
  38. //
  39. //
  40. // ----------------------------------------------- Internal Function Prototypes
  41. //
  42. KSTATUS
  43. SdRk32AddDevice (
  44. PVOID Driver,
  45. PSTR DeviceId,
  46. PSTR ClassId,
  47. PSTR CompatibleIds,
  48. PVOID DeviceToken
  49. );
  50. VOID
  51. SdRk32DispatchStateChange (
  52. PIRP Irp,
  53. PVOID DeviceContext,
  54. PVOID IrpContext
  55. );
  56. VOID
  57. SdRk32DispatchOpen (
  58. PIRP Irp,
  59. PVOID DeviceContext,
  60. PVOID IrpContext
  61. );
  62. VOID
  63. SdRk32DispatchClose (
  64. PIRP Irp,
  65. PVOID DeviceContext,
  66. PVOID IrpContext
  67. );
  68. VOID
  69. SdRk32DispatchIo (
  70. PIRP Irp,
  71. PVOID DeviceContext,
  72. PVOID IrpContext
  73. );
  74. VOID
  75. SdRk32DispatchSystemControl (
  76. PIRP Irp,
  77. PVOID DeviceContext,
  78. PVOID IrpContext
  79. );
  80. VOID
  81. SdRk32ParentDispatchStateChange (
  82. PIRP Irp,
  83. PSD_RK32_CONTEXT Context,
  84. PVOID IrpContext
  85. );
  86. VOID
  87. SdRk32ChildDispatchStateChange (
  88. PIRP Irp,
  89. PSD_RK32_CHILD Child,
  90. PVOID IrpContext
  91. );
  92. KSTATUS
  93. SdRk32ParentProcessResourceRequirements (
  94. PIRP Irp,
  95. PSD_RK32_CONTEXT Device
  96. );
  97. KSTATUS
  98. SdRk32ParentStartDevice (
  99. PIRP Irp,
  100. PSD_RK32_CONTEXT Device
  101. );
  102. KSTATUS
  103. SdRk32ParentQueryChildren (
  104. PIRP Irp,
  105. PSD_RK32_CONTEXT Device
  106. );
  107. KSTATUS
  108. SdRk32HardResetController (
  109. PSD_RK32_CONTEXT Device
  110. );
  111. KSTATUS
  112. SdRk32InitializeVendorResource (
  113. PSD_RK32_CONTEXT Device,
  114. PRESOURCE_ALLOCATION Resource
  115. );
  116. INTERRUPT_STATUS
  117. SdRk32InterruptService (
  118. PVOID Context
  119. );
  120. INTERRUPT_STATUS
  121. SdRk32InterruptServiceDispatch (
  122. PVOID Context
  123. );
  124. INTERRUPT_STATUS
  125. SdRk32CardInterruptWorker (
  126. PVOID Context
  127. );
  128. VOID
  129. SdRk32DmaCompletion (
  130. PSD_CONTROLLER Controller,
  131. PVOID Context,
  132. UINTN BytesTransferred,
  133. KSTATUS Status
  134. );
  135. PSD_RK32_CHILD
  136. SdRk32pCreateChild (
  137. PSD_RK32_CONTEXT Device
  138. );
  139. VOID
  140. SdRk32pDestroyChild (
  141. PSD_RK32_CHILD Child
  142. );
  143. VOID
  144. SdRk32pChildAddReference (
  145. PSD_RK32_CHILD Child
  146. );
  147. VOID
  148. SdRk32pChildReleaseReference (
  149. PSD_RK32_CHILD Child
  150. );
  151. KSTATUS
  152. SdRk32ChildBlockIoReset (
  153. PVOID DiskToken
  154. );
  155. KSTATUS
  156. SdRk32ChildBlockIoRead (
  157. PVOID DiskToken,
  158. PIO_BUFFER IoBuffer,
  159. ULONGLONG BlockAddress,
  160. UINTN BlockCount,
  161. PUINTN BlocksCompleted
  162. );
  163. KSTATUS
  164. SdRk32ChildBlockIoWrite (
  165. PVOID DiskToken,
  166. PIO_BUFFER IoBuffer,
  167. ULONGLONG BlockAddress,
  168. UINTN BlockCount,
  169. PUINTN BlocksCompleted
  170. );
  171. KSTATUS
  172. SdRk32PerformIoPolled (
  173. PIRP_READ_WRITE IrpReadWrite,
  174. PSD_RK32_CHILD Child,
  175. BOOL Write,
  176. BOOL LockRequired
  177. );
  178. KSTATUS
  179. SdRk32InitializeDma (
  180. PSD_RK32_CONTEXT Device
  181. );
  182. VOID
  183. SdRk32BlockIoDma (
  184. PSD_RK32_CONTEXT Device,
  185. ULONGLONG BlockOffset,
  186. UINTN BlockCount,
  187. PIO_BUFFER IoBuffer,
  188. UINTN IoBufferOffset,
  189. BOOL Write,
  190. PSD_IO_COMPLETION_ROUTINE CompletionRoutine,
  191. PVOID CompletionContext
  192. );
  193. KSTATUS
  194. SdRk32InitializeController (
  195. PSD_CONTROLLER Controller,
  196. PVOID Context,
  197. ULONG Phase
  198. );
  199. KSTATUS
  200. SdRk32ResetController (
  201. PSD_CONTROLLER Controller,
  202. PVOID Context,
  203. ULONG Flags
  204. );
  205. KSTATUS
  206. SdRk32SendCommand (
  207. PSD_CONTROLLER Controller,
  208. PVOID Context,
  209. PSD_COMMAND Command
  210. );
  211. KSTATUS
  212. SdRk32GetSetBusWidth (
  213. PSD_CONTROLLER Controller,
  214. PVOID Context,
  215. BOOL Set
  216. );
  217. KSTATUS
  218. SdRk32GetSetClockSpeed (
  219. PSD_CONTROLLER Controller,
  220. PVOID Context,
  221. BOOL Set
  222. );
  223. KSTATUS
  224. SdRk32GetSetVoltage (
  225. PSD_CONTROLLER Controller,
  226. PVOID Context,
  227. BOOL Set
  228. );
  229. KSTATUS
  230. SdRk32ReadData (
  231. PSD_CONTROLLER Controller,
  232. PVOID Context,
  233. PVOID Data,
  234. ULONG Size
  235. );
  236. KSTATUS
  237. SdRk32WriteData (
  238. PSD_CONTROLLER Controller,
  239. PVOID Context,
  240. PVOID Data,
  241. ULONG Size
  242. );
  243. KSTATUS
  244. SdRk32SetClockSpeed (
  245. PSD_RK32_CONTEXT Device,
  246. SD_CLOCK_SPEED ClockSpeed
  247. );
  248. VOID
  249. SdRk32SetDmaInterrupts (
  250. PSD_CONTROLLER Controller,
  251. PSD_RK32_CONTEXT Device,
  252. BOOL Enable,
  253. ULONG BufferSize
  254. );
  255. KSTATUS
  256. SdRk32UpdateClock (
  257. PSD_RK32_CONTEXT Device
  258. );
  259. VOID
  260. SdRk32Rk808InterfaceNotificationCallback (
  261. PVOID Context,
  262. PDEVICE Device,
  263. PVOID InterfaceBuffer,
  264. ULONG InterfaceBufferSize,
  265. BOOL Arrival
  266. );
  267. KSTATUS
  268. SdRk32SetRegulatorVoltage (
  269. PSD_RK32_CONTEXT Device,
  270. BOOL LowVoltage
  271. );
  272. //
  273. // -------------------------------------------------------------------- Globals
  274. //
  275. PDRIVER SdRk32Driver = NULL;
  276. UUID SdRk32DiskInterfaceUuid = UUID_DISK_INTERFACE;
  277. UUID SdRk32VendorResourceUuid = SD_RK32_VENDOR_RESOURCE_UUID;
  278. UUID SdRk32Rk808InterfaceUuid = UUID_RK808_INTERFACE;
  279. DISK_INTERFACE SdRk32DiskInterfaceTemplate = {
  280. DISK_INTERFACE_VERSION,
  281. NULL,
  282. 0,
  283. 0,
  284. NULL,
  285. SdRk32ChildBlockIoReset,
  286. SdRk32ChildBlockIoRead,
  287. SdRk32ChildBlockIoWrite
  288. };
  289. SD_FUNCTION_TABLE SdRk32FunctionTable = {
  290. SdRk32InitializeController,
  291. SdRk32ResetController,
  292. SdRk32SendCommand,
  293. SdRk32GetSetBusWidth,
  294. SdRk32GetSetClockSpeed,
  295. SdRk32GetSetVoltage,
  296. NULL,
  297. NULL,
  298. NULL,
  299. NULL
  300. };
  301. //
  302. // ------------------------------------------------------------------ Functions
  303. //
  304. KSTATUS
  305. DriverEntry (
  306. PDRIVER Driver
  307. )
  308. /*++
  309. Routine Description:
  310. This routine is the entry point for the SD/MMC driver. It registers its
  311. other dispatch functions, and performs driver-wide initialization.
  312. Arguments:
  313. Driver - Supplies a pointer to the driver object.
  314. Return Value:
  315. STATUS_SUCCESS on success.
  316. Failure code on error.
  317. --*/
  318. {
  319. DRIVER_FUNCTION_TABLE FunctionTable;
  320. KSTATUS Status;
  321. SdRk32Driver = Driver;
  322. RtlZeroMemory(&FunctionTable, sizeof(DRIVER_FUNCTION_TABLE));
  323. FunctionTable.Version = DRIVER_FUNCTION_TABLE_VERSION;
  324. FunctionTable.AddDevice = SdRk32AddDevice;
  325. FunctionTable.DispatchStateChange = SdRk32DispatchStateChange;
  326. FunctionTable.DispatchOpen = SdRk32DispatchOpen;
  327. FunctionTable.DispatchClose = SdRk32DispatchClose;
  328. FunctionTable.DispatchIo = SdRk32DispatchIo;
  329. FunctionTable.DispatchSystemControl = SdRk32DispatchSystemControl;
  330. Status = IoRegisterDriverFunctions(Driver, &FunctionTable);
  331. return Status;
  332. }
  333. KSTATUS
  334. SdRk32AddDevice (
  335. PVOID Driver,
  336. PSTR DeviceId,
  337. PSTR ClassId,
  338. PSTR CompatibleIds,
  339. PVOID DeviceToken
  340. )
  341. /*++
  342. Routine Description:
  343. This routine is called when a device is detected for which the SD/MMC driver
  344. acts as the function driver. The driver will attach itself to the stack.
  345. Arguments:
  346. Driver - Supplies a pointer to the driver being called.
  347. DeviceId - Supplies a pointer to a string with the device ID.
  348. ClassId - Supplies a pointer to a string containing the device's class ID.
  349. CompatibleIds - Supplies a pointer to a string containing device IDs
  350. that would be compatible with this device.
  351. DeviceToken - Supplies an opaque token that the driver can use to identify
  352. the device in the system. This token should be used when attaching to
  353. the stack.
  354. Return Value:
  355. STATUS_SUCCESS on success.
  356. Failure code if the driver was unsuccessful in attaching itself.
  357. --*/
  358. {
  359. PSD_RK32_CONTEXT Context;
  360. KSTATUS Status;
  361. //
  362. // Allocate non-paged pool because this device could be the paging device.
  363. //
  364. Context = MmAllocateNonPagedPool(sizeof(SD_RK32_CONTEXT),
  365. SD_ALLOCATION_TAG);
  366. if (Context == NULL) {
  367. Status = STATUS_INSUFFICIENT_RESOURCES;
  368. goto AddDeviceEnd;
  369. }
  370. RtlZeroMemory(Context, sizeof(SD_RK32_CONTEXT));
  371. Context->Type = SdRk32Parent;
  372. Context->InterruptVector = -1ULL;
  373. Context->CardInterruptVector = -1ULL;
  374. Context->InterruptHandle = INVALID_HANDLE;
  375. Context->CardInterruptHandle = INVALID_HANDLE;
  376. Context->OsDevice = DeviceToken;
  377. KeInitializeSpinLock(&(Context->DpcLock));
  378. Context->Lock = KeCreateQueuedLock();
  379. if (Context->Lock == NULL) {
  380. Status = STATUS_INSUFFICIENT_RESOURCES;
  381. goto AddDeviceEnd;
  382. }
  383. Status = IoAttachDriverToDevice(Driver, DeviceToken, Context);
  384. if (!KSUCCESS(Status)) {
  385. goto AddDeviceEnd;
  386. }
  387. AddDeviceEnd:
  388. if (!KSUCCESS(Status)) {
  389. if (Context != NULL) {
  390. MmFreeNonPagedPool(Context);
  391. }
  392. }
  393. return Status;
  394. }
  395. VOID
  396. SdRk32DispatchStateChange (
  397. PIRP Irp,
  398. PVOID DeviceContext,
  399. PVOID IrpContext
  400. )
  401. /*++
  402. Routine Description:
  403. This routine handles State Change IRPs.
  404. Arguments:
  405. Irp - Supplies a pointer to the I/O request packet.
  406. DeviceContext - Supplies the context pointer supplied by the driver when it
  407. attached itself to the driver stack. Presumably this pointer contains
  408. driver-specific device context.
  409. IrpContext - Supplies the context pointer supplied by the driver when
  410. the IRP was created.
  411. Return Value:
  412. None.
  413. --*/
  414. {
  415. PSD_RK32_CONTEXT Context;
  416. ASSERT(Irp->MajorCode == IrpMajorStateChange);
  417. Context = DeviceContext;
  418. switch (Context->Type) {
  419. case SdRk32Parent:
  420. SdRk32ParentDispatchStateChange(Irp, Context, IrpContext);
  421. break;
  422. case SdRk32Child:
  423. SdRk32ChildDispatchStateChange(Irp,
  424. (PSD_RK32_CHILD)Context,
  425. IrpContext);
  426. break;
  427. default:
  428. ASSERT(FALSE);
  429. break;
  430. }
  431. return;
  432. }
  433. VOID
  434. SdRk32DispatchOpen (
  435. PIRP Irp,
  436. PVOID DeviceContext,
  437. PVOID IrpContext
  438. )
  439. /*++
  440. Routine Description:
  441. This routine handles Open IRPs.
  442. Arguments:
  443. Irp - Supplies a pointer to the I/O request packet.
  444. DeviceContext - Supplies the context pointer supplied by the driver when it
  445. attached itself to the driver stack. Presumably this pointer contains
  446. driver-specific device context.
  447. IrpContext - Supplies the context pointer supplied by the driver when
  448. the IRP was created.
  449. Return Value:
  450. None.
  451. --*/
  452. {
  453. PSD_RK32_CHILD Child;
  454. Child = DeviceContext;
  455. //
  456. // Only the child can be opened or closed.
  457. //
  458. if (Child->Type != SdRk32Child) {
  459. return;
  460. }
  461. SdRk32pChildAddReference(Child);
  462. IoCompleteIrp(SdRk32Driver, Irp, STATUS_SUCCESS);
  463. return;
  464. }
  465. VOID
  466. SdRk32DispatchClose (
  467. PIRP Irp,
  468. PVOID DeviceContext,
  469. PVOID IrpContext
  470. )
  471. /*++
  472. Routine Description:
  473. This routine handles Close IRPs.
  474. Arguments:
  475. Irp - Supplies a pointer to the I/O request packet.
  476. DeviceContext - Supplies the context pointer supplied by the driver when it
  477. attached itself to the driver stack. Presumably this pointer contains
  478. driver-specific device context.
  479. IrpContext - Supplies the context pointer supplied by the driver when
  480. the IRP was created.
  481. Return Value:
  482. None.
  483. --*/
  484. {
  485. PSD_RK32_CHILD Child;
  486. Child = DeviceContext;
  487. if (Child->Type != SdRk32Child) {
  488. return;
  489. }
  490. SdRk32pChildReleaseReference(Child);
  491. IoCompleteIrp(SdRk32Driver, Irp, STATUS_SUCCESS);
  492. return;
  493. }
  494. VOID
  495. SdRk32DispatchIo (
  496. PIRP Irp,
  497. PVOID DeviceContext,
  498. PVOID IrpContext
  499. )
  500. /*++
  501. Routine Description:
  502. This routine handles I/O IRPs.
  503. Arguments:
  504. Irp - Supplies a pointer to the I/O request packet.
  505. DeviceContext - Supplies the context pointer supplied by the driver when it
  506. attached itself to the driver stack. Presumably this pointer contains
  507. driver-specific device context.
  508. IrpContext - Supplies the context pointer supplied by the driver when
  509. the IRP was created.
  510. Return Value:
  511. None.
  512. --*/
  513. {
  514. UINTN BlockCount;
  515. ULONGLONG BlockOffset;
  516. UINTN BytesToComplete;
  517. PSD_RK32_CHILD Child;
  518. BOOL CompleteIrp;
  519. PSD_CONTROLLER Controller;
  520. IO_OFFSET IoOffset;
  521. ULONG IrpReadWriteFlags;
  522. KSTATUS IrpStatus;
  523. KSTATUS Status;
  524. ULONG Value;
  525. BOOL Write;
  526. ASSERT(KeGetRunLevel() == RunLevelLow);
  527. Child = DeviceContext;
  528. Controller = Child->Controller;
  529. if (Child->Type != SdRk32Child) {
  530. ASSERT(FALSE);
  531. return;
  532. }
  533. CompleteIrp = TRUE;
  534. Write = FALSE;
  535. if (Irp->MinorCode == IrpMinorIoWrite) {
  536. Write = TRUE;
  537. }
  538. //
  539. // Polled I/O is shared by a few code paths and prepares the IRP for I/O
  540. // further down the stack. It should also only be hit in the down direction
  541. // path as it always completes the IRP.
  542. //
  543. if ((Child->Flags & SD_RK32_CHILD_FLAG_DMA_SUPPORTED) == 0) {
  544. ASSERT(Irp->Direction == IrpDown);
  545. CompleteIrp = TRUE;
  546. Status = SdRk32PerformIoPolled(&(Irp->U.ReadWrite), Child, Write, TRUE);
  547. goto DispatchIoEnd;
  548. }
  549. //
  550. // Set the IRP read/write flags for the preparation and completion steps.
  551. //
  552. IrpReadWriteFlags = IRP_READ_WRITE_FLAG_DMA;
  553. if (Write != FALSE) {
  554. IrpReadWriteFlags |= IRP_READ_WRITE_FLAG_WRITE;
  555. }
  556. if (Irp->Direction == IrpDown) {
  557. Controller->Try = 0;
  558. }
  559. //
  560. // If the IRP is on the way up, then clean up after the DMA as this IRP is
  561. // still sitting in the channel. An IRP going up is already complete.
  562. //
  563. if (Irp->Direction == IrpUp) {
  564. ASSERT(Irp == Child->Irp);
  565. //
  566. // Disable DMA mode.
  567. //
  568. Value = SD_DWC_READ_REGISTER(Child->Parent, SdDwcControl);
  569. Value &= ~SD_DWC_CONTROL_USE_INTERNAL_DMAC;
  570. SD_DWC_WRITE_REGISTER(Child->Parent, SdDwcControl, Value);
  571. //
  572. // If the IO went badly, try to recover and make another attempt.
  573. //
  574. IrpStatus = IoGetIrpStatus(Irp);
  575. if (!KSUCCESS(IrpStatus)) {
  576. Status = SdErrorRecovery(Controller);
  577. if (!KSUCCESS(Status)) {
  578. IrpStatus = Status;
  579. IoUpdateIrpStatus(Irp, IrpStatus);
  580. }
  581. //
  582. // Do not make further attempts if the media is gone or enough
  583. // attempts have been made.
  584. //
  585. if (((Controller->Flags &
  586. SD_CONTROLLER_FLAG_MEDIA_CHANGED) != 0) ||
  587. ((Controller->Flags &
  588. SD_CONTROLLER_FLAG_MEDIA_PRESENT) == 0) ||
  589. (Controller->Try >= SD_MAX_IO_RETRIES)) {
  590. IrpStatus = STATUS_SUCCESS;
  591. } else {
  592. Controller->Try += 1;
  593. }
  594. }
  595. //
  596. // Release the hold on the controller and complete any buffer
  597. // operations related to the completed transfer.
  598. //
  599. Child->Irp = NULL;
  600. KeReleaseQueuedLock(Child->ControllerLock);
  601. Status = IoCompleteReadWriteIrp(&(Irp->U.ReadWrite),
  602. IrpReadWriteFlags);
  603. if (!KSUCCESS(Status)) {
  604. IoUpdateIrpStatus(Irp, Status);
  605. }
  606. //
  607. // Potentially return the completed IRP.
  608. //
  609. if (KSUCCESS(IrpStatus)) {
  610. CompleteIrp = FALSE;
  611. goto DispatchIoEnd;
  612. }
  613. }
  614. //
  615. // Start the DMA on the way down.
  616. //
  617. BytesToComplete = Irp->U.ReadWrite.IoSizeInBytes;
  618. IoOffset = Irp->U.ReadWrite.IoOffset;
  619. Irp->U.ReadWrite.IoBytesCompleted = 0;
  620. ASSERT(Irp->U.ReadWrite.IoBuffer != NULL);
  621. ASSERT((Child->BlockCount != 0) && (Child->BlockShift != 0));
  622. ASSERT(IS_ALIGNED(IoOffset, 1 << Child->BlockShift) != FALSE);
  623. ASSERT(IS_ALIGNED(BytesToComplete, 1 << Child->BlockShift) != FALSE);
  624. //
  625. // Before acquiring the controller's lock and starting the DMA, prepare
  626. // the I/O context for SD (i.e. it must use physical addresses that
  627. // are less than 4GB and be sector size aligned).
  628. //
  629. Status = IoPrepareReadWriteIrp(&(Irp->U.ReadWrite),
  630. 1 << Child->BlockShift,
  631. 0,
  632. MAX_ULONG,
  633. IrpReadWriteFlags);
  634. if (!KSUCCESS(Status)) {
  635. goto DispatchIoEnd;
  636. }
  637. //
  638. // Lock the controller to serialize access to the hardware.
  639. //
  640. KeAcquireQueuedLock(Child->ControllerLock);
  641. if (((Controller->Flags & SD_CONTROLLER_FLAG_MEDIA_PRESENT) == 0) ||
  642. ((Controller->Flags & SD_CONTROLLER_FLAG_MEDIA_CHANGED) != 0)) {
  643. Status = STATUS_NO_MEDIA;
  644. if ((Controller->Flags & SD_CONTROLLER_FLAG_MEDIA_CHANGED) != 0) {
  645. Status = STATUS_MEDIA_CHANGED;
  646. }
  647. KeReleaseQueuedLock(Child->ControllerLock);
  648. IoCompleteReadWriteIrp(&(Irp->U.ReadWrite), IrpReadWriteFlags);
  649. goto DispatchIoEnd;
  650. }
  651. //
  652. // If it's DMA, just send it on through.
  653. //
  654. Irp->U.ReadWrite.NewIoOffset = IoOffset;
  655. Child->Irp = Irp;
  656. BlockOffset = IoOffset >> Child->BlockShift;
  657. BlockCount = BytesToComplete >> Child->BlockShift;
  658. CompleteIrp = FALSE;
  659. IoPendIrp(SdRk32Driver, Irp);
  660. //
  661. // Set the controller into DMA mode.
  662. //
  663. Value = SD_DWC_READ_REGISTER(Child->Parent, SdDwcControl);
  664. if ((Value & SD_DWC_CONTROL_USE_INTERNAL_DMAC) == 0) {
  665. Value |= SD_DWC_CONTROL_USE_INTERNAL_DMAC;
  666. SD_DWC_WRITE_REGISTER(Child->Parent, SdDwcControl, Value);
  667. }
  668. //
  669. // Make sure the system isn't trying to do I/O off the end of the
  670. // disk.
  671. //
  672. ASSERT(BlockOffset < Child->BlockCount);
  673. ASSERT(BlockCount >= 1);
  674. //
  675. // If it's a multiblock command, send CMD23 first if possible.
  676. //
  677. ASSERT((Controller->IoCompletionRoutine == NULL) &&
  678. (Controller->IoCompletionContext == NULL) &&
  679. (Controller->IoRequestSize == 0));
  680. Controller->SendStop = FALSE;
  681. if (BlockCount > 1) {
  682. Controller->IoCompletionRoutine = SdRk32DmaCompletion;
  683. Controller->IoCompletionContext = Child;
  684. Status = SdSendBlockCount(Controller, BlockCount, Write, TRUE);
  685. if (KSUCCESS(Status)) {
  686. goto DispatchIoEnd;
  687. } else {
  688. Controller->SendStop = TRUE;
  689. Controller->IoCompletionRoutine = NULL;
  690. Controller->IoCompletionContext = NULL;
  691. if (Status == STATUS_NOT_SUPPORTED) {
  692. Status = STATUS_SUCCESS;
  693. } else {
  694. CompleteIrp = TRUE;
  695. KeReleaseQueuedLock(Child->ControllerLock);
  696. goto DispatchIoEnd;
  697. }
  698. }
  699. }
  700. SdRk32BlockIoDma(Child->Parent,
  701. BlockOffset,
  702. BlockCount,
  703. Irp->U.ReadWrite.IoBuffer,
  704. 0,
  705. Write,
  706. SdRk32DmaCompletion,
  707. Child);
  708. //
  709. // DMA transfers are self perpetuating, so after kicking off this
  710. // first transfer, return. This returns with the lock held because
  711. // I/O is still in progress.
  712. //
  713. ASSERT(KeIsQueuedLockHeld(Child->ControllerLock) != FALSE);
  714. ASSERT(CompleteIrp == FALSE);
  715. DispatchIoEnd:
  716. if (CompleteIrp != FALSE) {
  717. IoCompleteIrp(SdRk32Driver, Irp, Status);
  718. }
  719. return;
  720. }
  721. VOID
  722. SdRk32DispatchSystemControl (
  723. PIRP Irp,
  724. PVOID DeviceContext,
  725. PVOID IrpContext
  726. )
  727. /*++
  728. Routine Description:
  729. This routine handles System Control IRPs.
  730. Arguments:
  731. Irp - Supplies a pointer to the I/O request packet.
  732. DeviceContext - Supplies the context pointer supplied by the driver when it
  733. attached itself to the driver stack. Presumably this pointer contains
  734. driver-specific device context.
  735. IrpContext - Supplies the context pointer supplied by the driver when
  736. the IRP was created.
  737. Return Value:
  738. None.
  739. --*/
  740. {
  741. PSD_RK32_CHILD Child;
  742. PVOID Context;
  743. PSYSTEM_CONTROL_FILE_OPERATION FileOperation;
  744. PSYSTEM_CONTROL_LOOKUP Lookup;
  745. PFILE_PROPERTIES Properties;
  746. ULONGLONG PropertiesFileSize;
  747. KSTATUS Status;
  748. Context = Irp->U.SystemControl.SystemContext;
  749. Child = DeviceContext;
  750. //
  751. // Only child devices are supported.
  752. //
  753. if (Child->Type != SdRk32Child) {
  754. ASSERT(Child->Type == SdRk32Parent);
  755. return;
  756. }
  757. switch (Irp->MinorCode) {
  758. case IrpMinorSystemControlLookup:
  759. Lookup = (PSYSTEM_CONTROL_LOOKUP)Context;
  760. Status = STATUS_PATH_NOT_FOUND;
  761. if (Lookup->Root != FALSE) {
  762. //
  763. // Enable opening of the root as a single file.
  764. //
  765. Properties = &(Lookup->Properties);
  766. Properties->FileId = 0;
  767. Properties->Type = IoObjectBlockDevice;
  768. Properties->HardLinkCount = 1;
  769. Properties->BlockCount = Child->BlockCount;
  770. Properties->BlockSize = 1 << Child->BlockShift;
  771. WRITE_INT64_SYNC(&(Properties->FileSize),
  772. Child->BlockCount << Child->BlockShift);
  773. Status = STATUS_SUCCESS;
  774. }
  775. IoCompleteIrp(SdRk32Driver, Irp, Status);
  776. break;
  777. //
  778. // Writes to the disk's properties are not allowed. Fail if the data
  779. // has changed.
  780. //
  781. case IrpMinorSystemControlWriteFileProperties:
  782. FileOperation = (PSYSTEM_CONTROL_FILE_OPERATION)Context;
  783. Properties = FileOperation->FileProperties;
  784. READ_INT64_SYNC(&(Properties->FileSize), &PropertiesFileSize);
  785. if ((Properties->FileId != 0) ||
  786. (Properties->Type != IoObjectBlockDevice) ||
  787. (Properties->HardLinkCount != 1) ||
  788. (Properties->BlockSize != (1 << Child->BlockShift)) ||
  789. (Properties->BlockCount != Child->BlockCount) ||
  790. (PropertiesFileSize != (Child->BlockCount << Child->BlockShift))) {
  791. Status = STATUS_NOT_SUPPORTED;
  792. } else {
  793. Status = STATUS_SUCCESS;
  794. }
  795. IoCompleteIrp(SdRk32Driver, Irp, Status);
  796. break;
  797. //
  798. // Do not support hard disk device truncation.
  799. //
  800. case IrpMinorSystemControlTruncate:
  801. IoCompleteIrp(SdRk32Driver, Irp, STATUS_NOT_SUPPORTED);
  802. break;
  803. //
  804. // Gather and return device information.
  805. //
  806. case IrpMinorSystemControlDeviceInformation:
  807. break;
  808. case IrpMinorSystemControlSynchronize:
  809. IoCompleteIrp(SdRk32Driver, Irp, STATUS_SUCCESS);
  810. break;
  811. //
  812. // Ignore everything unrecognized.
  813. //
  814. default:
  815. ASSERT(FALSE);
  816. break;
  817. }
  818. return;
  819. }
  820. VOID
  821. SdRk32ParentDispatchStateChange (
  822. PIRP Irp,
  823. PSD_RK32_CONTEXT Context,
  824. PVOID IrpContext
  825. )
  826. /*++
  827. Routine Description:
  828. This routine handles State Change IRPs for a parent device.
  829. Arguments:
  830. Irp - Supplies a pointer to the I/O request packet.
  831. Context - Supplies a pointer to the controller information.
  832. IrpContext - Supplies the context pointer supplied by the driver when
  833. the IRP was created.
  834. Return Value:
  835. None.
  836. --*/
  837. {
  838. KSTATUS Status;
  839. if (Irp->Direction == IrpUp) {
  840. if (!KSUCCESS(IoGetIrpStatus(Irp))) {
  841. return;
  842. }
  843. switch (Irp->MinorCode) {
  844. case IrpMinorQueryResources:
  845. Status = SdRk32ParentProcessResourceRequirements(Irp, Context);
  846. if (!KSUCCESS(Status)) {
  847. IoCompleteIrp(SdRk32Driver, Irp, Status);
  848. }
  849. break;
  850. case IrpMinorStartDevice:
  851. Status = SdRk32ParentStartDevice(Irp, Context);
  852. if (!KSUCCESS(Status)) {
  853. IoCompleteIrp(SdRk32Driver, Irp, Status);
  854. }
  855. break;
  856. case IrpMinorQueryChildren:
  857. Status = SdRk32ParentQueryChildren(Irp, Context);
  858. if (!KSUCCESS(Status)) {
  859. IoCompleteIrp(SdRk32Driver, Irp, Status);
  860. }
  861. break;
  862. default:
  863. break;
  864. }
  865. }
  866. return;
  867. }
  868. VOID
  869. SdRk32ChildDispatchStateChange (
  870. PIRP Irp,
  871. PSD_RK32_CHILD Child,
  872. PVOID IrpContext
  873. )
  874. /*++
  875. Routine Description:
  876. This routine handles State Change IRPs for a parent device.
  877. Arguments:
  878. Irp - Supplies a pointer to the I/O request packet.
  879. Child - Supplies a pointer to the child device information.
  880. IrpContext - Supplies the context pointer supplied by the driver when
  881. the IRP was created.
  882. Return Value:
  883. None.
  884. --*/
  885. {
  886. BOOL CompleteIrp;
  887. KSTATUS Status;
  888. ASSERT(Irp->MajorCode == IrpMajorStateChange);
  889. //
  890. // The IRP is on its way down the stack. Do most processing here.
  891. //
  892. if (Irp->Direction == IrpDown) {
  893. Status = STATUS_NOT_SUPPORTED;
  894. CompleteIrp = TRUE;
  895. switch (Irp->MinorCode) {
  896. case IrpMinorQueryResources:
  897. Status = STATUS_SUCCESS;
  898. break;
  899. case IrpMinorStartDevice:
  900. Status = STATUS_SUCCESS;
  901. if (Child->DiskInterface.DiskToken == NULL) {
  902. RtlCopyMemory(&(Child->DiskInterface),
  903. &SdRk32DiskInterfaceTemplate,
  904. sizeof(DISK_INTERFACE));
  905. Child->DiskInterface.BlockSize = 1 << Child->BlockShift;
  906. Child->DiskInterface.BlockCount = Child->BlockCount;
  907. Child->DiskInterface.DiskToken = Child;
  908. Status = IoCreateInterface(&SdRk32DiskInterfaceUuid,
  909. Child->Device,
  910. &(Child->DiskInterface),
  911. sizeof(DISK_INTERFACE));
  912. if (!KSUCCESS(Status)) {
  913. Child->DiskInterface.DiskToken = NULL;
  914. }
  915. }
  916. break;
  917. case IrpMinorQueryChildren:
  918. Irp->U.QueryChildren.Children = NULL;
  919. Irp->U.QueryChildren.ChildCount = 0;
  920. Status = STATUS_SUCCESS;
  921. break;
  922. case IrpMinorQueryInterface:
  923. break;
  924. case IrpMinorRemoveDevice:
  925. if (Child->DiskInterface.DiskToken != NULL) {
  926. Status = IoDestroyInterface(&SdRk32DiskInterfaceUuid,
  927. Child->Device,
  928. &(Child->DiskInterface));
  929. ASSERT(KSUCCESS(Status));
  930. Child->DiskInterface.DiskToken = NULL;
  931. }
  932. SdRk32pChildReleaseReference(Child);
  933. Status = STATUS_SUCCESS;
  934. break;
  935. //
  936. // Pass all other IRPs down.
  937. //
  938. default:
  939. CompleteIrp = FALSE;
  940. break;
  941. }
  942. //
  943. // Complete the IRP unless there's a reason not to.
  944. //
  945. if (CompleteIrp != FALSE) {
  946. IoCompleteIrp(SdRk32Driver, Irp, Status);
  947. }
  948. //
  949. // The IRP is completed and is on its way back up.
  950. //
  951. } else {
  952. ASSERT(Irp->Direction == IrpUp);
  953. }
  954. return;
  955. }
  956. KSTATUS
  957. SdRk32ParentProcessResourceRequirements (
  958. PIRP Irp,
  959. PSD_RK32_CONTEXT Device
  960. )
  961. /*++
  962. Routine Description:
  963. This routine filters through the resource requirements presented by the
  964. bus for a SD RK32xx Host controller. It adds an interrupt vector
  965. requirement for any interrupt line requested.
  966. Arguments:
  967. Irp - Supplies a pointer to the I/O request packet.
  968. Device - Supplies a pointer to this device.
  969. Return Value:
  970. Status code.
  971. --*/
  972. {
  973. PRESOURCE_CONFIGURATION_LIST Requirements;
  974. KSTATUS Status;
  975. RESOURCE_REQUIREMENT VectorRequirement;
  976. ASSERT((Irp->MajorCode == IrpMajorStateChange) &&
  977. (Irp->MinorCode == IrpMinorQueryResources));
  978. //
  979. // Initialize a nice interrupt vector requirement in preparation.
  980. //
  981. RtlZeroMemory(&VectorRequirement, sizeof(RESOURCE_REQUIREMENT));
  982. VectorRequirement.Type = ResourceTypeInterruptVector;
  983. VectorRequirement.Minimum = 0;
  984. VectorRequirement.Maximum = -1;
  985. VectorRequirement.Length = 1;
  986. //
  987. // Loop through all configuration lists, creating a vector for each line.
  988. //
  989. Requirements = Irp->U.QueryResources.ResourceRequirements;
  990. Status = IoCreateAndAddInterruptVectorsForLines(Requirements,
  991. &VectorRequirement);
  992. if (!KSUCCESS(Status)) {
  993. goto ProcessResourceRequirementsEnd;
  994. }
  995. ProcessResourceRequirementsEnd:
  996. return Status;
  997. }
  998. KSTATUS
  999. SdRk32ParentStartDevice (
  1000. PIRP Irp,
  1001. PSD_RK32_CONTEXT Device
  1002. )
  1003. /*++
  1004. Routine Description:
  1005. This routine starts up the RK32xx SD controller.
  1006. Arguments:
  1007. Irp - Supplies a pointer to the I/O request packet.
  1008. Device - Supplies a pointer to this SD RK32xx device.
  1009. Return Value:
  1010. Status code.
  1011. --*/
  1012. {
  1013. PRESOURCE_ALLOCATION Allocation;
  1014. PRESOURCE_ALLOCATION_LIST AllocationList;
  1015. IO_CONNECT_INTERRUPT_PARAMETERS Connect;
  1016. PRESOURCE_ALLOCATION ControllerBase;
  1017. PRESOURCE_ALLOCATION LineAllocation;
  1018. SD_INITIALIZATION_BLOCK Parameters;
  1019. KSTATUS Status;
  1020. PRESOURCE_ALLOCATION VendorResource;
  1021. ControllerBase = NULL;
  1022. VendorResource = NULL;
  1023. //
  1024. // Loop through the allocated resources to get the controller base and the
  1025. // interrupt.
  1026. //
  1027. AllocationList = Irp->U.StartDevice.ProcessorLocalResources;
  1028. Allocation = IoGetNextResourceAllocation(AllocationList, NULL);
  1029. while (Allocation != NULL) {
  1030. //
  1031. // If the resource is an interrupt vector, then it should have an
  1032. // owning interrupt line allocation.
  1033. //
  1034. if (Allocation->Type == ResourceTypeInterruptVector) {
  1035. ASSERT(Allocation->OwningAllocation != NULL);
  1036. //
  1037. // Save the line and vector number. The first one is the main
  1038. // interrupt, the second one is the card detect interrupt.
  1039. //
  1040. LineAllocation = Allocation->OwningAllocation;
  1041. if (Device->InterruptVector == -1ULL) {
  1042. Device->InterruptLine = LineAllocation->Allocation;
  1043. Device->InterruptVector = Allocation->Allocation;
  1044. } else {
  1045. ASSERT(Device->CardInterruptVector == -1ULL);
  1046. Device->CardInterruptLine = LineAllocation->Allocation;
  1047. Device->CardInterruptVector = Allocation->Allocation;
  1048. }
  1049. } else if (Allocation->Type == ResourceTypePhysicalAddressSpace) {
  1050. ASSERT(ControllerBase == NULL);
  1051. ControllerBase = Allocation;
  1052. } else if (Allocation->Type == ResourceTypeVendorSpecific) {
  1053. ASSERT(VendorResource == NULL);
  1054. VendorResource = Allocation;
  1055. }
  1056. //
  1057. // Get the next allocation in the list.
  1058. //
  1059. Allocation = IoGetNextResourceAllocation(AllocationList, Allocation);
  1060. }
  1061. //
  1062. // Fail to start if the controller base was not found.
  1063. //
  1064. if ((ControllerBase == NULL) ||
  1065. (ControllerBase->Length < SD_RK32_CONTROLLER_LENGTH) ||
  1066. (VendorResource == NULL)) {
  1067. Status = STATUS_INVALID_CONFIGURATION;
  1068. goto StartDeviceEnd;
  1069. }
  1070. //
  1071. // Initialize RK32xx specific stuff.
  1072. //
  1073. if (Device->ControllerBase == NULL) {
  1074. Device->PhysicalAddress = ControllerBase->Allocation;
  1075. Device->ControllerBase = MmMapPhysicalAddress(
  1076. ControllerBase->Allocation,
  1077. ControllerBase->Length,
  1078. TRUE,
  1079. FALSE,
  1080. TRUE);
  1081. if (Device->ControllerBase == NULL) {
  1082. Status = STATUS_INSUFFICIENT_RESOURCES;
  1083. goto StartDeviceEnd;
  1084. }
  1085. }
  1086. Status = SdRk32InitializeVendorResource(Device, VendorResource);
  1087. if (!KSUCCESS(Status)) {
  1088. RtlDebugPrint("SdRk32InitializeVendorResource Failed: %x\n", Status);
  1089. goto StartDeviceEnd;
  1090. }
  1091. Status = SdRk32HardResetController(Device);
  1092. if (Status == STATUS_NO_MEDIA) {
  1093. Status = STATUS_SUCCESS;
  1094. goto StartDeviceEnd;
  1095. } else if (!KSUCCESS(Status)) {
  1096. RtlDebugPrint("SdRk32ResetController Failed: %x\n", Status);
  1097. goto StartDeviceEnd;
  1098. }
  1099. //
  1100. // Initialize the standard SD controller.
  1101. //
  1102. if (Device->Controller == NULL) {
  1103. RtlZeroMemory(&Parameters, sizeof(SD_INITIALIZATION_BLOCK));
  1104. Parameters.Voltages = SD_VOLTAGE_32_33 | SD_VOLTAGE_33_34;
  1105. Parameters.HostCapabilities = SD_MODE_4BIT |
  1106. SD_MODE_HIGH_SPEED |
  1107. SD_MODE_AUTO_CMD12 |
  1108. SD_MODE_CMD23;
  1109. Parameters.FundamentalClock = Device->FundamentalClock;
  1110. Parameters.ConsumerContext = Device;
  1111. Parameters.OsDevice = Device->OsDevice;
  1112. RtlCopyMemory(&(Parameters.FunctionTable),
  1113. &SdRk32FunctionTable,
  1114. sizeof(SD_FUNCTION_TABLE));
  1115. Device->Controller = SdCreateController(&Parameters);
  1116. if (Device->Controller == NULL) {
  1117. Status = STATUS_INSUFFICIENT_RESOURCES;
  1118. goto StartDeviceEnd;
  1119. }
  1120. }
  1121. //
  1122. // Attempt to connect the interrupt before initializing the controller. The
  1123. // initialization process may trigger some interrupts.
  1124. //
  1125. if (Device->InterruptHandle == INVALID_HANDLE) {
  1126. RtlZeroMemory(&Connect, sizeof(IO_CONNECT_INTERRUPT_PARAMETERS));
  1127. Connect.Version = IO_CONNECT_INTERRUPT_PARAMETERS_VERSION;
  1128. Connect.Device = Irp->Device;
  1129. Connect.LineNumber = Device->InterruptLine;
  1130. Connect.Vector = Device->InterruptVector;
  1131. Connect.InterruptServiceRoutine = SdRk32InterruptService;
  1132. Connect.DispatchServiceRoutine = SdRk32InterruptServiceDispatch;
  1133. Connect.Context = Device;
  1134. Connect.Interrupt = &(Device->InterruptHandle);
  1135. Status = IoConnectInterrupt(&Connect);
  1136. if (!KSUCCESS(Status)) {
  1137. goto StartDeviceEnd;
  1138. }
  1139. Device->Controller->InterruptHandle = Device->InterruptHandle;
  1140. }
  1141. //
  1142. // Also wire up the card detect interrupt if it's present.
  1143. //
  1144. if ((Device->CardInterruptHandle == INVALID_HANDLE) &&
  1145. (Device->CardInterruptVector != -1ULL)) {
  1146. RtlZeroMemory(&Connect, sizeof(IO_CONNECT_INTERRUPT_PARAMETERS));
  1147. Connect.Version = IO_CONNECT_INTERRUPT_PARAMETERS_VERSION;
  1148. Connect.Device = Irp->Device;
  1149. Connect.LineNumber = Device->CardInterruptLine;
  1150. Connect.Vector = Device->CardInterruptVector;
  1151. Connect.LowLevelServiceRoutine = SdRk32CardInterruptWorker;
  1152. Connect.Context = Device;
  1153. Connect.Interrupt = &(Device->InterruptHandle);
  1154. Status = IoConnectInterrupt(&Connect);
  1155. if (!KSUCCESS(Status)) {
  1156. goto StartDeviceEnd;
  1157. }
  1158. }
  1159. Status = STATUS_SUCCESS;
  1160. StartDeviceEnd:
  1161. if (!KSUCCESS(Status)) {
  1162. if (Device->InterruptHandle != INVALID_HANDLE) {
  1163. IoDisconnectInterrupt(Device->InterruptHandle);
  1164. Device->InterruptHandle = INVALID_HANDLE;
  1165. Device->Controller->InterruptHandle = INVALID_HANDLE;
  1166. }
  1167. if (Device->CardInterruptHandle != INVALID_HANDLE) {
  1168. IoDisconnectInterrupt(Device->CardInterruptHandle);
  1169. }
  1170. if (Device->Controller != NULL) {
  1171. SdDestroyController(Device->Controller);
  1172. Device->Controller = NULL;
  1173. }
  1174. }
  1175. return Status;
  1176. }
  1177. KSTATUS
  1178. SdRk32ParentQueryChildren (
  1179. PIRP Irp,
  1180. PSD_RK32_CONTEXT Device
  1181. )
  1182. /*++
  1183. Routine Description:
  1184. This routine potentially enumerates the disk device for the SD RK32xx
  1185. controller.
  1186. Arguments:
  1187. Irp - Supplies a pointer to the I/O request packet.
  1188. Device - Supplies a pointer to this device.
  1189. Return Value:
  1190. Status code.
  1191. --*/
  1192. {
  1193. ULONG BlockSize;
  1194. PSTR DeviceId;
  1195. ULONG FlagsMask;
  1196. PSD_RK32_CHILD NewChild;
  1197. ULONG OldFlags;
  1198. KSTATUS Status;
  1199. NewChild = NULL;
  1200. //
  1201. // Check to see if any changes to the children are pending.
  1202. //
  1203. FlagsMask = SD_CONTROLLER_FLAG_INSERTION_PENDING |
  1204. SD_CONTROLLER_FLAG_REMOVAL_PENDING;
  1205. OldFlags = RtlAtomicAnd32(&(Device->Controller->Flags), ~FlagsMask);
  1206. //
  1207. // If either a removal or insertion is pending, clean out the old child.
  1208. // In practice, not all removals interrupt, meaning that two insertions can
  1209. // arrive in a row.
  1210. //
  1211. if ((OldFlags & FlagsMask) != 0) {
  1212. if (Device->Child != NULL) {
  1213. KeAcquireQueuedLock(Device->Lock);
  1214. RtlAtomicAnd32(&(Device->Child->Controller->Flags),
  1215. ~SD_CONTROLLER_FLAG_MEDIA_PRESENT);
  1216. KeReleaseQueuedLock(Device->Lock);
  1217. Device->Child = NULL;
  1218. }
  1219. }
  1220. //
  1221. // If an insertion is pending, try to enumerate the child.
  1222. //
  1223. if ((OldFlags & SD_CONTROLLER_FLAG_INSERTION_PENDING) != 0) {
  1224. ASSERT(Device->Child == NULL);
  1225. RtlAtomicAnd32(&(Device->Controller->Flags),
  1226. ~SD_CONTROLLER_FLAG_MEDIA_CHANGED);
  1227. Status = SdInitializeController(Device->Controller, FALSE);
  1228. if (!KSUCCESS(Status)) {
  1229. if (Status == STATUS_TIMEOUT) {
  1230. Status = STATUS_SUCCESS;
  1231. } else {
  1232. RtlDebugPrint("SdInitializeController failed: %x\n", Status);
  1233. }
  1234. goto ParentQueryChildrenEnd;
  1235. }
  1236. NewChild = SdRk32pCreateChild(Device);
  1237. if (NewChild == NULL) {
  1238. Status = STATUS_INSUFFICIENT_RESOURCES;
  1239. goto ParentQueryChildrenEnd;
  1240. }
  1241. BlockSize = 0;
  1242. Status = SdGetMediaParameters(NewChild->Controller,
  1243. &(NewChild->BlockCount),
  1244. &BlockSize);
  1245. if (!KSUCCESS(Status)) {
  1246. if (Status == STATUS_NO_MEDIA) {
  1247. Status = STATUS_SUCCESS;
  1248. }
  1249. goto ParentQueryChildrenEnd;
  1250. }
  1251. ASSERT(POWER_OF_2(BlockSize) != FALSE);
  1252. NewChild->BlockShift = RtlCountTrailingZeros32(BlockSize);
  1253. //
  1254. // Try to enable DMA, but it's okay if it doesn't succeed.
  1255. //
  1256. Status = SdRk32InitializeDma(Device);
  1257. if (KSUCCESS(Status)) {
  1258. NewChild->Flags |= SD_RK32_CHILD_FLAG_DMA_SUPPORTED;
  1259. } else if (Status == STATUS_NO_MEDIA) {
  1260. Status = STATUS_SUCCESS;
  1261. goto ParentQueryChildrenEnd;
  1262. }
  1263. DeviceId = SD_MMC_DEVICE_ID;
  1264. if (SD_IS_CARD_SD(Device->Controller)) {
  1265. DeviceId = SD_CARD_DEVICE_ID;
  1266. }
  1267. Status = IoCreateDevice(SdRk32Driver,
  1268. NewChild,
  1269. Irp->Device,
  1270. DeviceId,
  1271. DISK_CLASS_ID,
  1272. NULL,
  1273. &(NewChild->Device));
  1274. if (!KSUCCESS(Status)) {
  1275. return Status;
  1276. }
  1277. Device->Child = NewChild;
  1278. NewChild = NULL;
  1279. }
  1280. //
  1281. // If there's no child present, don't enumerate it.
  1282. //
  1283. if (Device->Child == NULL) {
  1284. return STATUS_SUCCESS;
  1285. }
  1286. ASSERT((Device->Child != NULL) && (Device->Child->Device != NULL));
  1287. //
  1288. // Enumerate the one child.
  1289. //
  1290. Status = IoMergeChildArrays(Irp,
  1291. &(Device->Child->Device),
  1292. 1,
  1293. SD_ALLOCATION_TAG);
  1294. ParentQueryChildrenEnd:
  1295. if (NewChild != NULL) {
  1296. ASSERT(NewChild->Device == NULL);
  1297. SdRk32pChildReleaseReference(NewChild);
  1298. }
  1299. return Status;
  1300. }
  1301. KSTATUS
  1302. SdRk32HardResetController (
  1303. PSD_RK32_CONTEXT Device
  1304. )
  1305. /*++
  1306. Routine Description:
  1307. This routine hard resets the RK32xx SD controller and card.
  1308. Arguments:
  1309. Device - Supplies a pointer to this SD RK32xx device.
  1310. Return Value:
  1311. Status code.
  1312. --*/
  1313. {
  1314. ULONGLONG Frequency;
  1315. ULONG ResetMask;
  1316. KSTATUS Status;
  1317. ULONGLONG Timeout;
  1318. ULONG Value;
  1319. Frequency = HlQueryTimeCounterFrequency();
  1320. //
  1321. // First perform a hardware reset on the SD card.
  1322. //
  1323. SD_DWC_WRITE_REGISTER(Device, SdDwcPower, SD_DWC_POWER_DISABLE);
  1324. SD_DWC_WRITE_REGISTER(Device, SdDwcResetN, SD_DWC_RESET_ENABLE);
  1325. HlBusySpin(5000);
  1326. SD_DWC_WRITE_REGISTER(Device, SdDwcPower, SD_DWC_POWER_ENABLE);
  1327. SD_DWC_WRITE_REGISTER(Device, SdDwcResetN, 0);
  1328. HlBusySpin(1000);
  1329. //
  1330. // Perform a complete controller reset and wait for it to complete.
  1331. //
  1332. ResetMask = SD_DWC_CONTROL_FIFO_RESET |
  1333. SD_DWC_CONTROL_DMA_RESET |
  1334. SD_DWC_CONTROL_CONTROLLER_RESET;
  1335. SD_DWC_WRITE_REGISTER(Device, SdDwcControl, ResetMask);
  1336. Status = STATUS_TIMEOUT;
  1337. Timeout = KeGetRecentTimeCounter() + (Frequency * SD_RK32_TIMEOUT);
  1338. do {
  1339. Value = SD_DWC_READ_REGISTER(Device, SdDwcControl);
  1340. if ((Value & ResetMask) == 0) {
  1341. Status = STATUS_SUCCESS;
  1342. break;
  1343. }
  1344. } while (KeGetRecentTimeCounter() <= Timeout);
  1345. if (!KSUCCESS(Status)) {
  1346. goto HardResetControllerEnd;
  1347. }
  1348. //
  1349. // Reset the internal DMA.
  1350. //
  1351. Value = SD_DWC_READ_REGISTER(Device, SdDwcBusMode);
  1352. Value |= SD_DWC_BUS_MODE_INTERNAL_DMA_RESET;
  1353. SD_DWC_WRITE_REGISTER(Device, SdDwcBusMode, Value);
  1354. Status = STATUS_TIMEOUT;
  1355. Timeout = KeGetRecentTimeCounter() + (Frequency * SD_RK32_TIMEOUT);
  1356. do {
  1357. Value = SD_DWC_READ_REGISTER(Device, SdDwcBusMode);
  1358. if ((Value & SD_DWC_BUS_MODE_INTERNAL_DMA_RESET) == 0) {
  1359. Status = STATUS_SUCCESS;
  1360. break;
  1361. }
  1362. } while (KeGetRecentTimeCounter() <= Timeout);
  1363. if (!KSUCCESS(Status)) {
  1364. return Status;
  1365. }
  1366. Status = SdRk32SetRegulatorVoltage(Device, FALSE);
  1367. if (!KSUCCESS(Status)) {
  1368. return Status;
  1369. }
  1370. //
  1371. // Clear interrupts.
  1372. //
  1373. SD_DWC_WRITE_REGISTER(Device,
  1374. SdDwcInterruptStatus,
  1375. SD_DWC_INTERRUPT_STATUS_ALL_MASK);
  1376. //
  1377. // Set 3v3 volts in the UHS register.
  1378. //
  1379. SD_DWC_WRITE_REGISTER(Device, SdDwcUhs, SD_DWC_UHS_VOLTAGE_3V3);
  1380. //
  1381. // Set the clock to 400kHz in preparation for sending CMD0 with the
  1382. // initialization bit set.
  1383. //
  1384. Status = SdRk32SetClockSpeed(Device, SdClock400kHz);
  1385. if (!KSUCCESS(Status)) {
  1386. goto HardResetControllerEnd;
  1387. }
  1388. //
  1389. // Reset the card by sending the CMD0 reset command with the initialization
  1390. // bit set.
  1391. //
  1392. Value = SD_DWC_COMMAND_START |
  1393. SD_DWC_COMMAND_USE_HOLD_REGISTER |
  1394. SD_DWC_COMMAND_SEND_INITIALIZATION;
  1395. SD_DWC_WRITE_REGISTER(Device, SdDwcCommand, Value);
  1396. //
  1397. // Wait for the command to complete.
  1398. //
  1399. Status = STATUS_TIMEOUT;
  1400. Timeout = KeGetRecentTimeCounter() + (Frequency * SD_RK32_TIMEOUT);
  1401. do {
  1402. Value = SD_DWC_READ_REGISTER(Device, SdDwcCommand);
  1403. if ((Value & SD_DWC_COMMAND_START) == 0) {
  1404. Status = STATUS_SUCCESS;
  1405. break;
  1406. }
  1407. } while (KeGetRecentTimeCounter() <= Timeout);
  1408. if (!KSUCCESS(Status)) {
  1409. goto HardResetControllerEnd;
  1410. }
  1411. Status = STATUS_TIMEOUT;
  1412. Timeout = KeGetRecentTimeCounter() + (Frequency * SD_RK32_TIMEOUT);
  1413. do {
  1414. Value = SD_DWC_READ_REGISTER(Device, SdDwcInterruptStatus);
  1415. if (Value != 0) {
  1416. if ((Value & SD_DWC_INTERRUPT_STATUS_COMMAND_DONE) != 0) {
  1417. Status = STATUS_SUCCESS;
  1418. } else if ((Value &
  1419. SD_DWC_INTERRUPT_STATUS_ERROR_RESPONSE_TIMEOUT) != 0) {
  1420. Status = STATUS_NO_MEDIA;
  1421. } else {
  1422. Status = STATUS_DEVICE_IO_ERROR;
  1423. }
  1424. SD_DWC_WRITE_REGISTER(Device, SdDwcInterruptStatus, Value);
  1425. break;
  1426. }
  1427. } while (KeGetRecentTimeCounter() <= Timeout);
  1428. if (!KSUCCESS(Status)) {
  1429. goto HardResetControllerEnd;
  1430. }
  1431. HardResetControllerEnd:
  1432. return Status;
  1433. }
  1434. KSTATUS
  1435. SdRk32InitializeVendorResource (
  1436. PSD_RK32_CONTEXT Device,
  1437. PRESOURCE_ALLOCATION Resource
  1438. )
  1439. /*++
  1440. Routine Description:
  1441. This routine gets the fundamental clock frequency to use for the SD
  1442. controller. It initializes the device context with the value.
  1443. Arguments:
  1444. Device - Supplies a pointer to the SD RK32 device.
  1445. Resource - Supplies a pointer to the vendor specific resource data.
  1446. Return Value:
  1447. Status code.
  1448. --*/
  1449. {
  1450. PSD_RK32_VENDOR_RESOURCE Data;
  1451. KSTATUS Status;
  1452. Data = Resource->Data;
  1453. if (Resource->DataSize < sizeof(SD_RK32_VENDOR_RESOURCE)) {
  1454. return STATUS_DATA_LENGTH_MISMATCH;
  1455. }
  1456. if (RtlAreUuidsEqual(&(Data->Uuid), &SdRk32VendorResourceUuid) == FALSE) {
  1457. return STATUS_INVALID_CONFIGURATION;
  1458. }
  1459. Device->FundamentalClock = Data->FundamentalClock;
  1460. Device->Ldo = Data->Ldo;
  1461. if (Device->Ldo != 0) {
  1462. Status = IoRegisterForInterfaceNotifications(
  1463. &SdRk32Rk808InterfaceUuid,
  1464. SdRk32Rk808InterfaceNotificationCallback,
  1465. NULL,
  1466. Device,
  1467. TRUE);
  1468. if (!KSUCCESS(Status)) {
  1469. goto InitializeVendorResourceEnd;
  1470. }
  1471. }
  1472. //
  1473. // Eventually, this should be handled by a more official clock manager.
  1474. //
  1475. Device->Cru = MmMapPhysicalAddress(Data->Cru,
  1476. MmPageSize(),
  1477. TRUE,
  1478. FALSE,
  1479. TRUE);
  1480. if (Device->Cru == NULL) {
  1481. Status = STATUS_INSUFFICIENT_RESOURCES;
  1482. goto InitializeVendorResourceEnd;
  1483. }
  1484. Device->VendorData = Data;
  1485. Status = STATUS_SUCCESS;
  1486. InitializeVendorResourceEnd:
  1487. return Status;
  1488. }
  1489. INTERRUPT_STATUS
  1490. SdRk32InterruptService (
  1491. PVOID Context
  1492. )
  1493. /*++
  1494. Routine Description:
  1495. This routine implements the RK32xx SD interrupt service routine.
  1496. Arguments:
  1497. Context - Supplies the context pointer given to the system when the
  1498. interrupt was connected. In this case, this points to the RK32xx SD
  1499. controller.
  1500. Return Value:
  1501. Interrupt status.
  1502. --*/
  1503. {
  1504. PSD_CONTROLLER Controller;
  1505. PSD_RK32_CONTEXT Device;
  1506. ULONG MaskedStatus;
  1507. Device = (PSD_RK32_CONTEXT)Context;
  1508. MaskedStatus = SD_DWC_READ_REGISTER(Device, SdDwcMaskedInterruptStatus);
  1509. if (MaskedStatus == 0) {
  1510. return InterruptStatusNotClaimed;
  1511. }
  1512. Controller = Device->Controller;
  1513. SD_DWC_WRITE_REGISTER(Device, SdDwcInterruptStatus, MaskedStatus);
  1514. RtlAtomicOr32(&(Controller->PendingStatusBits), MaskedStatus);
  1515. return InterruptStatusClaimed;
  1516. }
  1517. INTERRUPT_STATUS
  1518. SdRk32InterruptServiceDispatch (
  1519. PVOID Context
  1520. )
  1521. /*++
  1522. Routine Description:
  1523. This routine implements the RK32xx SD dispatch level interrupt service
  1524. routine.
  1525. Arguments:
  1526. Context - Supplies the context pointer given to the system when the
  1527. interrupt was connected. In this case, this points to the RK32xx SD
  1528. controller.
  1529. Return Value:
  1530. Interrupt status.
  1531. --*/
  1532. {
  1533. UINTN BytesCompleted;
  1534. PVOID CompletionContext;
  1535. PSD_IO_COMPLETION_ROUTINE CompletionRoutine;
  1536. PSD_CONTROLLER Controller;
  1537. PSD_RK32_CONTEXT Device;
  1538. BOOL Inserted;
  1539. ULONG PendingBits;
  1540. BOOL Removed;
  1541. KSTATUS Status;
  1542. Device = (PSD_RK32_CONTEXT)Context;
  1543. Controller = Device->Controller;
  1544. PendingBits = RtlAtomicExchange32(&(Controller->PendingStatusBits), 0);
  1545. if (PendingBits == 0) {
  1546. return InterruptStatusNotClaimed;
  1547. }
  1548. //
  1549. // Process a media change.
  1550. //
  1551. Status = STATUS_DEVICE_IO_ERROR;
  1552. Inserted = FALSE;
  1553. Removed = FALSE;
  1554. if ((PendingBits & SD_DWC_INTERRUPT_STATUS_CARD_DETECT) != 0) {
  1555. //
  1556. // TODO: Hanndle RK32xx SD/MMC insertion and removal.
  1557. //
  1558. ASSERT(FALSE);
  1559. }
  1560. KeAcquireSpinLock(&(Device->DpcLock));
  1561. //
  1562. // Process the I/O completion. The only other interrupt bits that are sent
  1563. // to the DPC are the error bits and the transfer complete bit.
  1564. //
  1565. if ((PendingBits & SD_DWC_INTERRUPT_ERROR_MASK) != 0) {
  1566. Status = STATUS_DEVICE_IO_ERROR;
  1567. if ((Controller->Flags & SD_CONTROLLER_FLAG_MEDIA_CHANGED) != 0) {
  1568. Inserted = TRUE;
  1569. Removed = TRUE;
  1570. } else if ((Controller->Flags &
  1571. SD_CONTROLLER_FLAG_MEDIA_PRESENT) == 0) {
  1572. Removed = TRUE;
  1573. }
  1574. } else if ((PendingBits &
  1575. SD_DWC_INTERRUPT_STATUS_DATA_TRANSFER_OVER) != 0) {
  1576. Status = STATUS_SUCCESS;
  1577. } else if ((PendingBits & SD_DWC_INTERRUPT_STATUS_COMMAND_DONE) != 0) {
  1578. Status = STATUS_SUCCESS;
  1579. }
  1580. if (Controller->IoCompletionRoutine != NULL) {
  1581. CompletionRoutine = Controller->IoCompletionRoutine;
  1582. CompletionContext = Controller->IoCompletionContext;
  1583. BytesCompleted = Controller->IoRequestSize;
  1584. Controller->IoCompletionRoutine = NULL;
  1585. Controller->IoCompletionContext = NULL;
  1586. Controller->IoRequestSize = 0;
  1587. CompletionRoutine(Controller,
  1588. CompletionContext,
  1589. BytesCompleted,
  1590. Status);
  1591. }
  1592. if (((Inserted != FALSE) || (Removed != FALSE)) &&
  1593. (Controller->FunctionTable.MediaChangeCallback != NULL)) {
  1594. Controller->FunctionTable.MediaChangeCallback(
  1595. Controller,
  1596. Controller->ConsumerContext,
  1597. Removed,
  1598. Inserted);
  1599. }
  1600. KeReleaseSpinLock(&(Device->DpcLock));
  1601. return InterruptStatusClaimed;
  1602. }
  1603. INTERRUPT_STATUS
  1604. SdRk32CardInterruptWorker (
  1605. PVOID Context
  1606. )
  1607. /*++
  1608. Routine Description:
  1609. This routine implements the RK32xx SD low level card detect interrupt
  1610. service work routine.
  1611. Arguments:
  1612. Context - Supplies the context pointer given to the system when the
  1613. interrupt was connected. In this case, this points to the RK32xx SD
  1614. controller.
  1615. Return Value:
  1616. Interrupt status.
  1617. --*/
  1618. {
  1619. PSD_RK32_CONTEXT Device;
  1620. Device = (PSD_RK32_CONTEXT)Context;
  1621. if (Device->Controller->FunctionTable.MediaChangeCallback != NULL) {
  1622. Device->Controller->FunctionTable.MediaChangeCallback(
  1623. Device->Controller,
  1624. NULL,
  1625. TRUE,
  1626. TRUE);
  1627. }
  1628. return InterruptStatusClaimed;
  1629. }
  1630. VOID
  1631. SdRk32DmaCompletion (
  1632. PSD_CONTROLLER Controller,
  1633. PVOID Context,
  1634. UINTN BytesTransferred,
  1635. KSTATUS Status
  1636. )
  1637. /*++
  1638. Routine Description:
  1639. This routine is called by the SD library when a DMA transfer completes.
  1640. This routine is called from a DPC and, as a result, can get called back
  1641. at dispatch level.
  1642. Arguments:
  1643. Controller - Supplies a pointer to the controller.
  1644. Context - Supplies a context pointer passed to the library when the DMA
  1645. request was issued.
  1646. BytesTransferred - Supplies the number of bytes transferred in the request.
  1647. Status - Supplies the status code representing the completion of the I/O.
  1648. Return Value:
  1649. None.
  1650. --*/
  1651. {
  1652. UINTN BlockCount;
  1653. ULONGLONG BlockOffset;
  1654. PSD_RK32_CHILD Child;
  1655. IO_OFFSET IoOffset;
  1656. UINTN IoSize;
  1657. PIRP Irp;
  1658. BOOL Write;
  1659. Child = Context;
  1660. Irp = Child->Irp;
  1661. ASSERT(Irp != NULL);
  1662. if (!KSUCCESS(Status)) {
  1663. RtlDebugPrint("SD RK32xx Failed %x %I64x %x: %x\n",
  1664. Irp->MinorCode,
  1665. Irp->U.ReadWrite.IoOffset,
  1666. Irp->U.ReadWrite.IoSizeInBytes,
  1667. Status);
  1668. BytesTransferred = 0;
  1669. IoCompleteIrp(SdRk32Driver, Irp, Status);
  1670. return;
  1671. }
  1672. Irp->U.ReadWrite.IoBytesCompleted += BytesTransferred;
  1673. Irp->U.ReadWrite.NewIoOffset += BytesTransferred;
  1674. //
  1675. // If this transfer's over, potentially send a stop. If that's done or
  1676. // not needed, complete the IRP.
  1677. //
  1678. if (Irp->U.ReadWrite.IoBytesCompleted ==
  1679. Irp->U.ReadWrite.IoSizeInBytes) {
  1680. if ((Controller->SendStop != FALSE) &&
  1681. ((Controller->HostCapabilities & SD_MODE_AUTO_CMD12) == 0)) {
  1682. Controller->SendStop = FALSE;
  1683. Child->Controller->IoCompletionRoutine = SdRk32DmaCompletion;
  1684. Child->Controller->IoCompletionContext = Child;
  1685. Status = SdSendStop(Controller, TRUE, TRUE);
  1686. if (!KSUCCESS(Status)) {
  1687. IoCompleteIrp(SdRk32Driver, Irp, Status);
  1688. }
  1689. } else {
  1690. IoCompleteIrp(SdRk32Driver, Irp, Status);
  1691. }
  1692. return;
  1693. }
  1694. IoOffset = Irp->U.ReadWrite.IoOffset + Irp->U.ReadWrite.IoBytesCompleted;
  1695. BlockOffset = IoOffset >> Child->BlockShift;
  1696. IoSize = Irp->U.ReadWrite.IoSizeInBytes -
  1697. Irp->U.ReadWrite.IoBytesCompleted;
  1698. BlockCount = IoSize >> Child->BlockShift;
  1699. Write = FALSE;
  1700. if (Irp->MinorCode == IrpMinorIoWrite) {
  1701. Write = TRUE;
  1702. }
  1703. SdRk32BlockIoDma(Child->Parent,
  1704. BlockOffset,
  1705. BlockCount,
  1706. Irp->U.ReadWrite.IoBuffer,
  1707. Irp->U.ReadWrite.IoBytesCompleted,
  1708. Write,
  1709. SdRk32DmaCompletion,
  1710. Child);
  1711. return;
  1712. }
  1713. PSD_RK32_CHILD
  1714. SdRk32pCreateChild (
  1715. PSD_RK32_CONTEXT Device
  1716. )
  1717. /*++
  1718. Routine Description:
  1719. This routine creates an SD child context.
  1720. Arguments:
  1721. Device - Supplies a pointer to the parent device to which the child belongs.
  1722. Return Value:
  1723. Returns a pointer to the new child on success or NULL on failure.
  1724. --*/
  1725. {
  1726. PSD_RK32_CHILD Child;
  1727. Child = MmAllocateNonPagedPool(sizeof(SD_RK32_CHILD), SD_ALLOCATION_TAG);
  1728. if (Child == NULL) {
  1729. return NULL;
  1730. }
  1731. RtlZeroMemory(Child, sizeof(SD_RK32_CHILD));
  1732. Child->Type = SdRk32Child;
  1733. Child->Parent = Device;
  1734. Child->Controller = Device->Controller;
  1735. Child->ControllerLock = Device->Lock;
  1736. Child->ReferenceCount = 1;
  1737. return Child;
  1738. }
  1739. VOID
  1740. SdRk32pDestroyChild (
  1741. PSD_RK32_CHILD Child
  1742. )
  1743. /*++
  1744. Routine Description:
  1745. This routine destroys the given SD child device.
  1746. Arguments:
  1747. Child - Supplies a pointer to the SD child device to destroy.
  1748. Return Value:
  1749. None.
  1750. --*/
  1751. {
  1752. ASSERT(Child->DiskInterface.DiskToken == NULL);
  1753. ASSERT(Child->Irp == NULL);
  1754. MmFreeNonPagedPool(Child);
  1755. return;
  1756. }
  1757. VOID
  1758. SdRk32pChildAddReference (
  1759. PSD_RK32_CHILD Child
  1760. )
  1761. /*++
  1762. Routine Description:
  1763. This routine adds a reference to SD child device.
  1764. Arguments:
  1765. Child - Supplies a pointer to the SD child device.
  1766. Return Value:
  1767. None.
  1768. --*/
  1769. {
  1770. ULONG OldReferenceCount;
  1771. OldReferenceCount = RtlAtomicAdd32(&(Child->ReferenceCount), 1);
  1772. ASSERT((OldReferenceCount != 0) && (OldReferenceCount < 0x10000000));
  1773. return;
  1774. }
  1775. VOID
  1776. SdRk32pChildReleaseReference (
  1777. PSD_RK32_CHILD Child
  1778. )
  1779. /*++
  1780. Routine Description:
  1781. This routine releases a reference from the SD child.
  1782. Arguments:
  1783. Child - Supplies a pointer to the SD child.
  1784. Return Value:
  1785. None.
  1786. --*/
  1787. {
  1788. ULONG OldReferenceCount;
  1789. OldReferenceCount = RtlAtomicAdd32(&(Child->ReferenceCount), (ULONG)-1);
  1790. ASSERT((OldReferenceCount != 0) && (OldReferenceCount < 0x10000000));
  1791. if (OldReferenceCount == 1) {
  1792. SdRk32pDestroyChild(Child);
  1793. }
  1794. return;
  1795. }
  1796. KSTATUS
  1797. SdRk32ChildBlockIoReset (
  1798. PVOID DiskToken
  1799. )
  1800. /*++
  1801. Routine Description:
  1802. This routine must be called immediately before using the block read and
  1803. write routines in order to allow the disk to reset any I/O channels in
  1804. preparation for imminent block I/O. This routine is called at high run
  1805. level.
  1806. Arguments:
  1807. DiskToken - Supplies an opaque token for the disk. The appropriate token is
  1808. retrieved by querying the disk device information.
  1809. Return Value:
  1810. Status code.
  1811. --*/
  1812. {
  1813. PSD_RK32_CHILD Child;
  1814. KSTATUS Status;
  1815. ULONG Value;
  1816. ASSERT(KeGetRunLevel() == RunLevelHigh);
  1817. Child = (PSD_RK32_CHILD)DiskToken;
  1818. //
  1819. // Put the SD controller into critical execution mode.
  1820. //
  1821. SdSetCriticalMode(Child->Controller, TRUE);
  1822. //
  1823. // Abort any current transaction that might have been left incomplete
  1824. // when the crash occurred.
  1825. //
  1826. Status = SdAbortTransaction(Child->Controller, FALSE);
  1827. if (!KSUCCESS(Status)) {
  1828. return Status;
  1829. }
  1830. //
  1831. // Make sure the controller is not stuck in DMA transfer mode.
  1832. //
  1833. //
  1834. // Make sure DMA mode is disabled.
  1835. //
  1836. Value = SD_DWC_READ_REGISTER(Child->Parent, SdDwcControl);
  1837. if ((Value & SD_DWC_CONTROL_USE_INTERNAL_DMAC) != 0) {
  1838. Value &= ~SD_DWC_CONTROL_USE_INTERNAL_DMAC;
  1839. SD_DWC_WRITE_REGISTER(Child->Parent, SdDwcControl, Value);
  1840. }
  1841. return Status;
  1842. }
  1843. KSTATUS
  1844. SdRk32ChildBlockIoRead (
  1845. PVOID DiskToken,
  1846. PIO_BUFFER IoBuffer,
  1847. ULONGLONG BlockAddress,
  1848. UINTN BlockCount,
  1849. PUINTN BlocksCompleted
  1850. )
  1851. /*++
  1852. Routine Description:
  1853. This routine reads the block contents from the disk into the given I/O
  1854. buffer using polled I/O. It does so without acquiring any locks or
  1855. allocating any resources, as this routine is used for crash dump support
  1856. when the system is in a very fragile state. This routine must be called at
  1857. high level.
  1858. Arguments:
  1859. DiskToken - Supplies an opaque token for the disk. The appropriate token is
  1860. retrieved by querying the disk device information.
  1861. IoBuffer - Supplies a pointer to the I/O buffer where the data will be read.
  1862. BlockAddress - Supplies the block index to read (for physical disk, this is
  1863. the LBA).
  1864. BlockCount - Supplies the number of blocks to read.
  1865. BlocksCompleted - Supplies a pointer that receives the total number of
  1866. blocks read.
  1867. Return Value:
  1868. Status code.
  1869. --*/
  1870. {
  1871. PSD_RK32_CHILD Child;
  1872. IRP_READ_WRITE IrpReadWrite;
  1873. KSTATUS Status;
  1874. ASSERT(KeGetRunLevel() == RunLevelHigh);
  1875. Child = (PSD_RK32_CHILD)DiskToken;
  1876. IrpReadWrite.IoBuffer = IoBuffer;
  1877. IrpReadWrite.IoOffset = BlockAddress << Child->BlockShift;
  1878. IrpReadWrite.IoSizeInBytes = BlockCount << Child->BlockShift;
  1879. //
  1880. // As this read routine is meant for critical code paths (crash dump),
  1881. // indicate that the channel should not be locked when performing the I/O.
  1882. // It may be that some other thread holds the lock, which would cause a
  1883. // dead lock as all other processors and threads are likely frozen.
  1884. //
  1885. Status = SdRk32PerformIoPolled(&IrpReadWrite, Child, FALSE, FALSE);
  1886. *BlocksCompleted = IrpReadWrite.IoBytesCompleted >> Child->BlockShift;
  1887. return Status;
  1888. }
  1889. KSTATUS
  1890. SdRk32ChildBlockIoWrite (
  1891. PVOID DiskToken,
  1892. PIO_BUFFER IoBuffer,
  1893. ULONGLONG BlockAddress,
  1894. UINTN BlockCount,
  1895. PUINTN BlocksCompleted
  1896. )
  1897. /*++
  1898. Routine Description:
  1899. This routine writes the contents of the given I/O buffer to the disk using
  1900. polled I/O. It does so without acquiring any locks or allocating any
  1901. resources, as this routine is used for crash dump support when the system
  1902. is in a very fragile state. This routine must be called at high level.
  1903. Arguments:
  1904. DiskToken - Supplies an opaque token for the disk. The appropriate token is
  1905. retrieved by querying the disk device information.
  1906. IoBuffer - Supplies a pointer to the I/O buffer containing the data to
  1907. write.
  1908. BlockAddress - Supplies the block index to write to (for physical disk,
  1909. this is the LBA).
  1910. BlockCount - Supplies the number of blocks to write.
  1911. BlocksCompleted - Supplies a pointer that receives the total number of
  1912. blocks written.
  1913. Return Value:
  1914. Status code.
  1915. --*/
  1916. {
  1917. PSD_RK32_CHILD Child;
  1918. IRP_READ_WRITE IrpReadWrite;
  1919. KSTATUS Status;
  1920. ASSERT(KeGetRunLevel() == RunLevelHigh);
  1921. Child = (PSD_RK32_CHILD)DiskToken;
  1922. IrpReadWrite.IoBuffer = IoBuffer;
  1923. IrpReadWrite.IoOffset = BlockAddress << Child->BlockShift;
  1924. IrpReadWrite.IoSizeInBytes = BlockCount << Child->BlockShift;
  1925. //
  1926. // As this write routine is meant for critical code paths (crash dump),
  1927. // indicate that the channel should not be locked when performing the I/O.
  1928. // It may be that some other thread holds the lock, which would cause a
  1929. // dead lock as all other processors and threads are likely frozen.
  1930. //
  1931. Status = SdRk32PerformIoPolled(&IrpReadWrite, Child, TRUE, FALSE);
  1932. *BlocksCompleted = IrpReadWrite.IoBytesCompleted >> Child->BlockShift;
  1933. return Status;
  1934. }
  1935. KSTATUS
  1936. SdRk32PerformIoPolled (
  1937. PIRP_READ_WRITE IrpReadWrite,
  1938. PSD_RK32_CHILD Child,
  1939. BOOL Write,
  1940. BOOL LockRequired
  1941. )
  1942. /*++
  1943. Routine Description:
  1944. This routine performs polled I/O data transfers.
  1945. Arguments:
  1946. IrpReadWrite - Supplies a pointer to the IRP read/write context.
  1947. Child - Supplies a pointer to the SD child device.
  1948. Write - Supplies a boolean indicating if this is a read operation (TRUE) or
  1949. a write operation (FALSE).
  1950. LockRequired - Supplies a boolean indicating if this operation requires the
  1951. child's controller lock to be acquired (TRUE) or not (FALSE).
  1952. Return Value:
  1953. None.
  1954. --*/
  1955. {
  1956. UINTN BlockCount;
  1957. ULONGLONG BlockOffset;
  1958. UINTN BytesRemaining;
  1959. UINTN BytesThisRound;
  1960. KSTATUS CompletionStatus;
  1961. PSD_CONTROLLER Controller;
  1962. PIO_BUFFER_FRAGMENT Fragment;
  1963. UINTN FragmentIndex;
  1964. UINTN FragmentOffset;
  1965. PIO_BUFFER IoBuffer;
  1966. UINTN IoBufferOffset;
  1967. ULONG IrpReadWriteFlags;
  1968. BOOL LockHeld;
  1969. BOOL ReadWriteIrpPrepared;
  1970. KSTATUS Status;
  1971. PVOID VirtualAddress;
  1972. IrpReadWrite->IoBytesCompleted = 0;
  1973. LockHeld = FALSE;
  1974. ReadWriteIrpPrepared = FALSE;
  1975. ASSERT(IrpReadWrite->IoBuffer != NULL);
  1976. ASSERT(Child->Type == SdRk32Child);
  1977. ASSERT((Child->BlockCount != 0) && (Child->BlockShift != 0));
  1978. Controller = Child->Controller;
  1979. //
  1980. // Validate the supplied I/O buffer is aligned and big enough.
  1981. //
  1982. IrpReadWriteFlags = IRP_READ_WRITE_FLAG_POLLED;
  1983. if (Write != FALSE) {
  1984. IrpReadWriteFlags |= IRP_READ_WRITE_FLAG_WRITE;
  1985. }
  1986. Status = IoPrepareReadWriteIrp(IrpReadWrite,
  1987. 1 << Child->BlockShift,
  1988. 0,
  1989. MAX_ULONGLONG,
  1990. IrpReadWriteFlags);
  1991. if (!KSUCCESS(Status)) {
  1992. goto PerformBlockIoPolledEnd;
  1993. }
  1994. ReadWriteIrpPrepared = TRUE;
  1995. //
  1996. // Make sure the I/O buffer is mapped before use. SD depends on the buffer
  1997. // being mapped.
  1998. //
  1999. IoBuffer = IrpReadWrite->IoBuffer;
  2000. Status = MmMapIoBuffer(IoBuffer, FALSE, FALSE, FALSE);
  2001. if (!KSUCCESS(Status)) {
  2002. goto PerformBlockIoPolledEnd;
  2003. }
  2004. //
  2005. // Find the starting fragment based on the current offset.
  2006. //
  2007. IoBufferOffset = MmGetIoBufferCurrentOffset(IoBuffer);
  2008. FragmentIndex = 0;
  2009. FragmentOffset = 0;
  2010. while (IoBufferOffset != 0) {
  2011. ASSERT(FragmentIndex < IoBuffer->FragmentCount);
  2012. Fragment = &(IoBuffer->Fragment[FragmentIndex]);
  2013. if (IoBufferOffset < Fragment->Size) {
  2014. FragmentOffset = IoBufferOffset;
  2015. break;
  2016. }
  2017. IoBufferOffset -= Fragment->Size;
  2018. FragmentIndex += 1;
  2019. }
  2020. if (LockRequired != FALSE) {
  2021. KeAcquireQueuedLock(Child->ControllerLock);
  2022. LockHeld = TRUE;
  2023. }
  2024. if (((Controller->Flags & SD_CONTROLLER_FLAG_MEDIA_PRESENT) == 0) ||
  2025. ((Controller->Flags & SD_CONTROLLER_FLAG_MEDIA_CHANGED) != 0)) {
  2026. Status = STATUS_NO_MEDIA;
  2027. if ((Controller->Flags & SD_CONTROLLER_FLAG_MEDIA_CHANGED) != 0) {
  2028. Status = STATUS_MEDIA_CHANGED;
  2029. }
  2030. goto PerformBlockIoPolledEnd;
  2031. }
  2032. //
  2033. // Loop reading in or writing out each fragment in the I/O buffer.
  2034. //
  2035. BytesRemaining = IrpReadWrite->IoSizeInBytes;
  2036. ASSERT(IS_ALIGNED(BytesRemaining, 1 << Child->BlockShift) != FALSE);
  2037. ASSERT(IS_ALIGNED(IrpReadWrite->IoOffset, 1 << Child->BlockShift) != FALSE);
  2038. BlockOffset = IrpReadWrite->IoOffset >> Child->BlockShift;
  2039. while (BytesRemaining != 0) {
  2040. ASSERT(FragmentIndex < IoBuffer->FragmentCount);
  2041. Fragment = &(IoBuffer->Fragment[FragmentIndex]);
  2042. VirtualAddress = Fragment->VirtualAddress + FragmentOffset;
  2043. BytesThisRound = Fragment->Size - FragmentOffset;
  2044. if (BytesRemaining < BytesThisRound) {
  2045. BytesThisRound = BytesRemaining;
  2046. }
  2047. ASSERT(IS_ALIGNED(BytesThisRound, (1 << Child->BlockShift)) != FALSE);
  2048. BlockCount = BytesThisRound >> Child->BlockShift;
  2049. //
  2050. // Make sure the system isn't trying to do I/O off the end of the disk.
  2051. //
  2052. ASSERT(BlockOffset < Child->BlockCount);
  2053. ASSERT(BlockCount >= 1);
  2054. Status = SdBlockIoPolled(Controller,
  2055. BlockOffset,
  2056. BlockCount,
  2057. VirtualAddress,
  2058. Write);
  2059. if (!KSUCCESS(Status)) {
  2060. goto PerformBlockIoPolledEnd;
  2061. }
  2062. BlockOffset += BlockCount;
  2063. BytesRemaining -= BytesThisRound;
  2064. IrpReadWrite->IoBytesCompleted += BytesThisRound;
  2065. FragmentOffset += BytesThisRound;
  2066. if (FragmentOffset >= Fragment->Size) {
  2067. FragmentIndex += 1;
  2068. FragmentOffset = 0;
  2069. }
  2070. }
  2071. Status = STATUS_SUCCESS;
  2072. PerformBlockIoPolledEnd:
  2073. if (LockHeld != FALSE) {
  2074. KeReleaseQueuedLock(Child->ControllerLock);
  2075. }
  2076. if (ReadWriteIrpPrepared != FALSE) {
  2077. CompletionStatus = IoCompleteReadWriteIrp(IrpReadWrite,
  2078. IrpReadWriteFlags);
  2079. if (!KSUCCESS(CompletionStatus) && KSUCCESS(Status)) {
  2080. Status = CompletionStatus;
  2081. }
  2082. }
  2083. IrpReadWrite->NewIoOffset = IrpReadWrite->IoOffset +
  2084. IrpReadWrite->IoBytesCompleted;
  2085. return Status;
  2086. }
  2087. KSTATUS
  2088. SdRk32InitializeDma (
  2089. PSD_RK32_CONTEXT Device
  2090. )
  2091. /*++
  2092. Routine Description:
  2093. This routine initializes DMA support in the RK32 host controller.
  2094. Arguments:
  2095. Device - Supplies a pointer to the RK32xx SD device.
  2096. Return Value:
  2097. Status code.
  2098. --*/
  2099. {
  2100. PSD_CONTROLLER Controller;
  2101. PSD_DWC_DMA_DESCRIPTOR Descriptor;
  2102. ULONG IoBufferFlags;
  2103. ULONG Value;
  2104. Controller = Device->Controller;
  2105. if ((Controller->Flags & SD_CONTROLLER_FLAG_MEDIA_CHANGED) != 0) {
  2106. return STATUS_MEDIA_CHANGED;
  2107. } else if ((Controller->Flags & SD_CONTROLLER_FLAG_MEDIA_PRESENT) == 0) {
  2108. return STATUS_NO_MEDIA;
  2109. }
  2110. if ((Controller->HostCapabilities & SD_MODE_AUTO_CMD12) == 0) {
  2111. return STATUS_NOT_SUPPORTED;
  2112. }
  2113. //
  2114. // Create the DMA descriptor table if not already done.
  2115. //
  2116. if (Controller->DmaDescriptorTable == NULL) {
  2117. IoBufferFlags = IO_BUFFER_FLAG_PHYSICALLY_CONTIGUOUS |
  2118. IO_BUFFER_FLAG_MAP_NON_CACHED;
  2119. Controller->DmaDescriptorTable = MmAllocateNonPagedIoBuffer(
  2120. 0,
  2121. MAX_ULONG,
  2122. 4,
  2123. SD_RK32_DMA_DESCRIPTOR_TABLE_SIZE,
  2124. IoBufferFlags);
  2125. if (Controller->DmaDescriptorTable == NULL) {
  2126. return STATUS_INSUFFICIENT_RESOURCES;
  2127. }
  2128. ASSERT(Controller->DmaDescriptorTable->FragmentCount == 1);
  2129. }
  2130. Descriptor = Controller->DmaDescriptorTable->Fragment[0].VirtualAddress;
  2131. RtlZeroMemory(Descriptor, SD_RK32_DMA_DESCRIPTOR_TABLE_SIZE);
  2132. //
  2133. // Enable DMA in the control register.
  2134. //
  2135. Value = SD_DWC_READ_REGISTER(Device, SdDwcControl);
  2136. Value |= SD_DWC_CONTROL_DMA_ENABLE;
  2137. SD_DWC_WRITE_REGISTER(Device, SdDwcControl, Value);
  2138. //
  2139. // Read it to make sure the write stuck.
  2140. //
  2141. Value = SD_DWC_READ_REGISTER(Device, SdDwcControl);
  2142. if ((Value & SD_DWC_CONTROL_DMA_ENABLE) == 0) {
  2143. return STATUS_NOT_SUPPORTED;
  2144. }
  2145. //
  2146. // Enable internal DMA in the bus mode register.
  2147. //
  2148. Value = SD_DWC_READ_REGISTER(Device, SdDwcBusMode);
  2149. Value |= SD_DWC_BUS_MODE_IDMAC_ENABLE;
  2150. SD_DWC_WRITE_REGISTER(Device, SdDwcBusMode, Value);
  2151. //
  2152. // Read it to make sure the write stuck.
  2153. //
  2154. Value = SD_DWC_READ_REGISTER(Device, SdDwcBusMode);
  2155. if ((Value & SD_DWC_BUS_MODE_IDMAC_ENABLE) == 0) {
  2156. return STATUS_NOT_SUPPORTED;
  2157. }
  2158. return STATUS_SUCCESS;
  2159. }
  2160. VOID
  2161. SdRk32BlockIoDma (
  2162. PSD_RK32_CONTEXT Device,
  2163. ULONGLONG BlockOffset,
  2164. UINTN BlockCount,
  2165. PIO_BUFFER IoBuffer,
  2166. UINTN IoBufferOffset,
  2167. BOOL Write,
  2168. PSD_IO_COMPLETION_ROUTINE CompletionRoutine,
  2169. PVOID CompletionContext
  2170. )
  2171. /*++
  2172. Routine Description:
  2173. This routine performs a block I/O read or write using standard ADMA2.
  2174. Arguments:
  2175. Device - Supplies a pointer to the RK32xx controller device.
  2176. BlockOffset - Supplies the logical block address of the I/O.
  2177. BlockCount - Supplies the number of blocks to read or write.
  2178. IoBuffer - Supplies a pointer to the buffer containing the data to write
  2179. or where the read data should be returned.
  2180. IoBufferOffset - Supplies the offset from the beginning of the I/O buffer
  2181. where this I/O should begin. This is relative to the I/O buffer's
  2182. current offset.
  2183. Write - Supplies a boolean indicating if this is a read operation (FALSE)
  2184. or a write operation.
  2185. CompletionRoutine - Supplies a pointer to a function to call when the I/O
  2186. completes.
  2187. CompletionContext - Supplies a context pointer to pass as a parameter to
  2188. the completion routine.
  2189. Return Value:
  2190. None. The status of the operation is returned when the completion routine
  2191. is called, which may be during the execution of this function in the case
  2192. of an early failure.
  2193. --*/
  2194. {
  2195. ULONG BlockLength;
  2196. SD_COMMAND Command;
  2197. PSD_CONTROLLER Controller;
  2198. ULONG DescriptorCount;
  2199. PHYSICAL_ADDRESS DescriptorPhysical;
  2200. UINTN DescriptorSize;
  2201. PSD_DWC_DMA_DESCRIPTOR DmaDescriptor;
  2202. PIO_BUFFER DmaDescriptorTable;
  2203. PIO_BUFFER_FRAGMENT Fragment;
  2204. UINTN FragmentIndex;
  2205. UINTN FragmentOffset;
  2206. PHYSICAL_ADDRESS PhysicalAddress;
  2207. KSTATUS Status;
  2208. ULONG TableAddress;
  2209. UINTN TransferSize;
  2210. UINTN TransferSizeRemaining;
  2211. ULONG Value;
  2212. ASSERT(BlockCount != 0);
  2213. Controller = Device->Controller;
  2214. if ((Controller->Flags & SD_CONTROLLER_FLAG_MEDIA_CHANGED) != 0) {
  2215. Status = STATUS_MEDIA_CHANGED;
  2216. goto BlockIoDmaEnd;
  2217. } else if ((Controller->Flags & SD_CONTROLLER_FLAG_MEDIA_PRESENT) == 0) {
  2218. Status = STATUS_NO_MEDIA;
  2219. goto BlockIoDmaEnd;
  2220. }
  2221. if (Write != FALSE) {
  2222. if (BlockCount > 1) {
  2223. Command.Command = SdCommandWriteMultipleBlocks;
  2224. } else {
  2225. Command.Command = SdCommandWriteSingleBlock;
  2226. }
  2227. BlockLength = Controller->WriteBlockLength;
  2228. TransferSize = BlockCount * BlockLength;
  2229. ASSERT(TransferSize != 0);
  2230. } else {
  2231. if (BlockCount > 1) {
  2232. Command.Command = SdCommandReadMultipleBlocks;
  2233. } else {
  2234. Command.Command = SdCommandReadSingleBlock;
  2235. }
  2236. BlockLength = Controller->ReadBlockLength;
  2237. TransferSize = BlockCount * BlockLength;
  2238. ASSERT(TransferSize != 0);
  2239. }
  2240. //
  2241. // Get to the correct spot in the I/O buffer.
  2242. //
  2243. IoBufferOffset += MmGetIoBufferCurrentOffset(IoBuffer);
  2244. FragmentIndex = 0;
  2245. FragmentOffset = 0;
  2246. while (IoBufferOffset != 0) {
  2247. ASSERT(FragmentIndex < IoBuffer->FragmentCount);
  2248. Fragment = &(IoBuffer->Fragment[FragmentIndex]);
  2249. if (IoBufferOffset < Fragment->Size) {
  2250. FragmentOffset = IoBufferOffset;
  2251. break;
  2252. }
  2253. IoBufferOffset -= Fragment->Size;
  2254. FragmentIndex += 1;
  2255. }
  2256. //
  2257. // Do a DMA reset.
  2258. //
  2259. Value = SD_DWC_READ_REGISTER(Device, SdDwcControl);
  2260. Value |= SD_DWC_CONTROL_DMA_RESET;
  2261. SD_DWC_WRITE_REGISTER(Device, SdDwcControl, Value);
  2262. do {
  2263. Value = SD_DWC_READ_REGISTER(Device, SdDwcControl);
  2264. } while ((Value & SD_DWC_CONTROL_DMA_RESET) != 0);
  2265. Value = SD_DWC_READ_REGISTER(Device, SdDwcBusMode);
  2266. Value |= SD_DWC_BUS_MODE_INTERNAL_DMA_RESET;
  2267. SD_DWC_WRITE_REGISTER(Device, SdDwcBusMode, Value);
  2268. //
  2269. // Fill out the DMA descriptors.
  2270. //
  2271. DmaDescriptorTable = Controller->DmaDescriptorTable;
  2272. DmaDescriptor = DmaDescriptorTable->Fragment[0].VirtualAddress;
  2273. DescriptorPhysical = DmaDescriptorTable->Fragment[0].PhysicalAddress;
  2274. DescriptorCount = 0;
  2275. TransferSizeRemaining = TransferSize;
  2276. while ((TransferSizeRemaining != 0) &&
  2277. (DescriptorCount < SD_RK32_DMA_DESCRIPTOR_COUNT - 1)) {
  2278. ASSERT(FragmentIndex < IoBuffer->FragmentCount);
  2279. Fragment = &(IoBuffer->Fragment[FragmentIndex]);
  2280. //
  2281. // This descriptor size is going to the the minimum of the total
  2282. // remaining size, the size that can fit in a DMA descriptor, and the
  2283. // remaining size of the fragment.
  2284. //
  2285. DescriptorSize = TransferSizeRemaining;
  2286. if (DescriptorSize > SD_DWC_DMA_DESCRIPTOR_MAX_BUFFER_SIZE) {
  2287. DescriptorSize = SD_DWC_DMA_DESCRIPTOR_MAX_BUFFER_SIZE;
  2288. }
  2289. if (DescriptorSize > (Fragment->Size - FragmentOffset)) {
  2290. DescriptorSize = Fragment->Size - FragmentOffset;
  2291. }
  2292. TransferSizeRemaining -= DescriptorSize;
  2293. PhysicalAddress = Fragment->PhysicalAddress + FragmentOffset;
  2294. //
  2295. // Assert that the buffer is within the first 4GB.
  2296. //
  2297. ASSERT(((ULONG)PhysicalAddress == PhysicalAddress) &&
  2298. ((ULONG)(PhysicalAddress + DescriptorSize) ==
  2299. PhysicalAddress + DescriptorSize));
  2300. DmaDescriptor->Address = PhysicalAddress;
  2301. DmaDescriptor->Size = DescriptorSize;
  2302. DmaDescriptor->Control =
  2303. SD_DWC_DMA_DESCRIPTOR_CONTROL_OWN |
  2304. SD_DWC_DMA_DESCRIPTOR_CONTROL_SECOND_ADDRESS_CHAINED |
  2305. SD_DWC_DMA_DESCRIPTOR_CONTROL_DISABLE_INTERRUPT_ON_COMPLETION;
  2306. if (DescriptorCount == 0) {
  2307. DmaDescriptor->Control |=
  2308. SD_DWC_DMA_DESCRIPTOR_CONTROL_FIRST_DESCRIPTOR;
  2309. }
  2310. DescriptorPhysical += sizeof(SD_DWC_DMA_DESCRIPTOR);
  2311. DmaDescriptor->NextDescriptor = DescriptorPhysical;
  2312. DmaDescriptor += 1;
  2313. DescriptorCount += 1;
  2314. FragmentOffset += DescriptorSize;
  2315. if (FragmentOffset >= Fragment->Size) {
  2316. FragmentIndex += 1;
  2317. FragmentOffset = 0;
  2318. }
  2319. }
  2320. //
  2321. // Mark the last DMA descriptor as the end of the transfer.
  2322. //
  2323. DmaDescriptor -= 1;
  2324. DmaDescriptor->Control &=
  2325. ~(SD_DWC_DMA_DESCRIPTOR_CONTROL_SECOND_ADDRESS_CHAINED |
  2326. SD_DWC_DMA_DESCRIPTOR_CONTROL_DISABLE_INTERRUPT_ON_COMPLETION);
  2327. DmaDescriptor->Control |= SD_DWC_DMA_DESCRIPTOR_CONTROL_LAST_DESCRIPTOR;
  2328. DmaDescriptor->NextDescriptor = 0;
  2329. RtlMemoryBarrier();
  2330. Command.ResponseType = SD_RESPONSE_R1;
  2331. if ((Controller->Flags & SD_CONTROLLER_FLAG_HIGH_CAPACITY) != 0) {
  2332. Command.CommandArgument = BlockOffset;
  2333. } else {
  2334. Command.CommandArgument = BlockOffset * BlockLength;
  2335. }
  2336. ASSERT((TransferSize - TransferSizeRemaining) <= MAX_ULONG);
  2337. Command.BufferSize = (ULONG)(TransferSize - TransferSizeRemaining);
  2338. Command.BufferVirtual = NULL;
  2339. Command.BufferPhysical = INVALID_PHYSICAL_ADDRESS;
  2340. Command.Write = Write;
  2341. Command.Dma = TRUE;
  2342. Controller->IoCompletionRoutine = CompletionRoutine;
  2343. Controller->IoCompletionContext = CompletionContext;
  2344. Controller->IoRequestSize = Command.BufferSize;
  2345. //
  2346. // Write the table base, enable DMA, and write the poll demand to get it
  2347. // moving.
  2348. //
  2349. TableAddress = (ULONG)(DmaDescriptorTable->Fragment[0].PhysicalAddress);
  2350. SD_DWC_WRITE_REGISTER(Device, SdDwcDescriptorBaseAddress, TableAddress);
  2351. Value = SD_DWC_READ_REGISTER(Device, SdDwcControl);
  2352. Value |= SD_DWC_CONTROL_USE_INTERNAL_DMAC | SD_DWC_CONTROL_DMA_ENABLE;
  2353. SD_DWC_WRITE_REGISTER(Device, SdDwcControl, Value);
  2354. Value = SD_DWC_READ_REGISTER(Device, SdDwcBusMode);
  2355. Value |= SD_DWC_BUS_MODE_IDMAC_ENABLE | SD_DWC_BUS_MODE_FIXED_BURST;
  2356. SD_DWC_WRITE_REGISTER(Device, SdDwcBusMode, Value);
  2357. SD_DWC_WRITE_REGISTER(Device, SdDwcPollDemand, 1);
  2358. Status = Controller->FunctionTable.SendCommand(Controller,
  2359. Controller->ConsumerContext,
  2360. &Command);
  2361. if (!KSUCCESS(Status)) {
  2362. Controller->IoCompletionRoutine = NULL;
  2363. Controller->IoCompletionContext = NULL;
  2364. Controller->IoRequestSize = 0;
  2365. goto BlockIoDmaEnd;
  2366. }
  2367. Status = STATUS_SUCCESS;
  2368. BlockIoDmaEnd:
  2369. //
  2370. // If this routine failed, call the completion routine back immediately.
  2371. //
  2372. if (!KSUCCESS(Status)) {
  2373. CompletionRoutine(Controller, CompletionContext, 0, Status);
  2374. }
  2375. return;
  2376. }
  2377. KSTATUS
  2378. SdRk32InitializeController (
  2379. PSD_CONTROLLER Controller,
  2380. PVOID Context,
  2381. ULONG Phase
  2382. )
  2383. /*++
  2384. Routine Description:
  2385. This routine performs any controller specific initialization steps.
  2386. Arguments:
  2387. Controller - Supplies a pointer to the controller.
  2388. Context - Supplies a context pointer passed to the SD/MMC library upon
  2389. creation of the controller.
  2390. Phase - Supplies the phase of initialization. Phase 0 happens after the
  2391. initial software reset and Phase 1 happens after the bus width has been
  2392. set to 1 and the speed to 400KHz.
  2393. Return Value:
  2394. Status code.
  2395. --*/
  2396. {
  2397. PSD_RK32_CONTEXT Device;
  2398. ULONG Mask;
  2399. KSTATUS Status;
  2400. ULONG Value;
  2401. ULONG Voltage;
  2402. Device = (PSD_RK32_CONTEXT)Context;
  2403. //
  2404. // Phase 0 is an early initialization phase that happens after the
  2405. // controller has been reset. It is used to gather capabilities and set
  2406. // certain parameters in the hardware.
  2407. //
  2408. if (Phase == 0) {
  2409. Mask = SD_DWC_CONTROL_FIFO_RESET | SD_DWC_CONTROL_CONTROLLER_RESET;
  2410. SD_DWC_WRITE_REGISTER(Device, SdDwcControl, Mask);
  2411. do {
  2412. Value = SD_DWC_READ_REGISTER(Device, SdDwcControl);
  2413. } while ((Value & Mask) != 0);
  2414. //
  2415. // Set the default burst length.
  2416. //
  2417. Value = (SD_DWC_BUS_MODE_BURST_LENGTH_16 <<
  2418. SD_DWC_BUS_MODE_BURST_LENGTH_SHIFT) |
  2419. SD_DWC_BUS_MODE_FIXED_BURST;
  2420. SD_DWC_WRITE_REGISTER(Device, SdDwcBusMode, Value);
  2421. //
  2422. // Set the default FIFO threshold.
  2423. //
  2424. SD_DWC_WRITE_REGISTER(Device,
  2425. SdDwcFifoThreshold,
  2426. SD_DWC_FIFO_THRESHOLD_DEFAULT);
  2427. //
  2428. // Set the default timeout.
  2429. //
  2430. SD_DWC_WRITE_REGISTER(Device, SdDwcTimeout, SD_DWC_TIMEOUT_DEFAULT);
  2431. //
  2432. // Set the voltages based on the supported values supplied when the
  2433. // controller was created.
  2434. //
  2435. Voltage = SD_DWC_READ_REGISTER(Device, SdDwcUhs);
  2436. Voltage &= ~SD_DWC_UHS_VOLTAGE_MASK;
  2437. if ((Controller->Voltages & (SD_VOLTAGE_32_33 | SD_VOLTAGE_33_34)) ==
  2438. (SD_VOLTAGE_32_33 | SD_VOLTAGE_33_34)) {
  2439. Voltage |= SD_DWC_UHS_VOLTAGE_3V3;
  2440. } else if ((Controller->Voltages &
  2441. (SD_VOLTAGE_165_195 | SD_VOLTAGE_18)) != 0) {
  2442. Voltage |= SD_DWC_UHS_VOLTAGE_1V8;
  2443. } else {
  2444. Status = STATUS_DEVICE_NOT_CONNECTED;
  2445. goto InitializeControllerEnd;
  2446. }
  2447. SD_DWC_WRITE_REGISTER(Device, SdDwcUhs, Voltage);
  2448. //
  2449. // Phase 1 happens right before the initialization command sequence is
  2450. // about to begin. The clock and bus width have been program and the device
  2451. // is just about read to go.
  2452. //
  2453. } else if (Phase == 1) {
  2454. //
  2455. // Turn on the power.
  2456. //
  2457. SD_DWC_WRITE_REGISTER(Device, SdDwcPower, SD_DWC_POWER_ENABLE);
  2458. //
  2459. // Set the interrupt mask, clear any pending state, and enable the
  2460. // interrupts.
  2461. //
  2462. Controller->EnabledInterrupts = SD_DWC_INTERRUPT_DEFAULT_MASK;
  2463. SD_DWC_WRITE_REGISTER(Device,
  2464. SdDwcInterruptMask,
  2465. SD_DWC_INTERRUPT_DEFAULT_MASK);
  2466. SD_DWC_WRITE_REGISTER(Device,
  2467. SdDwcInterruptStatus,
  2468. SD_DWC_INTERRUPT_STATUS_ALL_MASK);
  2469. Value = SD_DWC_READ_REGISTER(Device, SdDwcControl);
  2470. Value |= SD_DWC_CONTROL_INTERRUPT_ENABLE;
  2471. SD_DWC_WRITE_REGISTER(Device, SdDwcControl, Value);
  2472. }
  2473. Status = STATUS_SUCCESS;
  2474. InitializeControllerEnd:
  2475. return Status;
  2476. }
  2477. KSTATUS
  2478. SdRk32ResetController (
  2479. PSD_CONTROLLER Controller,
  2480. PVOID Context,
  2481. ULONG Flags
  2482. )
  2483. /*++
  2484. Routine Description:
  2485. This routine performs a soft reset of the SD controller.
  2486. Arguments:
  2487. Controller - Supplies a pointer to the controller.
  2488. Context - Supplies a context pointer passed to the SD/MMC library upon
  2489. creation of the controller.
  2490. Flags - Supplies a bitmask of reset flags. See SD_RESET_FLAG_* for
  2491. definitions.
  2492. Return Value:
  2493. Status code.
  2494. --*/
  2495. {
  2496. ULONG BusMode;
  2497. ULONG CardType;
  2498. ULONG Control;
  2499. PSD_RK32_CONTEXT Device;
  2500. ULONGLONG Frequency;
  2501. ULONG ResetMask;
  2502. KSTATUS Status;
  2503. ULONGLONG Timeout;
  2504. ULONG Value;
  2505. Device = (PSD_RK32_CONTEXT)Context;
  2506. Device->InVoltageSwitch = FALSE;
  2507. Frequency = HlQueryTimeCounterFrequency();
  2508. ResetMask = SD_DWC_CONTROL_FIFO_RESET |
  2509. SD_DWC_CONTROL_DMA_RESET |
  2510. SD_DWC_CONTROL_CONTROLLER_RESET;
  2511. if ((Flags & SD_RESET_FLAG_ALL) != 0) {
  2512. //
  2513. // Power cycle the card.
  2514. //
  2515. SD_DWC_WRITE_REGISTER(Device, SdDwcPower, 0);
  2516. HlBusySpin(10000);
  2517. SdRk32SetRegulatorVoltage(Device, FALSE);
  2518. SD_DWC_WRITE_REGISTER(Device, SdDwcPower, SD_DWC_POWER_ENABLE);
  2519. HlBusySpin(10000);
  2520. }
  2521. CardType = SD_DWC_READ_REGISTER(Device, SdDwcCardType);
  2522. Control = SD_DWC_READ_REGISTER(Device, SdDwcControl);
  2523. Value = (Control | ResetMask) &
  2524. ~(SD_DWC_CONTROL_DMA_ENABLE |
  2525. SD_DWC_CONTROL_USE_INTERNAL_DMAC);
  2526. SD_DWC_WRITE_REGISTER(Device, SdDwcControl, Value);
  2527. Status = STATUS_TIMEOUT;
  2528. Timeout = SdQueryTimeCounter(Controller) + (Frequency * SD_RK32_TIMEOUT);
  2529. do {
  2530. Value = SD_DWC_READ_REGISTER(Device, SdDwcControl);
  2531. if ((Value & ResetMask) == 0) {
  2532. Status = STATUS_SUCCESS;
  2533. break;
  2534. }
  2535. } while (SdQueryTimeCounter(Controller) <= Timeout);
  2536. if (!KSUCCESS(Status)) {
  2537. return Status;
  2538. }
  2539. SD_DWC_WRITE_REGISTER(Device, SdDwcInterruptStatus, 0xFFFFFFFF);
  2540. //
  2541. // Wait for the DMA status to clear.
  2542. //
  2543. Status = STATUS_TIMEOUT;
  2544. Timeout = SdQueryTimeCounter(Controller) + (Frequency * SD_RK32_TIMEOUT);
  2545. do {
  2546. Value = SD_DWC_READ_REGISTER(Device, SdDwcStatus);
  2547. if ((Value & SD_DWC_STATUS_DMA_REQUEST) == 0) {
  2548. Status = STATUS_SUCCESS;
  2549. break;
  2550. }
  2551. } while (SdQueryTimeCounter(Controller) <= Timeout);
  2552. if (!KSUCCESS(Status)) {
  2553. return Status;
  2554. }
  2555. //
  2556. // Reset the FIFO again.
  2557. //
  2558. ResetMask = SD_DWC_CONTROL_FIFO_RESET;
  2559. Device = (PSD_RK32_CONTEXT)Context;
  2560. Value = (Control | ResetMask) &
  2561. ~(SD_DWC_CONTROL_DMA_ENABLE |
  2562. SD_DWC_CONTROL_USE_INTERNAL_DMAC);
  2563. SD_DWC_WRITE_REGISTER(Device, SdDwcControl, Value);
  2564. Status = STATUS_TIMEOUT;
  2565. Timeout = SdQueryTimeCounter(Controller) + (Frequency * SD_RK32_TIMEOUT);
  2566. do {
  2567. Value = SD_DWC_READ_REGISTER(Device, SdDwcControl);
  2568. if ((Value & ResetMask) == 0) {
  2569. Status = STATUS_SUCCESS;
  2570. break;
  2571. }
  2572. } while (SdQueryTimeCounter(Controller) <= Timeout);
  2573. if (!KSUCCESS(Status)) {
  2574. return Status;
  2575. }
  2576. //
  2577. // Reset the internal DMA.
  2578. //
  2579. BusMode = SD_DWC_READ_REGISTER(Device, SdDwcBusMode);
  2580. Value = BusMode &
  2581. ~(SD_DWC_BUS_MODE_FIXED_BURST | SD_DWC_BUS_MODE_IDMAC_ENABLE);
  2582. Value |= SD_DWC_BUS_MODE_INTERNAL_DMA_RESET;
  2583. SD_DWC_WRITE_REGISTER(Device, SdDwcBusMode, Value);
  2584. Status = STATUS_TIMEOUT;
  2585. Timeout = SdQueryTimeCounter(Controller) + (Frequency * SD_RK32_TIMEOUT);
  2586. do {
  2587. Value = SD_DWC_READ_REGISTER(Device, SdDwcBusMode);
  2588. if ((Value & SD_DWC_BUS_MODE_INTERNAL_DMA_RESET) == 0) {
  2589. Status = STATUS_SUCCESS;
  2590. break;
  2591. }
  2592. } while (SdQueryTimeCounter(Controller) <= Timeout);
  2593. if (!KSUCCESS(Status)) {
  2594. return Status;
  2595. }
  2596. SD_DWC_WRITE_REGISTER(Device, SdDwcBusMode, BusMode);
  2597. //
  2598. // Restore the original control, and update the clock.
  2599. //
  2600. SD_DWC_WRITE_REGISTER(Device, SdDwcControl, Control);
  2601. SD_DWC_WRITE_REGISTER(Device, SdDwcCardType, CardType);
  2602. Status = SdRk32SetClockSpeed(Device, Controller->ClockSpeed);
  2603. if (!KSUCCESS(Status)) {
  2604. return Status;
  2605. }
  2606. Value = (Controller->ReadBlockLength <<
  2607. SD_DWC_CARD_READ_THRESHOLD_SIZE_SHIFT) |
  2608. SD_DWC_CARD_READ_THRESHOLD_ENABLE;
  2609. SD_DWC_WRITE_REGISTER(Device, SdDwcCardThresholdControl, Value);
  2610. return STATUS_SUCCESS;
  2611. }
  2612. KSTATUS
  2613. SdRk32SendCommand (
  2614. PSD_CONTROLLER Controller,
  2615. PVOID Context,
  2616. PSD_COMMAND Command
  2617. )
  2618. /*++
  2619. Routine Description:
  2620. This routine sends the given command to the card.
  2621. Arguments:
  2622. Controller - Supplies a pointer to the controller.
  2623. Context - Supplies a context pointer passed to the SD/MMC library upon
  2624. creation of the controller.
  2625. Command - Supplies a pointer to the command parameters.
  2626. Return Value:
  2627. Status code.
  2628. --*/
  2629. {
  2630. ULONG CommandValue;
  2631. PSD_RK32_CONTEXT Device;
  2632. ULONG Flags;
  2633. KSTATUS Status;
  2634. ULONGLONG Timeout;
  2635. ULONG Value;
  2636. Device = (PSD_RK32_CONTEXT)Context;
  2637. //
  2638. // Clear any old interrupt status.
  2639. //
  2640. SD_DWC_WRITE_REGISTER(Device,
  2641. SdDwcInterruptStatus,
  2642. SD_DWC_INTERRUPT_STATUS_ALL_MASK);
  2643. SdRk32SetDmaInterrupts(Controller,
  2644. Device,
  2645. Command->Dma,
  2646. Command->BufferSize);
  2647. //
  2648. // If the stop command is being sent, add the flag to make sure the current
  2649. // data transfer stops and that this command does not wait for the previous
  2650. // data to complete. Otherwise, wait for the previous data to complete.
  2651. //
  2652. if ((Command->Command == SdCommandStopTransmission) &&
  2653. (Command->ResponseType != SD_RESPONSE_R1B)) {
  2654. Flags = SD_DWC_COMMAND_STOP_ABORT;
  2655. } else {
  2656. Flags = SD_DWC_COMMAND_WAIT_PREVIOUS_DATA_COMPLETE;
  2657. if (Command->Command == SdCommandReset) {
  2658. Flags |= SD_DWC_COMMAND_SEND_INITIALIZATION;
  2659. //
  2660. // For the voltage switch command, disable low power clock mode and set
  2661. // the required flag in the CMD register.
  2662. //
  2663. } else if (Command->Command == SdCommandVoltageSwitch) {
  2664. Value = SD_DWC_READ_REGISTER(Device, SdDwcClockEnable);
  2665. Value &= ~SD_DWC_CLOCK_ENABLE_LOW_POWER;
  2666. SD_DWC_WRITE_REGISTER(Device, SdDwcClockEnable, Value);
  2667. Status = SdRk32UpdateClock(Device);
  2668. if (!KSUCCESS(Status)) {
  2669. goto SendCommandEnd;
  2670. }
  2671. Device->InVoltageSwitch = TRUE;
  2672. Flags |= SD_DWC_COMMAND_VOLT_SWITCH;
  2673. }
  2674. //
  2675. // Wait for the FIFO to become empty command to complete.
  2676. //
  2677. Timeout = 0;
  2678. Value = SD_DWC_READ_REGISTER(Device, SdDwcStatus);
  2679. if ((Value & SD_DWC_STATUS_FIFO_EMPTY) == 0) {
  2680. Value = SD_DWC_READ_REGISTER(Device, SdDwcControl);
  2681. Value |= SD_DWC_CONTROL_FIFO_RESET;
  2682. SD_DWC_WRITE_REGISTER(Device, SdDwcControl, Value);
  2683. Status = STATUS_TIMEOUT;
  2684. do {
  2685. Value = SD_DWC_READ_REGISTER(Device, SdDwcControl);
  2686. if ((Value & SD_DWC_CONTROL_FIFO_RESET) == 0) {
  2687. Status = STATUS_SUCCESS;
  2688. break;
  2689. } else if (Timeout == 0) {
  2690. Timeout = SdQueryTimeCounter(Controller) +
  2691. Controller->Timeout;
  2692. }
  2693. } while (SdQueryTimeCounter(Controller) <= Timeout);
  2694. if (!KSUCCESS(Status)) {
  2695. goto SendCommandEnd;
  2696. }
  2697. }
  2698. //
  2699. // Also wait for the controller to stop being busy from the last
  2700. // command. This comes into play on writes that use internal DMA. The
  2701. // state machine remains busy despite the transfer completion
  2702. // interrupt.
  2703. //
  2704. if ((Value & SD_DWC_STATUS_DATA_BUSY) != 0) {
  2705. Status = STATUS_TIMEOUT;
  2706. Timeout = SdQueryTimeCounter(Controller) + Controller->Timeout;
  2707. do {
  2708. Value = SD_DWC_READ_REGISTER(Device, SdDwcStatus);
  2709. if ((Value & SD_DWC_STATUS_DATA_BUSY) == 0) {
  2710. Status = STATUS_SUCCESS;
  2711. break;
  2712. }
  2713. } while (SdQueryTimeCounter(Controller) <= Timeout);
  2714. if (!KSUCCESS(Status)) {
  2715. goto SendCommandEnd;
  2716. }
  2717. }
  2718. }
  2719. //
  2720. // Set up the response flags.
  2721. //
  2722. if ((Command->ResponseType & SD_RESPONSE_PRESENT) != 0) {
  2723. if ((Command->ResponseType & SD_RESPONSE_136_BIT) != 0) {
  2724. Flags |= SD_DWC_COMMAND_LONG_RESPONSE;
  2725. }
  2726. Flags |= SD_DWC_COMMAND_RESPONSE_EXPECTED;
  2727. }
  2728. //
  2729. // Set up the remainder of the command flags.
  2730. //
  2731. if ((Command->ResponseType & SD_RESPONSE_VALID_CRC) != 0) {
  2732. Flags |= SD_DWC_COMMAND_CHECK_RESPONSE_CRC;
  2733. }
  2734. //
  2735. // If there's a data buffer, program the block count.
  2736. //
  2737. if (Command->BufferSize != 0) {
  2738. Flags |= SD_DWC_COMMAND_DATA_EXPECTED;
  2739. if (Command->Write != FALSE) {
  2740. Flags |= SD_DWC_COMMAND_WRITE;
  2741. } else {
  2742. Flags |= SD_DWC_COMMAND_READ;
  2743. }
  2744. //
  2745. // If reading or writing multiple blocks, the block size register
  2746. // should be set to the default block size and the byte count should be
  2747. // a multiple of the block size.
  2748. //
  2749. if ((Command->Command == SdCommandReadMultipleBlocks) ||
  2750. (Command->Command == SdCommandWriteMultipleBlocks)) {
  2751. if (((Controller->HostCapabilities & SD_MODE_AUTO_CMD12) != 0) &&
  2752. (Controller->SendStop != FALSE)) {
  2753. Flags |= SD_DWC_COMMAND_SEND_AUTO_STOP;
  2754. }
  2755. SD_DWC_WRITE_REGISTER(Device, SdDwcBlockSize, SD_RK32_BLOCK_SIZE);
  2756. SD_DWC_WRITE_REGISTER(Device, SdDwcByteCount, Command->BufferSize);
  2757. //
  2758. // Otherwise set the block size to total number of bytes to be
  2759. // processed.
  2760. //
  2761. } else {
  2762. SD_DWC_WRITE_REGISTER(Device, SdDwcBlockSize, Command->BufferSize);
  2763. SD_DWC_WRITE_REGISTER(Device, SdDwcByteCount, Command->BufferSize);
  2764. }
  2765. }
  2766. //
  2767. // Internal DMA better be enabled if this is a DMA command.
  2768. //
  2769. ASSERT((Command->Dma == FALSE) ||
  2770. (Command->BufferSize == 0) ||
  2771. (((SD_DWC_READ_REGISTER(Device, SdDwcBusMode) &
  2772. SD_DWC_BUS_MODE_IDMAC_ENABLE) != 0) &&
  2773. ((SD_DWC_READ_REGISTER(Device, SdDwcControl) &
  2774. SD_DWC_CONTROL_USE_INTERNAL_DMAC) != 0)));
  2775. SD_DWC_WRITE_REGISTER(Device, SdDwcTimeout, 0xFFFFFFFF);
  2776. //
  2777. // Write the command argument.
  2778. //
  2779. SD_DWC_WRITE_REGISTER(Device,
  2780. SdDwcCommandArgument,
  2781. Command->CommandArgument);
  2782. //
  2783. // Set the command and wait for it to be accepted.
  2784. //
  2785. CommandValue = (Command->Command << SD_DWC_COMMAND_INDEX_SHIFT) &
  2786. SD_DWC_COMMAND_INDEX_MASK;
  2787. CommandValue |= SD_DWC_COMMAND_START |
  2788. SD_DWC_COMMAND_USE_HOLD_REGISTER |
  2789. Flags;
  2790. SD_DWC_WRITE_REGISTER(Device, SdDwcCommand, CommandValue);
  2791. //
  2792. // If this was a DMA command, just let it sail away.
  2793. //
  2794. if (Command->Dma != FALSE) {
  2795. Status = STATUS_SUCCESS;
  2796. goto SendCommandEnd;
  2797. }
  2798. ASSERT(Controller->EnabledInterrupts == SD_DWC_INTERRUPT_DEFAULT_MASK);
  2799. Status = STATUS_TIMEOUT;
  2800. Timeout = 0;
  2801. do {
  2802. Value = SD_DWC_READ_REGISTER(Device, SdDwcCommand);
  2803. if ((Value & SD_DWC_COMMAND_START) == 0) {
  2804. Status = STATUS_SUCCESS;
  2805. break;
  2806. } else if (Timeout == 0) {
  2807. Timeout = SdQueryTimeCounter(Controller) + Controller->Timeout;
  2808. }
  2809. } while (SdQueryTimeCounter(Controller) <= Timeout);
  2810. if (!KSUCCESS(Status)) {
  2811. goto SendCommandEnd;
  2812. }
  2813. //
  2814. // Check the interrupt status. Voltage switch commands set a specific
  2815. // status bit, all other commands set command done.
  2816. //
  2817. Status = STATUS_TIMEOUT;
  2818. do {
  2819. Value = SD_DWC_READ_REGISTER(Device, SdDwcInterruptStatus);
  2820. if (Command->Command == SdCommandVoltageSwitch) {
  2821. if ((Value & SD_DWC_INTERRUPT_STATUS_VOLT_SWITCH) != 0) {
  2822. Status = STATUS_SUCCESS;
  2823. break;
  2824. }
  2825. } else if ((Value & SD_DWC_INTERRUPT_STATUS_COMMAND_DONE) != 0) {
  2826. Status = STATUS_SUCCESS;
  2827. break;
  2828. }
  2829. if (Timeout == 0) {
  2830. Timeout = SdQueryTimeCounter(Controller) + Controller->Timeout;
  2831. }
  2832. } while (SdQueryTimeCounter(Controller) <= Timeout);
  2833. if (!KSUCCESS(Status)) {
  2834. goto SendCommandEnd;
  2835. }
  2836. if ((Value & SD_DWC_INTERRUPT_STATUS_ERROR_RESPONSE_TIMEOUT) != 0) {
  2837. SD_DWC_WRITE_REGISTER(Device,
  2838. SdDwcInterruptStatus,
  2839. SD_DWC_INTERRUPT_STATUS_ALL_MASK);
  2840. SdRk32ResetController(Controller,
  2841. Context,
  2842. SD_RESET_FLAG_COMMAND_LINE);
  2843. Status = STATUS_TIMEOUT;
  2844. goto SendCommandEnd;
  2845. } else if ((Value & SD_DWC_INTERRUPT_STATUS_COMMAND_ERROR_MASK) != 0) {
  2846. SD_DWC_WRITE_REGISTER(Device,
  2847. SdDwcInterruptStatus,
  2848. SD_DWC_INTERRUPT_STATUS_ALL_MASK);
  2849. Status = STATUS_DEVICE_IO_ERROR;
  2850. goto SendCommandEnd;
  2851. }
  2852. //
  2853. // Acknowledge the completed command.
  2854. //
  2855. SD_DWC_WRITE_REGISTER(Device, SdDwcInterruptStatus, Value);
  2856. //
  2857. // Get the response if there is one.
  2858. //
  2859. if ((Command->ResponseType & SD_RESPONSE_PRESENT) != 0) {
  2860. if ((Command->ResponseType & SD_RESPONSE_136_BIT) != 0) {
  2861. Command->Response[3] = SD_DWC_READ_REGISTER(Device, SdDwcResponse0);
  2862. Command->Response[2] = SD_DWC_READ_REGISTER(Device, SdDwcResponse1);
  2863. Command->Response[1] = SD_DWC_READ_REGISTER(Device, SdDwcResponse2);
  2864. Command->Response[0] = SD_DWC_READ_REGISTER(Device, SdDwcResponse3);
  2865. if ((Controller->HostCapabilities &
  2866. SD_MODE_RESPONSE136_SHIFTED) != 0) {
  2867. Command->Response[0] = (Command->Response[0] << 8) |
  2868. ((Command->Response[1] >> 24) & 0xFF);
  2869. Command->Response[1] = (Command->Response[1] << 8) |
  2870. ((Command->Response[2] >> 24) & 0xFF);
  2871. Command->Response[2] = (Command->Response[2] << 8) |
  2872. ((Command->Response[3] >> 24) & 0xFF);
  2873. Command->Response[3] = Command->Response[3] << 8;
  2874. }
  2875. } else {
  2876. Command->Response[0] = SD_DWC_READ_REGISTER(Device, SdDwcResponse0);
  2877. }
  2878. }
  2879. //
  2880. // Read/write the data.
  2881. //
  2882. if (Command->BufferSize != 0) {
  2883. if (Command->Write != FALSE) {
  2884. Status = SdRk32WriteData(Controller,
  2885. Context,
  2886. Command->BufferVirtual,
  2887. Command->BufferSize);
  2888. } else {
  2889. Status = SdRk32ReadData(Controller,
  2890. Context,
  2891. Command->BufferVirtual,
  2892. Command->BufferSize);
  2893. }
  2894. if (!KSUCCESS(Status)) {
  2895. goto SendCommandEnd;
  2896. }
  2897. }
  2898. Status = STATUS_SUCCESS;
  2899. SendCommandEnd:
  2900. return Status;
  2901. }
  2902. KSTATUS
  2903. SdRk32GetSetBusWidth (
  2904. PSD_CONTROLLER Controller,
  2905. PVOID Context,
  2906. BOOL Set
  2907. )
  2908. /*++
  2909. Routine Description:
  2910. This routine gets or sets the controller's bus width. The bus width is
  2911. stored in the controller structure.
  2912. Arguments:
  2913. Controller - Supplies a pointer to the controller.
  2914. Context - Supplies a context pointer passed to the SD/MMC library upon
  2915. creation of the controller.
  2916. Set - Supplies a boolean indicating whether the bus width should be queried
  2917. or set.
  2918. Return Value:
  2919. Status code.
  2920. --*/
  2921. {
  2922. PSD_RK32_CONTEXT Device;
  2923. ULONG Value;
  2924. Device = (PSD_RK32_CONTEXT)Context;
  2925. if (Set != FALSE) {
  2926. switch (Controller->BusWidth) {
  2927. case 1:
  2928. Value = SD_DWC_CARD_TYPE_1_BIT_WIDTH;
  2929. break;
  2930. case 4:
  2931. Value = SD_DWC_CARD_TYPE_4_BIT_WIDTH;
  2932. break;
  2933. case 8:
  2934. Value = SD_DWC_CARD_TYPE_8_BIT_WIDTH;
  2935. break;
  2936. default:
  2937. RtlDebugPrint("SDRK32: Invalid bus width %d.\n",
  2938. Controller->BusWidth);
  2939. ASSERT(FALSE);
  2940. return STATUS_INVALID_CONFIGURATION;
  2941. }
  2942. SD_DWC_WRITE_REGISTER(Device, SdDwcCardType, Value);
  2943. } else {
  2944. Value = SD_DWC_READ_REGISTER(Device, SdDwcCardType);
  2945. if ((Value & SD_DWC_CARD_TYPE_8_BIT_WIDTH) != 0) {
  2946. Controller->BusWidth = 8;
  2947. } else if ((Value & SD_DWC_CARD_TYPE_4_BIT_WIDTH) != 0) {
  2948. Controller->BusWidth = 4;
  2949. } else {
  2950. Controller->BusWidth = 1;
  2951. }
  2952. }
  2953. return STATUS_SUCCESS;
  2954. }
  2955. KSTATUS
  2956. SdRk32GetSetClockSpeed (
  2957. PSD_CONTROLLER Controller,
  2958. PVOID Context,
  2959. BOOL Set
  2960. )
  2961. /*++
  2962. Routine Description:
  2963. This routine gets or sets the controller's clock speed. The clock speed is
  2964. stored in the controller structure.
  2965. Arguments:
  2966. Controller - Supplies a pointer to the controller.
  2967. Context - Supplies a context pointer passed to the SD/MMC library upon
  2968. creation of the controller.
  2969. Set - Supplies a boolean indicating whether the clock speed should be
  2970. queried (FALSE) or set (TRUE).
  2971. Return Value:
  2972. Status code.
  2973. --*/
  2974. {
  2975. PSD_RK32_CONTEXT Device;
  2976. Device = (PSD_RK32_CONTEXT)Context;
  2977. if (Device->FundamentalClock == 0) {
  2978. return STATUS_INVALID_CONFIGURATION;
  2979. }
  2980. //
  2981. // Getting the clock speed is not implemented as the divisor math might not
  2982. // work out precisely in reverse.
  2983. //
  2984. if (Set == FALSE) {
  2985. return STATUS_NOT_SUPPORTED;
  2986. }
  2987. return SdRk32SetClockSpeed(Device, Controller->ClockSpeed);
  2988. }
  2989. KSTATUS
  2990. SdRk32GetSetVoltage (
  2991. PSD_CONTROLLER Controller,
  2992. PVOID Context,
  2993. BOOL Set
  2994. )
  2995. /*++
  2996. Routine Description:
  2997. This routine gets or sets the bus voltage. The bus voltage is
  2998. stored in the controller structure.
  2999. Arguments:
  3000. Controller - Supplies a pointer to the controller.
  3001. Context - Supplies a context pointer passed to the SD/MMC library upon
  3002. creation of the controller.
  3003. Set - Supplies a boolean indicating whether the bus voltage should be
  3004. queried (FALSE) or set (TRUE).
  3005. Return Value:
  3006. Status code.
  3007. --*/
  3008. {
  3009. PSD_RK32_CONTEXT Device;
  3010. ULONG Mask;
  3011. KSTATUS Status;
  3012. ULONGLONG Timeout;
  3013. ULONG Value;
  3014. Device = Context;
  3015. if (Set == FALSE) {
  3016. Value = SD_DWC_READ_REGISTER(Device, SdDwcUhs);
  3017. if ((Value & SD_DWC_UHS_VOLTAGE_1V8) != 0) {
  3018. Controller->CurrentVoltage = SdVoltage1V8;
  3019. } else {
  3020. Controller->CurrentVoltage = SdVoltage3V3;
  3021. }
  3022. return STATUS_SUCCESS;
  3023. }
  3024. //
  3025. // When the standard SD library sent CMD11, the following happened inside
  3026. // send command:
  3027. // * Low power clocking was disabled.
  3028. // * The volt switch interrupt was waited on and cleared.
  3029. // Now stop the SD clock.
  3030. //
  3031. SD_DWC_WRITE_REGISTER(Device, SdDwcClockEnable, 0);
  3032. Status = SdRk32UpdateClock(Device);
  3033. if (!KSUCCESS(Status)) {
  3034. goto GetSetVoltageEnd;
  3035. }
  3036. if (Controller->CurrentVoltage != SdVoltage1V8) {
  3037. Status = SdRk32SetRegulatorVoltage(Device, FALSE);
  3038. if (!KSUCCESS(Status)) {
  3039. goto GetSetVoltageEnd;
  3040. }
  3041. HlBusySpin(10000);
  3042. Value = SD_DWC_CLOCK_ENABLE_ON | SD_DWC_CLOCK_ENABLE_LOW_POWER;
  3043. SD_DWC_WRITE_REGISTER(Device, SdDwcClockEnable, Value);
  3044. Status = SdRk32UpdateClock(Device);
  3045. if (!KSUCCESS(Status)) {
  3046. goto GetSetVoltageEnd;
  3047. }
  3048. return STATUS_SUCCESS;
  3049. }
  3050. ASSERT(Device->InVoltageSwitch != FALSE);
  3051. //
  3052. // Switch the voltage.
  3053. //
  3054. Status = SdRk32SetRegulatorVoltage(Device, TRUE);
  3055. if (!KSUCCESS(Status)) {
  3056. goto GetSetVoltageEnd;
  3057. }
  3058. //
  3059. // Wait at least 5ms as per spec.
  3060. //
  3061. HlBusySpin(10000);
  3062. //
  3063. // Re-enable the clock.
  3064. //
  3065. SD_DWC_WRITE_REGISTER(Device, SdDwcClockEnable, SD_DWC_CLOCK_ENABLE_ON);
  3066. Status = SdRk32UpdateClock(Device);
  3067. if (!KSUCCESS(Status)) {
  3068. goto GetSetVoltageEnd;
  3069. }
  3070. //
  3071. // Wait another millisecond as per spec.
  3072. //
  3073. HlBusySpin(2000);
  3074. //
  3075. // The controller should have generated a volt switch and command done
  3076. // interrupt if DAT[3:0] went high for a millisecond.
  3077. //
  3078. Timeout = 0;
  3079. Mask = SD_DWC_INTERRUPT_STATUS_VOLT_SWITCH |
  3080. SD_DWC_INTERRUPT_STATUS_COMMAND_DONE;
  3081. Status = STATUS_TIMEOUT;
  3082. do {
  3083. Value = SD_DWC_READ_REGISTER(Device, SdDwcInterruptStatus);
  3084. if ((Value & Mask) == Mask) {
  3085. Status = STATUS_SUCCESS;
  3086. break;
  3087. } else if (Timeout == 0) {
  3088. Timeout = SdQueryTimeCounter(Controller) +
  3089. HlQueryTimeCounterFrequency();
  3090. }
  3091. } while (SdQueryTimeCounter(Controller) <= Timeout);
  3092. SD_DWC_WRITE_REGISTER(Device, SdDwcInterruptStatus, Value);
  3093. if (!KSUCCESS(Status)) {
  3094. goto GetSetVoltageEnd;
  3095. }
  3096. Mask = SD_RESET_FLAG_COMMAND_LINE | SD_RESET_FLAG_DATA_LINE;
  3097. Status = SdRk32ResetController(Controller, Device, Mask);
  3098. if (!KSUCCESS(Status)) {
  3099. goto GetSetVoltageEnd;
  3100. }
  3101. Status = STATUS_SUCCESS;
  3102. GetSetVoltageEnd:
  3103. Device->InVoltageSwitch = FALSE;
  3104. return Status;
  3105. }
  3106. KSTATUS
  3107. SdRk32ReadData (
  3108. PSD_CONTROLLER Controller,
  3109. PVOID Context,
  3110. PVOID Data,
  3111. ULONG Size
  3112. )
  3113. /*++
  3114. Routine Description:
  3115. This routine reads polled data from the SD controller.
  3116. Arguments:
  3117. Controller - Supplies a pointer to the controller.
  3118. Context - Supplies a context pointer passed to the SD/MMC library upon
  3119. creation of the controller.
  3120. Data - Supplies a pointer to the buffer where the data will be read into.
  3121. Size - Supplies the size in bytes. This must be a multiple of four bytes.
  3122. Return Value:
  3123. Status code.
  3124. --*/
  3125. {
  3126. PULONG Buffer32;
  3127. ULONG BusyMask;
  3128. ULONG Count;
  3129. ULONG DataReadyMask;
  3130. BOOL DataTransferOver;
  3131. PSD_RK32_CONTEXT Device;
  3132. ULONG Interrupts;
  3133. ULONG IoIndex;
  3134. KSTATUS Status;
  3135. ULONGLONG Timeout;
  3136. ULONGLONG TimeoutTicks;
  3137. ULONG Value;
  3138. ASSERT(IS_ALIGNED(Size, sizeof(ULONG)) != FALSE);
  3139. Device = (PSD_RK32_CONTEXT)Context;
  3140. DataTransferOver = FALSE;
  3141. Buffer32 = (PULONG)Data;
  3142. Size /= sizeof(ULONG);
  3143. TimeoutTicks = HlQueryTimeCounterFrequency() * SD_RK32_TIMEOUT;
  3144. while (Size != 0) {
  3145. //
  3146. // Get the interrupt status register.
  3147. //
  3148. Status = STATUS_SUCCESS;
  3149. Timeout = SdQueryTimeCounter(Controller) + TimeoutTicks;
  3150. do {
  3151. Interrupts = SD_DWC_READ_REGISTER(Device, SdDwcInterruptStatus);
  3152. if (Interrupts != 0) {
  3153. Status = STATUS_SUCCESS;
  3154. break;
  3155. }
  3156. } while (SdQueryTimeCounter(Controller) <= Timeout);
  3157. if (!KSUCCESS(Status)) {
  3158. return Status;
  3159. }
  3160. //
  3161. // Reset the controller if any error bits are set.
  3162. //
  3163. if ((Interrupts & SD_DWC_INTERRUPT_STATUS_DATA_ERROR_MASK) != 0) {
  3164. SdRk32ResetController(Controller, Context, SD_RESET_FLAG_DATA_LINE);
  3165. return STATUS_DEVICE_IO_ERROR;
  3166. }
  3167. //
  3168. // Check for received data status. If data is ready, the status
  3169. // register holds the number of 32-bit elements to be read.
  3170. //
  3171. DataReadyMask = SD_DWC_INTERRUPT_STATUS_RECEIVE_FIFO_DATA_REQUEST;
  3172. if ((Interrupts & DataReadyMask) != 0) {
  3173. Count = SD_DWC_READ_REGISTER(Device, SdDwcStatus);
  3174. Count = (Count & SD_DWC_STATUS_FIFO_COUNT_MASK) >>
  3175. SD_DWC_STATUS_FIFO_COUNT_SHIFT;
  3176. if (Count > Size) {
  3177. Count = Size;
  3178. }
  3179. for (IoIndex = 0; IoIndex < Count; IoIndex += 1) {
  3180. *Buffer32 = SD_DWC_READ_REGISTER(Device, SdDwcFifoBase);
  3181. Buffer32 += 1;
  3182. }
  3183. Size -= Count;
  3184. SD_DWC_WRITE_REGISTER(Device,
  3185. SdDwcInterruptStatus,
  3186. DataReadyMask);
  3187. }
  3188. //
  3189. // Check for the transfer over bit. If it is set, then read the rest of
  3190. // the bytes from the FIFO.
  3191. //
  3192. if ((Interrupts & SD_DWC_INTERRUPT_STATUS_DATA_TRANSFER_OVER) != 0) {
  3193. for (IoIndex = 0; IoIndex < Size; IoIndex += 1) {
  3194. *Buffer32 = SD_DWC_READ_REGISTER(Device, SdDwcFifoBase);
  3195. Buffer32 += 1;
  3196. }
  3197. SD_DWC_WRITE_REGISTER(Device,
  3198. SdDwcInterruptStatus,
  3199. SD_DWC_INTERRUPT_STATUS_DATA_TRANSFER_OVER);
  3200. Size = 0;
  3201. DataTransferOver = TRUE;
  3202. break;
  3203. }
  3204. }
  3205. //
  3206. // If the data transfer over interrupt has not yet been seen, wait for it
  3207. // to be asserted.
  3208. //
  3209. if (DataTransferOver == FALSE) {
  3210. Status = STATUS_SUCCESS;
  3211. Timeout = SdQueryTimeCounter(Controller) + TimeoutTicks;
  3212. do {
  3213. Interrupts = SD_DWC_READ_REGISTER(Device, SdDwcInterruptStatus);
  3214. if ((Interrupts &
  3215. SD_DWC_INTERRUPT_STATUS_DATA_TRANSFER_OVER) != 0) {
  3216. Status = STATUS_SUCCESS;
  3217. break;
  3218. }
  3219. } while (SdQueryTimeCounter(Controller) <= Timeout);
  3220. if (!KSUCCESS(Status)) {
  3221. return Status;
  3222. }
  3223. SD_DWC_WRITE_REGISTER(Device,
  3224. SdDwcInterruptStatus,
  3225. SD_DWC_INTERRUPT_STATUS_DATA_TRANSFER_OVER);
  3226. }
  3227. //
  3228. // Wait until the state machine and data stop being busy.
  3229. //
  3230. BusyMask = SD_DWC_STATUS_DATA_STATE_MACHINE_BUSY |
  3231. SD_DWC_STATUS_DATA_BUSY;
  3232. Status = STATUS_SUCCESS;
  3233. Timeout = SdQueryTimeCounter(Controller) + TimeoutTicks;
  3234. do {
  3235. Value = SD_DWC_READ_REGISTER(Device, SdDwcStatus);
  3236. if ((Value & BusyMask) == 0) {
  3237. Status = STATUS_SUCCESS;
  3238. break;
  3239. }
  3240. } while (SdQueryTimeCounter(Controller) <= Timeout);
  3241. if (!KSUCCESS(Status)) {
  3242. return Status;
  3243. }
  3244. return STATUS_SUCCESS;
  3245. }
  3246. KSTATUS
  3247. SdRk32WriteData (
  3248. PSD_CONTROLLER Controller,
  3249. PVOID Context,
  3250. PVOID Data,
  3251. ULONG Size
  3252. )
  3253. /*++
  3254. Routine Description:
  3255. This routine writes polled data to the SD controller.
  3256. Arguments:
  3257. Controller - Supplies a pointer to the controller.
  3258. Context - Supplies a context pointer passed to the SD/MMC library upon
  3259. creation of the controller.
  3260. Data - Supplies a pointer to the buffer containing the data to write.
  3261. Size - Supplies the size in bytes. This must be a multiple of 4 bytes.
  3262. Return Value:
  3263. Status code.
  3264. --*/
  3265. {
  3266. PULONG Buffer32;
  3267. ULONG BusyMask;
  3268. ULONG Count;
  3269. ULONG DataRequestMask;
  3270. BOOL DataTransferOver;
  3271. PSD_RK32_CONTEXT Device;
  3272. ULONG Interrupts;
  3273. ULONG IoIndex;
  3274. KSTATUS Status;
  3275. ULONGLONG Timeout;
  3276. ULONGLONG TimeoutTicks;
  3277. ULONG Value;
  3278. ASSERT(IS_ALIGNED(Size, sizeof(ULONG)) != FALSE);
  3279. Device = (PSD_RK32_CONTEXT)Context;
  3280. DataTransferOver = FALSE;
  3281. Buffer32 = (PULONG)Data;
  3282. Size /= sizeof(ULONG);
  3283. TimeoutTicks = HlQueryTimeCounterFrequency() * SD_RK32_TIMEOUT;
  3284. while (Size != 0) {
  3285. //
  3286. // Get the interrupt status register.
  3287. //
  3288. Status = STATUS_SUCCESS;
  3289. Timeout = SdQueryTimeCounter(Controller) + TimeoutTicks;
  3290. do {
  3291. Interrupts = SD_DWC_READ_REGISTER(Device, SdDwcInterruptStatus);
  3292. if (Interrupts != 0) {
  3293. Status = STATUS_SUCCESS;
  3294. break;
  3295. }
  3296. } while (SdQueryTimeCounter(Controller) <= Timeout);
  3297. if (!KSUCCESS(Status)) {
  3298. return Status;
  3299. }
  3300. //
  3301. // Reset the controller if any error bits are set.
  3302. //
  3303. if ((Interrupts & SD_DWC_INTERRUPT_STATUS_DATA_ERROR_MASK) != 0) {
  3304. SdRk32ResetController(Controller, Context, SD_RESET_FLAG_DATA_LINE);
  3305. return STATUS_DEVICE_IO_ERROR;
  3306. }
  3307. //
  3308. // If the controller is ready for data to be written, the number of
  3309. // 4-byte elements consumed in the FIFO is stored in the status
  3310. // register. The available bytes is the total FIFO size minus that
  3311. // amount.
  3312. //
  3313. DataRequestMask = SD_DWC_INTERRUPT_STATUS_TRANSMIT_FIFO_DATA_REQUEST;
  3314. if ((Interrupts & DataRequestMask) != 0) {
  3315. Count = SD_DWC_READ_REGISTER(Device, SdDwcStatus);
  3316. Count = (Count & SD_DWC_STATUS_FIFO_COUNT_MASK) >>
  3317. SD_DWC_STATUS_FIFO_COUNT_SHIFT;
  3318. Count = (SD_DWC_FIFO_DEPTH / sizeof(ULONG)) - Count;
  3319. if (Count > Size) {
  3320. Count = Size;
  3321. }
  3322. for (IoIndex = 0; IoIndex < Count; IoIndex += 1) {
  3323. SD_DWC_WRITE_REGISTER(Device, SdDwcFifoBase, *Buffer32);
  3324. Buffer32 += 1;
  3325. }
  3326. Size -= Count;
  3327. SD_DWC_WRITE_REGISTER(Device,
  3328. SdDwcInterruptStatus,
  3329. DataRequestMask);
  3330. }
  3331. //
  3332. // Check for the transfer over bit. If it is set, then exit.
  3333. //
  3334. if ((Interrupts & SD_DWC_INTERRUPT_STATUS_DATA_TRANSFER_OVER) != 0) {
  3335. SD_DWC_WRITE_REGISTER(Device,
  3336. SdDwcInterruptStatus,
  3337. SD_DWC_INTERRUPT_STATUS_DATA_TRANSFER_OVER);
  3338. Size = 0;
  3339. DataTransferOver = TRUE;
  3340. break;
  3341. }
  3342. }
  3343. //
  3344. // If the data transfer over interrupt has not yet been seen, wait for it
  3345. // to be asserted.
  3346. //
  3347. if (DataTransferOver == FALSE) {
  3348. Status = STATUS_SUCCESS;
  3349. Timeout = SdQueryTimeCounter(Controller) + TimeoutTicks;
  3350. do {
  3351. Interrupts = SD_DWC_READ_REGISTER(Device, SdDwcInterruptStatus);
  3352. if ((Interrupts &
  3353. SD_DWC_INTERRUPT_STATUS_DATA_TRANSFER_OVER) != 0) {
  3354. Status = STATUS_SUCCESS;
  3355. break;
  3356. }
  3357. } while (SdQueryTimeCounter(Controller) <= Timeout);
  3358. if (!KSUCCESS(Status)) {
  3359. return Status;
  3360. }
  3361. SD_DWC_WRITE_REGISTER(Device,
  3362. SdDwcInterruptStatus,
  3363. SD_DWC_INTERRUPT_STATUS_DATA_TRANSFER_OVER);
  3364. }
  3365. //
  3366. // Wait until the state machine and data stop being busy.
  3367. //
  3368. BusyMask = SD_DWC_STATUS_DATA_STATE_MACHINE_BUSY |
  3369. SD_DWC_STATUS_DATA_BUSY;
  3370. Status = STATUS_SUCCESS;
  3371. Timeout = SdQueryTimeCounter(Controller) + TimeoutTicks;
  3372. do {
  3373. Value = SD_DWC_READ_REGISTER(Device, SdDwcStatus);
  3374. if ((Value & BusyMask) == 0) {
  3375. Status = STATUS_SUCCESS;
  3376. break;
  3377. }
  3378. } while (SdQueryTimeCounter(Controller) <= Timeout);
  3379. if (!KSUCCESS(Status)) {
  3380. return Status;
  3381. }
  3382. return STATUS_SUCCESS;
  3383. }
  3384. KSTATUS
  3385. SdRk32SetClockSpeed (
  3386. PSD_RK32_CONTEXT Device,
  3387. SD_CLOCK_SPEED ClockSpeed
  3388. )
  3389. /*++
  3390. Routine Description:
  3391. This routine sets the controller's clock speed. This function is RockChip
  3392. specific.
  3393. Arguments:
  3394. Device - Supplies a pointer to this SD RK32xx device.
  3395. ClockSpeed - Supplies the desired clock speed in Hertz.
  3396. Return Value:
  3397. Status code.
  3398. --*/
  3399. {
  3400. ULONG Divisor;
  3401. ULONGLONG Frequency;
  3402. ULONG InputClock;
  3403. KSTATUS Status;
  3404. ULONGLONG Timeout;
  3405. ULONG Value;
  3406. //
  3407. // TODO: Figure out why the RockChip SD fails occasionally and needs to be
  3408. // slowed down here.
  3409. //
  3410. if (ClockSpeed > SdClock25MHz) {
  3411. ClockSpeed = SdClock25MHz;
  3412. }
  3413. if (Device->FundamentalClock == 0) {
  3414. return STATUS_INVALID_CONFIGURATION;
  3415. }
  3416. Frequency = HlQueryTimeCounterFrequency();
  3417. //
  3418. // Wait for the card to not be busy.
  3419. //
  3420. Status = STATUS_TIMEOUT;
  3421. Timeout = KeGetRecentTimeCounter() + (Frequency * SD_RK32_TIMEOUT);
  3422. do {
  3423. Value = SD_DWC_READ_REGISTER(Device, SdDwcStatus);
  3424. if ((Value & SD_DWC_STATUS_DATA_BUSY) == 0) {
  3425. Status = STATUS_SUCCESS;
  3426. break;
  3427. }
  3428. } while (KeGetRecentTimeCounter() <= Timeout);
  3429. if (!KSUCCESS(Status)) {
  3430. return Status;
  3431. }
  3432. //
  3433. // Disable all clocks.
  3434. //
  3435. SD_DWC_WRITE_REGISTER(Device, SdDwcClockEnable, 0);
  3436. Status = SdRk32UpdateClock(Device);
  3437. if (!KSUCCESS(Status)) {
  3438. return Status;
  3439. }
  3440. //
  3441. // Use the 24MHz clock if a really slow speed is desired.
  3442. //
  3443. InputClock = Device->FundamentalClock;
  3444. if (ClockSpeed < (InputClock / (RK32_CRU_MAX_MMC_DIVISOR + 1))) {
  3445. //
  3446. // Select the raw 24MHz source, and set the DesignWare divider to 1 to
  3447. // divide by 2.
  3448. //
  3449. InputClock = RK32_SDMMC_FREQUENCY_24MHZ / 2;
  3450. ASSERT(ClockSpeed <= InputClock);
  3451. SD_DWC_WRITE_REGISTER(Device, SdDwcClockDivider, 1);
  3452. Value = (RK32_CRU_CLOCK_SELECT_24MHZ <<
  3453. RK32_CRU_CLOCK_SELECT_CLOCK_SHIFT);
  3454. //
  3455. // Use the general PLL.
  3456. //
  3457. } else {
  3458. SD_DWC_WRITE_REGISTER(Device, SdDwcClockDivider, 0);
  3459. Value = (RK32_CRU_CLOCK_SELECT_GENERAL_PLL <<
  3460. RK32_CRU_CLOCK_SELECT_CLOCK_SHIFT);
  3461. }
  3462. Divisor = InputClock / ClockSpeed;
  3463. if (InputClock / Divisor > ClockSpeed) {
  3464. Divisor += 1;
  3465. }
  3466. ASSERT(Divisor <= RK32_CRU_MAX_MMC_DIVISOR);
  3467. //
  3468. // Bits 16 and up must be set for the write to take effect. This is also
  3469. // why read-modify-write is not needed.
  3470. //
  3471. Value |= (RK32_CRU_CLOCK_SELECT_CLOCK_MASK |
  3472. RK32_CRU_CLOCK_SELECT_DIVIDER_MASK) <<
  3473. RK32_CRU_CLOCK_SELECT_PROTECT_SHIFT;
  3474. Value |= Divisor;
  3475. Value <<= Device->VendorData->ClockSelectShift;
  3476. SD_RK32_WRITE_CRU(Device, Device->VendorData->ClockSelectOffset, Value);
  3477. SD_DWC_WRITE_REGISTER(Device,
  3478. SdDwcClockSource,
  3479. SD_DWC_CLOCK_SOURCE_DIVIDER_0);
  3480. Status = SdRk32UpdateClock(Device);
  3481. if (!KSUCCESS(Status)) {
  3482. return Status;
  3483. }
  3484. //
  3485. // Enable the clocks in lower power mode.
  3486. //
  3487. SD_DWC_WRITE_REGISTER(Device,
  3488. SdDwcClockEnable,
  3489. (SD_DWC_CLOCK_ENABLE_LOW_POWER |
  3490. SD_DWC_CLOCK_ENABLE_ON));
  3491. Status = SdRk32UpdateClock(Device);
  3492. if (!KSUCCESS(Status)) {
  3493. return Status;
  3494. }
  3495. return STATUS_SUCCESS;
  3496. }
  3497. VOID
  3498. SdRk32SetDmaInterrupts (
  3499. PSD_CONTROLLER Controller,
  3500. PSD_RK32_CONTEXT Device,
  3501. BOOL Enable,
  3502. ULONG BufferSize
  3503. )
  3504. /*++
  3505. Routine Description:
  3506. This routine enables or disables interrupts necessary to perform block I/O
  3507. via DMA. It is assumed that the caller has synchronized disk access on this
  3508. controller and there are currently no DMA or polled operations in flight.
  3509. Arguments:
  3510. Controller - Supplies a pointer to the controller.
  3511. Device - Supplies a pointer to the RK32xx SD device context.
  3512. Enable - Supplies a boolean indicating if the DMA interrupts are to be
  3513. enabled (TRUE) or disabled (FALSE).
  3514. BufferSize - Supplies the length of the DMA buffer.
  3515. Return Value:
  3516. None.
  3517. --*/
  3518. {
  3519. ULONG Value;
  3520. //
  3521. // Enable the interrupts for transfer completion so that DMA operations
  3522. // can complete asynchronously. Unless, of course, the DMA interrupts are
  3523. // already enabled.
  3524. //
  3525. if (Enable != FALSE) {
  3526. Value = Controller->EnabledInterrupts | SD_DWC_INTERRUPT_ERROR_MASK;
  3527. Value &= ~(SD_DWC_INTERRUPT_MASK_DATA_TRANSFER_OVER |
  3528. SD_DWC_INTERRUPT_MASK_COMMAND_DONE);
  3529. if (BufferSize != 0) {
  3530. Value |= SD_DWC_INTERRUPT_MASK_DATA_TRANSFER_OVER;
  3531. } else {
  3532. Value |= SD_DWC_INTERRUPT_MASK_COMMAND_DONE;
  3533. }
  3534. //
  3535. // Disable the DMA interrupts so that they do not interfere with polled I/O
  3536. // attempts to check the transfer status. Do nothing if the DMA interrupts
  3537. // are disabled.
  3538. //
  3539. } else {
  3540. Value = Controller->EnabledInterrupts &
  3541. ~(SD_DWC_INTERRUPT_MASK_DATA_TRANSFER_OVER |
  3542. SD_DWC_INTERRUPT_MASK_COMMAND_DONE |
  3543. SD_DWC_INTERRUPT_ERROR_MASK);
  3544. }
  3545. if (Value != Controller->EnabledInterrupts) {
  3546. Controller->EnabledInterrupts = Value;
  3547. SD_DWC_WRITE_REGISTER(Device,
  3548. SdDwcInterruptMask,
  3549. Controller->EnabledInterrupts);
  3550. }
  3551. return;
  3552. }
  3553. KSTATUS
  3554. SdRk32UpdateClock (
  3555. PSD_RK32_CONTEXT Device
  3556. )
  3557. /*++
  3558. Routine Description:
  3559. This routine performs a clock update, activating the configuration when
  3560. the clock divisor, enable, or source registers are changed.
  3561. Arguments:
  3562. Device - Supplies a pointer to this SD RK32xx device.
  3563. Return Value:
  3564. Status code.
  3565. --*/
  3566. {
  3567. KSTATUS Status;
  3568. ULONGLONG Timeout;
  3569. ULONG Value;
  3570. Value = SD_DWC_COMMAND_START |
  3571. SD_DWC_COMMAND_UPDATE_CLOCK_REGISTERS |
  3572. SD_DWC_COMMAND_WAIT_PREVIOUS_DATA_COMPLETE;
  3573. if (Device->InVoltageSwitch != FALSE) {
  3574. Value |= SD_DWC_COMMAND_VOLT_SWITCH;
  3575. }
  3576. SD_DWC_WRITE_REGISTER(Device, SdDwcCommand, Value);
  3577. Status = STATUS_TIMEOUT;
  3578. Timeout = KeGetRecentTimeCounter() +
  3579. (HlQueryTimeCounterFrequency() * SD_RK32_TIMEOUT);
  3580. do {
  3581. Value = SD_DWC_READ_REGISTER(Device, SdDwcCommand);
  3582. if ((Value & SD_DWC_COMMAND_START) == 0) {
  3583. Status = STATUS_SUCCESS;
  3584. break;
  3585. }
  3586. } while (KeGetRecentTimeCounter() <= Timeout);
  3587. if (!KSUCCESS(Status)) {
  3588. return Status;
  3589. }
  3590. return Status;
  3591. }
  3592. VOID
  3593. SdRk32Rk808InterfaceNotificationCallback (
  3594. PVOID Context,
  3595. PDEVICE Device,
  3596. PVOID InterfaceBuffer,
  3597. ULONG InterfaceBufferSize,
  3598. BOOL Arrival
  3599. )
  3600. /*++
  3601. Routine Description:
  3602. This routine is called to notify listeners that an RK808 interface has
  3603. arrived or departed.
  3604. Arguments:
  3605. Context - Supplies the caller's context pointer, supplied when the caller
  3606. requested interface notifications.
  3607. Device - Supplies a pointer to the device exposing or deleting the
  3608. interface.
  3609. InterfaceBuffer - Supplies a pointer to the interface buffer of the
  3610. interface.
  3611. InterfaceBufferSize - Supplies the buffer size.
  3612. Arrival - Supplies TRUE if a new interface is arriving, or FALSE if an
  3613. interface is departing.
  3614. Return Value:
  3615. None.
  3616. --*/
  3617. {
  3618. PSD_RK32_CONTEXT SdDevice;
  3619. SdDevice = Context;
  3620. if (InterfaceBufferSize == sizeof(INTERFACE_RK808)) {
  3621. if (Arrival != FALSE) {
  3622. ASSERT(SdDevice->Rk808 == NULL);
  3623. SdDevice->Rk808 = InterfaceBuffer;
  3624. } else {
  3625. SdDevice->Rk808 = NULL;
  3626. }
  3627. }
  3628. return;
  3629. }
  3630. KSTATUS
  3631. SdRk32SetRegulatorVoltage (
  3632. PSD_RK32_CONTEXT Device,
  3633. BOOL LowVoltage
  3634. )
  3635. /*++
  3636. Routine Description:
  3637. This routine sets the regulator voltage of the SD bus pins.
  3638. Arguments:
  3639. Device - Supplies a pointer to the device context.
  3640. LowVoltage - Supplies a boolean indicating whether to set the bus voltage
  3641. to 1.8V (TRUE) or 3.3V (FALSE).
  3642. Return Value:
  3643. Status code.
  3644. --*/
  3645. {
  3646. RK808_LDO_CONFIGURATION Configuration;
  3647. KSTATUS Status;
  3648. ULONG Value;
  3649. if ((Device->Ldo != 0) && (Device->Rk808 != NULL)) {
  3650. RtlZeroMemory(&Configuration, sizeof(RK808_LDO_CONFIGURATION));
  3651. Configuration.Flags = RK808_LDO_ENABLED | RK808_LDO_OFF_IN_SLEEP;
  3652. Configuration.ActiveVoltage = 3300;
  3653. if (LowVoltage != FALSE) {
  3654. Configuration.ActiveVoltage = 1800;
  3655. }
  3656. Status = Device->Rk808->SetLdo(Device->Rk808,
  3657. Device->Ldo,
  3658. &Configuration);
  3659. if (!KSUCCESS(Status)) {
  3660. return Status;
  3661. }
  3662. }
  3663. Value = SD_DWC_READ_REGISTER(Device, SdDwcUhs);
  3664. if (LowVoltage != FALSE) {
  3665. Value |= SD_DWC_UHS_VOLTAGE_1V8;
  3666. } else {
  3667. Value = 0;
  3668. }
  3669. SD_DWC_WRITE_REGISTER(Device, SdDwcUhs, Value);
  3670. return Status;
  3671. }