entry.S 2.5 KB

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  1. /*++
  2. Copyright (c) 2014 Minoca Corp. All Rights Reserved
  3. Module Name:
  4. entry.s
  5. Abstract:
  6. This module implements the initial entry point into the ARMv7 firmware. Its
  7. job is to do essential initialization and call the C main function.
  8. Author:
  9. Evan Green 19-Dec-2014
  10. Environment:
  11. Firmware
  12. --*/
  13. ##
  14. ## ------------------------------------------------------------------- Includes
  15. ##
  16. #include <minoca/kernel/arm.inc>
  17. ##
  18. ## ---------------------------------------------------------------- Definitions
  19. ##
  20. .equ STACK_SIZE, 0x4000
  21. ##
  22. ## ----------------------------------------------------------------------- Code
  23. ##
  24. ##
  25. ## .text specifies that this code belongs in the executable section. This is
  26. ## the only section in the MBR code, data also lives in the text section.
  27. ## .arm specifies that this code should be compiled in ARM mode.
  28. ##
  29. .text
  30. .arm
  31. ##
  32. ## .global allows this label to be visible to the linker. _start is the entry
  33. ## point to the MBR code, so it needs to be globally visible.
  34. ##
  35. .global _start
  36. ##
  37. ## This is the entry point for the ARM boot loader. It changes to SVC mode,
  38. ## sets up the initial stack, and jumps to the main loader.
  39. ##
  40. _start:
  41. ##
  42. ## Save the boot device type argument.
  43. ##
  44. mov %r4, %r0
  45. ##
  46. ## Disable interrupts and switch to SVC mode.
  47. ##
  48. mov %r2, #(PSR_FLAG_IRQ | ARM_MODE_SVC)
  49. msr CPSR_c, %r2
  50. ##
  51. ## Flip some essential MMU bits allowing unaligned accesses.
  52. ##
  53. mrc p15, 0, %r0, %cr1, %cr0, 0
  54. bic %r0, %r0, #MMU_ALIGNMENT_FAULT_ENABLED
  55. orr %r0, %r0, #MMU_UNALIGNED_ACCESS_ENABLED
  56. mcr p15, 0, %r0, %cr1, %cr0, 0
  57. ##
  58. ## Zero out the BSS section.
  59. ##
  60. ldr %r1, =__bss_start__
  61. ldr %r2, =__bss_end__
  62. mov %r0, #0
  63. BssZeroLoop:
  64. str %r0, [%r1], #4
  65. cmp %r1, %r2
  66. blt BssZeroLoop
  67. ##
  68. ## The stack starts at the image base and works downwards.
  69. ##
  70. adr %r0, _start @ Get the current address for the stack top.
  71. ldr %r1, =STACK_SIZE @ Get the stack size.
  72. mov %r2, %r4 @ Get the boot device type.
  73. mov %sp, %r0 @ Set the stack.
  74. mov %r11, #0 @ Zero the ARM frame pointer.
  75. mov %r7, #0 @ Zero out the Thumb frame pointer.
  76. mov %r3, %r7 @ Zero out another temporary register.
  77. push {%r3, %r7} @ Create an empty stack frame for debugging.
  78. blx EfiBeagleBoneMain
  79. LoopForever:
  80. b LoopForever