arm.h 52 KB

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  1. /*++
  2. Copyright (c) 2012 Minoca Corp.
  3. This file is licensed under the terms of the GNU General Public License
  4. version 3. Alternative licensing terms are available. Contact
  5. info@minocacorp.com for details. See the LICENSE file at the root of this
  6. project for complete licensing information.
  7. Module Name:
  8. arm.h
  9. Abstract:
  10. This header contains definitions for aspects of the system that are specific
  11. to the ARM architecture.
  12. Author:
  13. Evan Green 11-Aug-2012
  14. --*/
  15. //
  16. // ------------------------------------------------------------------- Includes
  17. //
  18. //
  19. // --------------------------------------------------------------------- Macros
  20. //
  21. //
  22. // This macro gets the index into the first level page table for the given
  23. // virtual address.
  24. //
  25. #define FLT_INDEX(_Address) \
  26. (((ULONG)(_Address) & FLT_INDEX_MASK) >> FLT_INDEX_SHIFT)
  27. //
  28. // This macro gets the index into the second level page table for the given
  29. // virtual address.
  30. //
  31. #define SLT_INDEX(_Address) \
  32. (((ULONG)(_Address) & SLT_INDEX_MASK) >> SLT_INDEX_SHIFT)
  33. //
  34. // This macro gets the fault status type from the fault status register.
  35. //
  36. #define ARM_FAULT_STATUS_TYPE(_FaultStatus) \
  37. ((_FaultStatus) & ARM_FAULT_STATUS_TYPE_MASK)
  38. //
  39. // This macro determines if the given fault status is a page fault.
  40. //
  41. #define IS_ARM_PAGE_FAULT(_FaultStatus) \
  42. ((ARM_FAULT_STATUS_TYPE(_FaultStatus) == \
  43. ARM_FAULT_STATUS_TYPE_SECTION_TRANLSATION) || \
  44. (ARM_FAULT_STATUS_TYPE(_FaultStatus) == \
  45. ARM_FAULT_STATUS_TYPE_PAGE_TRANSLATION))
  46. #define IS_ARM_PERMISSION_FAULT(_FaultStatus) \
  47. ((ARM_FAULT_STATUS_TYPE(_FaultStatus) == \
  48. ARM_FAULT_STATUS_TYPE_SECTION_PERMISSION) || \
  49. (ARM_FAULT_STATUS_TYPE(_FaultStatus) == \
  50. ARM_FAULT_STATUS_TYPE_PAGE_PERMISSION))
  51. #define IS_ARM_DEBUG_BREAK(_FaultStatus) \
  52. (ARM_FAULT_STATUS_TYPE(_FaultStatus) == ARM_FAULT_STATUS_TYPE_DEBUG)
  53. //
  54. // This macro removes the thumb bit from the PC.
  55. //
  56. #define REMOVE_THUMB_BIT(_Pc) ((_Pc) & ~ARM_THUMB_BIT)
  57. //
  58. // This macro extracts the if-then state from a current program status register
  59. // value.
  60. //
  61. #define PSR_GET_IT_STATE(_Cpsr) \
  62. ((((_Cpsr) >> 8) & 0xFC) | (((_Cpsr) >> 25) & 0x3))
  63. //
  64. // This macro returns the given current program status register value with the
  65. // if-then state bits set to the given if-then state.
  66. //
  67. #define PSR_SET_IT_STATE(_Cpsr, _ItState) \
  68. (((_Cpsr) & 0xF9FF03FF) | \
  69. (((_ItState) << 25) & 0x06000000) | \
  70. (((_ItState) << 8) & 0x0000FC00))
  71. //
  72. // This macro determines if, given a current Program Status Register value,
  73. // the if-then state is active in any form..
  74. //
  75. #define PSR_IS_IT_ACTIVE(_Cpsr) (((_Cpsr) & PSR_FLAG_IT_STATE) != 0)
  76. //
  77. // This macro determines if the given if-then state is active.
  78. //
  79. #define IS_THUMB_IT_STATE_ACTIVE(_ItState) (((_ItState) & 0x0F) != 0)
  80. //
  81. // This macro extracts the active condition code from the given if-then state.
  82. //
  83. #define THUMB_CONDITION_FROM_IT_STATE(_ItState) (((_ItState) >> 4) & 0xF)
  84. //
  85. // This macro returns the given if-then state, advanced by one instruction.
  86. //
  87. #define THUMB_ADVANCE_IT_STATE(_ItState) \
  88. ((((_ItState) & 0x07) == 0) ? 0 : \
  89. ((((_ItState) << 1) & 0x1F) | ((_ItState) & 0xE0)))
  90. //
  91. // This macro reverses the if-then state by one instruction, placing the given
  92. // next bit in the next conditional position. This macro assumes the if-then
  93. // state is already active, it does not add the trailing one.
  94. //
  95. #define THUMB_RETREAT_IT_STATE(_ItState, _NextBit) \
  96. ((((_ItState) >> 1) & 0xF) | ((_NextBit) << 4) | ((_ItState) & 0xE0))
  97. //
  98. // This macro returns whether or not the given trap from is from privileged
  99. // mode.
  100. //
  101. #define IS_TRAP_FRAME_FROM_PRIVILEGED_MODE(_TrapFrame) \
  102. (((_TrapFrame)->Cpsr & ARM_MODE_MASK) != ARM_MODE_USER)
  103. //
  104. // This macro determines whether or not the given trap frame is complete or
  105. // left mostly uninitialized by the system call handler. The system call
  106. // handler sets a reserved flag in the CPSR.
  107. //
  108. #define IS_TRAP_FRAME_COMPLETE(_TrapFrame) \
  109. ((_TrapFrame)->ExceptionCpsr != 0xFFFFFFFF)
  110. //
  111. // This macro manipulates the bitfields in the coprocessor access mask.
  112. //
  113. #define ARM_COPROCESSOR_ACCESS_MASK(_Coprocessor) (0x3 << ((_Coprocessor) * 2))
  114. #define ARM_COPROCESSOR_ACCESS(_Coprocessor, _Access) \
  115. ((_Access) << ((_Coprocessor) * 2))
  116. //
  117. // ---------------------------------------------------------------- Definitions
  118. //
  119. #define ARM_INSTRUCTION_LENGTH 4
  120. #define THUMB16_INSTRUCTION_LENGTH 2
  121. #define THUMB32_INSTRUCTION_LENGTH 4
  122. #define ARM_THUMB_BIT 0x00000001
  123. //
  124. // Processor modes.
  125. //
  126. #define ARM_MODE_USER 0x00000010
  127. #define ARM_MODE_FIQ 0x00000011
  128. #define ARM_MODE_IRQ 0x00000012
  129. #define ARM_MODE_SVC 0x00000013
  130. #define ARM_MODE_MON 0x00000016
  131. #define ARM_MODE_ABORT 0x00000017
  132. #define ARM_MODE_HYP 0x0000001A
  133. #define ARM_MODE_UNDEF 0x0000001B
  134. #define ARM_MODE_SYSTEM 0x0000001F
  135. #define ARM_MODE_MASK 0x0000001F
  136. //
  137. // Program Status Register flags.
  138. //
  139. #define PSR_FLAG_NEGATIVE 0x80000000
  140. #define PSR_FLAG_ZERO 0x40000000
  141. #define PSR_FLAG_CARRY 0x20000000
  142. #define PSR_FLAG_OVERFLOW 0x10000000
  143. #define PSR_FLAG_SATURATION 0x08000000
  144. #define PSR_FLAG_JAZELLE 0x01000000
  145. #define PSR_FLAG_THUMB 0x00000020
  146. #define PSR_FLAG_FIQ 0x00000040
  147. #define PSR_FLAG_IRQ 0x00000080
  148. #define PSR_FLAG_ALIGNMENT 0x00000100
  149. #define PSR_FLAG_IT_STATE 0x06000C00
  150. //
  151. // Interrupt vector ranges.
  152. //
  153. #define MINIMUM_VECTOR 0x30
  154. #define MAXIMUM_VECTOR 0xFF
  155. #define MAXIMUM_DEVICE_VECTOR 0xBF
  156. #define INTERRUPT_VECTOR_COUNT (MAXIMUM_VECTOR + 1)
  157. #define IO_PORT_COUNT 0
  158. //
  159. // Interrupt vectors.
  160. //
  161. #define VECTOR_CLOCK_INTERRUPT 0xD0
  162. #define VECTOR_CLOCK_IPI 0xD1
  163. #define VECTOR_IPI_INTERRUPT 0xE0
  164. #define VECTOR_TLB_IPI 0xE1
  165. #define VECTOR_PROFILER_INTERRUPT 0xF0
  166. #define VECTOR_NMI 0xF1
  167. //
  168. // Undefined instructions used for debug breakpoints.
  169. //
  170. #define THUMB_BREAK_INSTRUCTION 0xDE20
  171. #define THUMB_DEBUG_SERVICE_INSTRUCTION 0xDE24
  172. #define THUMB_SINGLE_STEP_INSTRUCTION 0xDE21
  173. #define ARM_BREAK_INSTRUCTION 0xE7F000F3
  174. #define ARM_SINGLE_STEP_INSTRUCTION 0xE7F000F1
  175. #define ARM_DEBUG_SERVICE_INSTRUCTION 0xE7F000F4
  176. //
  177. // Thumb instruction width constants.
  178. //
  179. #define THUMB32_OP_SHIFT 11
  180. #define THUMB32_OP_MASK 0x1F
  181. #define THUMB32_OP_MIN 0x1D
  182. //
  183. // Memory related definitions.
  184. //
  185. #define PAGE_SIZE 4096
  186. #define PAGE_MASK 0x00000FFF
  187. #define PAGE_SHIFT 12
  188. #define EXCEPTION_VECTOR_ADDRESS 0xFFFF0000
  189. #define EXCEPTION_VECTOR_LOW_ADDRESS 0x00000000
  190. //
  191. // Translation table base register address mask.
  192. //
  193. // Bit definitions are tricky for this register because they change based on
  194. // whether or not the Multiprocessing Extensions are supported on the CPU.
  195. //
  196. #define TTBR_ADDRESS_MASK 0x00003FFF
  197. #define TTBR_NO_MP_INNER_CACHEABLE 0x00000001
  198. #define TTBR_SHAREABLE 0x00000002
  199. #define TTBR_NOT_OUTER_SHAREABLE 0x00000020
  200. #define TTBR_MP_INNER_NON_CACHEABLE 0x00000000
  201. #define TTBR_MP_INNER_WRITE_BACK_WRITE_ALLOCATE 0x00000040
  202. #define TTBR_MP_INNER_WRITE_THROUGH 0x00000001
  203. #define TTBR_MP_INNER_WRITE_BACK_NO_WRITE_ALLOCATE 0x00000041
  204. #define TTBR_OUTER_NON_CACHEABLE 0x00000000
  205. #define TTBR_OUTER_WRITE_BACK_WRITE_ALLOCATE 0x00000008
  206. #define TTBR_OUTER_WRITE_THROUGH 0x00000010
  207. #define TTBR_OUTER_WRITE_BACK_NO_WRITE_ALLOCATE 0x00000018
  208. #define TTBR_NO_MP_KERNEL_MASK \
  209. (TTBR_NO_MP_INNER_CACHEABLE | \
  210. TTBR_OUTER_WRITE_BACK_WRITE_ALLOCATE)
  211. #define TTBR_MP_KERNEL_MASK \
  212. (TTBR_SHAREABLE | \
  213. TTBR_MP_INNER_WRITE_BACK_WRITE_ALLOCATE | \
  214. TTBR_OUTER_WRITE_BACK_WRITE_ALLOCATE | \
  215. TTBR_NOT_OUTER_SHAREABLE)
  216. //
  217. // Page table sizes and alignments.
  218. //
  219. #define FLT_SIZE 0x4000
  220. #define FLT_ALIGNMENT 0x4000
  221. #define FLT_INDEX_MASK 0xFFF00000
  222. #define FLT_INDEX_SHIFT 20
  223. #define SLT_SIZE 1024
  224. #define SLT_INDEX_MASK 0x000FF000
  225. #define SLT_INDEX_SHIFT 12
  226. #define SLT_ALIGNMENT 10
  227. //
  228. // First level page table formats.
  229. //
  230. #define FLT_UNMAPPED 0
  231. #define FLT_COARSE_PAGE_TABLE 1
  232. #define FLT_SECTION 2
  233. #define FLT_SUPERSECTION 2
  234. //
  235. // Second level page table formats.
  236. //
  237. #define SLT_UNMAPPED 0
  238. #define SLT_LARGE_PAGE 1
  239. #define SLT_SMALL_PAGE 2
  240. #define SLT_SMALL_PAGE_NO_EXECUTE 3
  241. //
  242. // Second level page table access permission bits.
  243. //
  244. #define SLT_ACCESS_NONE 0
  245. #define SLT_ACCESS_SUPERVISOR 1
  246. #define SLT_ACCESS_USER_READ_ONLY 2
  247. #define SLT_ACCESS_USER_FULL 3
  248. //
  249. // Second level page table access permission bits when the Extended Access Bit
  250. // is set. Note that the "read only all modes" value only works for ARMv7, on
  251. // ARMv6 and below this value was reserved and 2 is the correct value.
  252. //
  253. #define SLT_XACCESS_SUPERVISOR_READ_ONLY 1
  254. #define SLT_XACCESS_READ_ONLY_ALL_MODES 3
  255. //
  256. // Second level page table cache attributes
  257. //
  258. #define SLT_TEX_NORMAL 0
  259. #define SLT_UNCACHED 0
  260. #define SLT_SHARED_DEVICE 1
  261. #define SLT_WRITE_THROUGH 2
  262. #define SLT_WRITE_BACK 3
  263. //
  264. // MMU Control bits (SCTLR, CP15, register 1).
  265. //
  266. #define MMU_ENABLED 0x00000001
  267. #define MMU_ALIGNMENT_FAULT_ENABLED 0x00000002
  268. #define MMU_DCACHE_ENABLED 0x00000004
  269. #define MMU_WRITE_BUFFER_ENABLED 0x00000008
  270. #define MMU_ENDIANNESS 0x00000080
  271. #define MMU_SYSTEM_PROTECTION 0x00000100
  272. #define MMU_ROM_PROTECTION 0x00000200
  273. #define MMU_BRANCH_PREDICTION_ENABLED 0x00000800
  274. #define MMU_ICACHE_ENABLED 0x00001000
  275. #define MMU_HIGH_EXCEPTION_VECTORS 0x00002000
  276. #define MMU_PREDICTABLE_REPLACEMENT 0x00004000
  277. #define MMU_DISABLE_THUMB_DEPRECATED 0x00008000
  278. #define MMU_FAST_INTERRUPTS 0x00200000
  279. #define MMU_UNALIGNED_ACCESS_ENABLED 0x00400000
  280. #define MMU_VMSA6_ENABLED 0x00800000
  281. #define MMU_VECTORED_INTERRUPTS_ENABLED 0x01000000
  282. #define MMU_EXCEPTION_ENDIAN 0x02000000
  283. #define MMU_THUMB_EXCEPTIONS 0x40000000
  284. //
  285. // ARMv6 auxiliary control register bits (ACTLR).
  286. //
  287. #define ARMV6_AUX_16K_CACHE_SIZE 0x00000040
  288. //
  289. // Cortex A17 auxiliary control register bits (ACTLR).
  290. //
  291. #define CORTEX_A17_AUX_SMP_ENABLE 0x00000040
  292. //
  293. // Define multiprocessor ID register bits.
  294. //
  295. #define MPIDR_MP_EXTENSIONS_ENABLED 0x80000000
  296. #define MPIDR_UNIPROCESSOR_SYSTEM 0x40000000
  297. #define MPIDR_LOWEST_AFFINITY_INTERDEPENDENT 0x01000000
  298. //
  299. // Define processor features bits.
  300. //
  301. #define CPUID_PROCESSOR1_SECURITY_EXTENSION_MASK 0x000000F0
  302. #define CPUID_PROCESSOR1_SECURITY_EXTENSION_UNSUPPORTED 0x00000000
  303. #define CPUID_PROCESSOR1_GENERIC_TIMER_MASK 0x000F0000
  304. #define CPUID_PROCESSOR1_GENERIC_TIMER_UNSUPPORTED 0x00000000
  305. //
  306. // Define bits in the ARMv7 Cache Type Register (CTR).
  307. //
  308. #define ARMV7_CACHE_TYPE_DATA_CACHE_SIZE_MASK 0x000F0000
  309. #define ARMV7_CACHE_TYPE_DATA_CACHE_SIZE_SHIFT 16
  310. #define ARMV7_CACHE_TYPE_INSTRUCTION_CACHE_SIZE_MASK 0x0000000F
  311. #define ARMV7_CACHE_TYPE_INSTRUCTION_CACHE_TYPE_MASK 0x0000C000
  312. //
  313. // Physically indexed, physically tagged caches are the easiest to deal with.
  314. //
  315. #define ARMV7_CACHE_TYPE_INSTRUCTION_CACHE_TYPE_PIPT 0x0000C000
  316. //
  317. // Define bits in the ARMv6 Cache Type Register (CTR).
  318. //
  319. #define ARMV6_CACHE_TYPE_SEPARATE_MASK 0x01000000
  320. #define ARMV6_CACHE_TYPE_DATA_CACHE_SIZE_MASK 0x003C0000
  321. #define ARMV6_CACHE_TYPE_DATA_CACHE_SIZE_SHIFT 18
  322. #define ARMV6_CACHE_TYPE_DATA_CACHE_LENGTH_MASK 0x00003000
  323. #define ARMV6_CACHE_TYPE_DATA_CACHE_LENGTH_SHIFT 12
  324. #define ARMV6_CACHE_TYPE_INSTRUCTION_CACHE_LENGTH_MASK 0x00000003
  325. //
  326. // Define ARM fault status bits.
  327. //
  328. #define ARM_FAULT_STATUS_EXTERNAL 0x00001000
  329. #define ARM_FAULT_STATUS_WRITE 0x00000800
  330. #define ARM_FAULT_STATUS_TYPE_MASK 0x0000040F
  331. #define ARM_FAULT_STATUS_TYPE_ALIGNMENT 0x00000001
  332. #define ARM_FAULT_STATUS_TYPE_ICACHE_MAINTENANCE 0x00000004
  333. #define ARM_FAULT_STATUS_TYPE_SYNCHRONOUS_EXTERNAL_FIRST_LEVEL 0x0000000C
  334. #define ARM_FAULT_STATUS_TYPE_SYNCHRONOUS_EXTERNAL_SECOND_LEVEL 0x0000000E
  335. #define ARM_FAULT_STATUS_TYPE_PARITY_FIRST_LEVEL 0x0000040C
  336. #define ARM_FAULT_STATUS_TYPE_PARITY_SECOND_LEVEL 0x0000040E
  337. #define ARM_FAULT_STATUS_TYPE_SECTION_TRANLSATION 0x00000005
  338. #define ARM_FAULT_STATUS_TYPE_PAGE_TRANSLATION 0x00000007
  339. #define ARM_FAULT_STATUS_TYPE_SECTION_ACCESS 0x00000003
  340. #define ARM_FAULT_STATUS_TYPE_PAGE_ACCESS 0x00000006
  341. #define ARM_FAULT_STATUS_TYPE_SECTION_DOMAIN 0x00000009
  342. #define ARM_FAULT_STATUS_TYPE_PAGE_DOMAIN 0x0000000B
  343. #define ARM_FAULT_STATUS_TYPE_SECTION_PERMISSION 0x0000000D
  344. #define ARM_FAULT_STATUS_TYPE_PAGE_PERMISSION 0x0000000F
  345. #define ARM_FAULT_STATUS_TYPE_DEBUG 0x00000002
  346. #define ARM_FAULT_STATUS_TYPE_SYNCHRONOUS_EXTERNAL 0x00000008
  347. #define ARM_FAULT_STATUS_TYPE_PARITY_MEMORY 0x00000409
  348. #define ARM_FAULT_STATUS_TYPE_ASYNCHRONOUS_EXTERNAL 0x00000406
  349. #define ARM_FAULT_STATUS_TYPE_ASYNCHRONOUS_PARITY 0x00000408
  350. //
  351. // Define ARM coprocessor access values.
  352. //
  353. #define ARM_COPROCESSOR_ACCESS_NONE 0x0
  354. #define ARM_COPROCESSOR_ACCESS_SUPERVISOR 0x1
  355. #define ARM_COPROCESSOR_ACCESS_FULL 0x3
  356. //
  357. // Define ARM floating point system ID (FPSID) register values.
  358. //
  359. #define ARM_FPSID_IMPLEMENTER_MASK 0xFF000000
  360. #define ARM_FPSID_IMPLEMENTER_SHIFT 24
  361. #define ARM_FPSID_IMPLEMENTER_ARM 0x41
  362. #define ARM_FPSID_SOFTWARE (1 << 23)
  363. #define ARM_FPSID_SUBARCHITECTURE_MASK 0x007F0000
  364. #define ARM_FPSID_SUBARCHITECTURE_SHIFT 16
  365. #define ARM_FPSID_SUBARCHITECTURE_VFPV1 0
  366. #define ARM_FPSID_SUBARCHITECTURE_VFPV2 1
  367. #define ARM_FPSID_SUBARCHITECTURE_VFPV3_COMMON_V2 2
  368. #define ARM_FPSID_SUBARCHITECTURE_VFPV3 3
  369. #define ARM_FPSID_SUBARCHITECTURE_VFPV3_COMMON_V3 4
  370. //
  371. // Define the FPU/SIMD extensions register values.
  372. //
  373. #define ARM_MVFR0_SIMD_REGISTERS_MASK 0x0000000F
  374. #define ARM_MVFR0_SIMD_REGISTERS_NONE 0
  375. #define ARM_MVFR0_SIMD_REGISTERS_16 1
  376. #define ARM_MVFR0_SIMD_REGISTERS_32 2
  377. //
  378. // Define the FPU/SIMD exception control register.
  379. //
  380. #define ARM_FPEXC_EXCEPTION 0x80000000
  381. #define ARM_FPEXC_ENABLE 0x40000000
  382. //
  383. // Define floating point status registers.
  384. //
  385. #define ARM_FPSCR_FLUSH_TO_ZERO (1 << 24)
  386. #define ARM_FPSCR_DEFAULT_NAN (1 << 25)
  387. //
  388. // Define the required alignment for FPU context.
  389. //
  390. #define FPU_CONTEXT_ALIGNMENT 16
  391. //
  392. // Define ARM Main ID register values.
  393. //
  394. #define ARM_MAIN_ID_IMPLEMENTOR_MASK 0xFF000000
  395. #define ARM_MAIN_ID_IMPLEMENTER_SHIFT 24
  396. #define ARM_MAIN_ID_VARIANT_MASK 0x00F00000
  397. #define ARM_MAIN_ID_VARIANT_SHIFT 20
  398. #define ARM_MAIN_ID_ARCHITECTURE_MASK 0x000F0000
  399. #define ARM_MAIN_ID_ARCHITECTURE_SHIFT 16
  400. #define ARM_MAIN_ID_PART_MASK 0x0000FFF0
  401. #define ARM_MAIN_ID_PART_SHIFT 4
  402. #define ARM_MAIN_ID_REVISION_MASK 0x0000000F
  403. #define ARM_MAIN_ID_ARCHITECTURE_ARMV4 1
  404. #define ARM_MAIN_ID_ARCHITECTURE_ARMV4T 2
  405. #define ARM_MAIN_ID_ARCHITECTURE_ARMV5 3
  406. #define ARM_MAIN_ID_ARCHITECTURE_ARMV5T 4
  407. #define ARM_MAIN_ID_ARCHITECTURE_ARMV5TE 5
  408. #define ARM_MAIN_ID_ARCHITECTURE_ARMV5TEJ 6
  409. #define ARM_MAIN_ID_ARCHITECTURE_ARMV6 7
  410. #define ARM_MAIN_ID_ARCHITECTURE_CPUID 0xF
  411. //
  412. // Define performance monitor control register bits.
  413. //
  414. #define PERF_CONTROL_CYCLE_COUNT_DIVIDE_64 0x00000008
  415. #define PERF_CONTROL_ENABLE 0x00000001
  416. //
  417. // Define the cycle counter performance monitor bit.
  418. //
  419. #define PERF_MONITOR_CYCLE_COUNTER 0x80000000
  420. //
  421. // Define the mask of all performance counter bits.
  422. //
  423. #define PERF_MONITOR_COUNTER_MASK 0xFFFFFFFF
  424. //
  425. // Define performance monitor user mode access enable bit.
  426. //
  427. #define PERF_USER_ACCESS_ENABLE 0x00000001
  428. //
  429. // Define the interrupt mask for the ARM1176 (ARMv6) PMCR.
  430. //
  431. #define ARMV6_PERF_MONITOR_INTERRUPT_MASK 0x00000070
  432. //
  433. // Define the size of an exception stack, in bytes.
  434. //
  435. #define EXCEPTION_STACK_SIZE 8
  436. //
  437. // Define the number of exception stacks that are needed (IRQ, FIQ, Abort,
  438. // and Undefined instruction).
  439. //
  440. #define EXCEPTION_STACK_COUNT 4
  441. //
  442. // Define which bits of the MPIDR are valid processor ID bits.
  443. //
  444. #define ARM_PROCESSOR_ID_MASK 0x00FFFFFF
  445. //
  446. // Define the Secure Configuration Register values.
  447. //
  448. #define SCR_NON_SECURE 0x00000001
  449. #define SCR_MONITOR_MODE_IRQ 0x00000002
  450. #define SCR_MONITOR_MODE_FIQ 0x00000004
  451. #define SCR_MONITOR_MODE_EXTERNAL_ABORT 0x00000008
  452. #define SCR_CPSR_FIQ_WRITABLE 0x00000010
  453. #define SCR_CPSR_ASYNC_ABORT_WRITABLE 0x00000020
  454. #define SCR_EARLY_TERMINATION_DISABLED 0x00000040
  455. #define SCR_NON_SECURE_SMC_DISABLED 0x00000080
  456. #define SCR_NON_SECURE_HVC_ENABLED 0x00000100
  457. #define SCR_NON_SECURE_INSTRUCTION_FETCH_DISABLED 0x00000200
  458. //
  459. // ------------------------------------------------------ Data Type Definitions
  460. //
  461. typedef
  462. KSTATUS
  463. (*PGET_NEXT_PC_READ_MEMORY_FUNCTION) (
  464. PVOID Address,
  465. ULONG Size,
  466. PVOID Data
  467. );
  468. /*++
  469. Routine Description:
  470. This routine attempts to read memory on behalf of the function trying to
  471. figure out what the next instruction will be.
  472. Arguments:
  473. Address - Supplies the virtual address that needs to be read.
  474. Size - Supplies the number of bytes to be read.
  475. Data - Supplies a pointer to the buffer where the read data will be
  476. returned on success.
  477. Return Value:
  478. Status code. STATUS_SUCCESS will only be returned if all the requested
  479. bytes could be read.
  480. --*/
  481. typedef
  482. BOOL
  483. (*PARM_HANDLE_EXCEPTION) (
  484. PTRAP_FRAME TrapFrame
  485. );
  486. /*++
  487. Routine Description:
  488. This routine is called to handle an ARM exception. Interrupts are disabled
  489. upon entry, and may be enabled during this function.
  490. Arguments:
  491. TrapFrame - Supplies a pointer to the exception trap frame.
  492. Return Value:
  493. TRUE if the exception was handled.
  494. FALSE if the exception was not handled.
  495. --*/
  496. /*++
  497. Structure Description:
  498. This structure defines the VFPv3 floating point state of the ARM
  499. architecture.
  500. Members:
  501. Registers - Stores the floating point state.
  502. --*/
  503. struct _FPU_CONTEXT {
  504. ULONGLONG Registers[32];
  505. ULONG Fpscr;
  506. } PACKED ALIGNED16;
  507. /*++
  508. Structure Description:
  509. This structure outlines a trap frame that will be generated during most
  510. interrupts and exceptions.
  511. Members:
  512. Registers - Stores the current state of the machine's registers. These
  513. values will be restored upon completion of the interrupt or exception.
  514. --*/
  515. struct _TRAP_FRAME {
  516. ULONG SvcSp;
  517. ULONG UserSp;
  518. ULONG UserLink;
  519. ULONG R0;
  520. ULONG ExceptionCpsr;
  521. ULONG R1;
  522. ULONG R2;
  523. ULONG R3;
  524. ULONG R4;
  525. ULONG R5;
  526. ULONG R6;
  527. ULONG R7;
  528. ULONG R8;
  529. ULONG R9;
  530. ULONG R10;
  531. ULONG R11;
  532. ULONG R12;
  533. ULONG SvcLink;
  534. ULONG Pc;
  535. ULONG Cpsr;
  536. };
  537. /*++
  538. Structure Description:
  539. This structure outlines the register state saved by the kernel when a
  540. user mode signal is dispatched. This generally contains 1) control
  541. registers which are clobbered by switching to the signal handler, and
  542. 2) volatile registers.
  543. Members:
  544. Common - Stores the common signal context information.
  545. TrapFrame - Stores the general register state.
  546. FpuContext - Stores the FPU state.
  547. --*/
  548. typedef struct _SIGNAL_CONTEXT_ARM {
  549. SIGNAL_CONTEXT Common;
  550. TRAP_FRAME TrapFrame;
  551. FPU_CONTEXT FpuContext;
  552. } PACKED SIGNAL_CONTEXT_ARM, *PSIGNAL_CONTEXT_ARM;
  553. /*++
  554. Structure Description:
  555. This structure contains the state of the processor, including both the
  556. non-volatile general registers and the system registers configured by the
  557. kernel. This structure is used in a manner similar to the C library
  558. setjmp/longjmp routines, the save context function appears to return
  559. twice. It returns once after the saving is complete, and then again with
  560. a different return value after restoring.
  561. Members:
  562. Pc - Stores the PC to branch to upon restore. By default this is
  563. initialized to the return address of the save/restore function, though
  564. it can be manipulated after the function returns.
  565. R0 - Stores the R0 register, also the return value from the restore
  566. operation. By default this is initialized to 1.
  567. R1 - Stores the R1 register, which can be used for a second argument in
  568. case this context is being manipulated.
  569. R2 - Stores the R2 register, which can be used for a third argument in
  570. case the PC is manipulated after save context returns.
  571. R3 - Stores the R3 register, which can be used for a third argument in
  572. case the PC is manipulated after save context returns.
  573. Cpsr - Stores the program status word (processor flags and mode).
  574. Sp - Stores the stack pointer (in SVC mode, which is assumed to be the
  575. current mode when the context was saved).
  576. R4 - Stores a non-volatile register.
  577. R5 - Stores a non-volatile register.
  578. R6 - Stores a non-volatile register.
  579. R7 - Stores a non-volatile register.
  580. R8 - Stores a non-volatile register.
  581. R9 - Stores a non-volatile register.
  582. R10 - Stores a non-volatile register.
  583. R11 - Stores a non-volatile register. R12 is volatile, and is not available
  584. since the restore code needs a register for its operation.
  585. UserLink - Stores the user mode link register.
  586. UserSp - Stores the user mode stack pointer.
  587. IrqLink - Stores the interrupt mode link register.
  588. IrqSp - Stores the interrupt link stack pointer.
  589. FiqLink - Stores the fast interrupt link register.
  590. FiqSp - Stores the fast interrupt stack pointer.
  591. AbortLink - Stores the abort mode link register.
  592. AbortSp - Stores the abort mode stack pointer.
  593. UndefLink - Stores the undefined instruction mode link pointer.
  594. UndefSp - Stores the undefined instruction mode stack pointer.
  595. VirtualAddress - Stores the virtual address of this structure member. The
  596. restore process might enable paging when the SCTLR is restored, so this
  597. contains the address to continue the restore from in virtual land.
  598. Sctlr - Stores the system control register.
  599. Ttbr0 - Stores the translation table base register 0.
  600. Ttbr1 - Stores the translation table base register 1.
  601. Actlr - Stores the auxiliary system control register.
  602. Cpacr - Stores the coprocessor access control register.
  603. Prrr - Stores the primary region remap register.
  604. Nmrr - Stores the normal memory remap register.
  605. ContextIdr - Stores the ASID register.
  606. Dfsr - Stores the data fault status register.
  607. Dfar - Store the data fault address register.
  608. Ifsr - Stores the instruction fault status register.
  609. Ifar - Stores the instruction fault address register.
  610. Dacr - Stores the domain access control register.
  611. Vbar - Stores the virtual base address register.
  612. Tpidrprw - Stores the privileged thread pointer register.
  613. Tpidruro - Stores the user read-only thread pointer register.
  614. Tpidrurw - Stores the user read-write thread pointer register.
  615. Pmcr - Stores the performance control register.
  616. Pminten - Stores the performance enabled interrupts.
  617. Pmuserenr - Stores the performance user enable register.
  618. Pmcnten - Stores the performance counter enable value.
  619. Pmccntr - Stores the cycle counter value.
  620. --*/
  621. struct _PROCESSOR_CONTEXT {
  622. ULONG Pc;
  623. ULONG R0;
  624. ULONG R1;
  625. ULONG R2;
  626. ULONG R3;
  627. ULONG Cpsr;
  628. ULONG Sp;
  629. ULONG R4;
  630. ULONG R5;
  631. ULONG R6;
  632. ULONG R7;
  633. ULONG R8;
  634. ULONG R9;
  635. ULONG R10;
  636. ULONG R11;
  637. ULONG UserLink;
  638. ULONG UserSp;
  639. ULONG IrqLink;
  640. ULONG IrqSp;
  641. ULONG FiqLink;
  642. ULONG FiqSp;
  643. ULONG AbortLink;
  644. ULONG AbortSp;
  645. ULONG UndefLink;
  646. ULONG UndefSp;
  647. ULONG VirtualAddress;
  648. ULONG Sctlr;
  649. ULONG Ttbr0;
  650. ULONG Ttbr1;
  651. ULONG Actlr;
  652. ULONG Cpacr;
  653. ULONG Prrr;
  654. ULONG Nmrr;
  655. ULONG ContextIdr;
  656. ULONG Dfsr;
  657. ULONG Dfar;
  658. ULONG Ifsr;
  659. ULONG Ifar;
  660. ULONG Dacr;
  661. ULONG Vbar;
  662. ULONG Tpidrprw;
  663. ULONG Tpidruro;
  664. ULONG Tpidrurw;
  665. ULONG Pmcr;
  666. ULONG Pminten;
  667. ULONG Pmuserenr;
  668. ULONG Pmcntenset;
  669. ULONG Pmccntr;
  670. };
  671. /*++
  672. Structure Description:
  673. This structure outlines an ARM interrupt dispatch table. The first half of
  674. this table is defined by the hardware, and contains instructions at known
  675. locations where the PC is snapped to when various types of exceptions occur.
  676. The second half of the table contains pointers to handler routines. The
  677. instructions in the table by default contain load PC instructions for the
  678. corresponding pointers. The locations of these pointers (but not their
  679. values) need to be kept near to the jump table because a ldr instruction
  680. can only reach so far.
  681. Members:
  682. ResetInstruction - Stores the instruction to execute on a Reset.
  683. UndefinedInstructionInstruction - Stores the instruction to execute
  684. upon encountering an undefined instruction.
  685. SoftwareInterruptInstruction - Stores the instruction to execute on a SWI
  686. instruction.
  687. PrefetchAbortInstruction - Stores the instruction to execute on an
  688. instruction fetch page fault.
  689. DataAbortInstruction - Stores the instruction to execute on a data access
  690. fault.
  691. Reserved - This space is reserved by the ARM ISA.
  692. IrqInstruction - Stores the instruction to execute on an IRQ interrupt.
  693. FiqInstruction - Stores the instruction to execute on an FIQ interrupt.
  694. UndefinedInstructionVector - Stores the address to jump to on encountering
  695. an undefined instruction. This is used for setting software
  696. breakpoints.
  697. SoftwareInterruptVector - Stores the address to jump to on encountering
  698. an SWI instruction. This is used for user to kernel transitions.
  699. PrefetchAbortVector - Stores the address to jump to on encountering an
  700. instruction fetch fault.
  701. DataAbortVector - Stores the address to jump to on encountering a data
  702. access fault.
  703. IrqVector - Stores the address to jump to on an IRQ interrupt.
  704. FiqVector - Stores the address to jump to on an FIQ interrupt.
  705. ResetVector - Stores the address to jump to on a reset.
  706. --*/
  707. typedef struct _ARM_INTERRUPT_TABLE {
  708. ULONG ResetInstruction;
  709. ULONG UndefinedInstructionInstruction;
  710. ULONG SoftwareInterruptInstruction;
  711. ULONG PrefetchAbortInstruction;
  712. ULONG DataAbortInstruction;
  713. ULONG Reserved;
  714. ULONG IrqInstruction;
  715. ULONG FiqInstruction;
  716. PVOID UndefinedInstructionVector;
  717. PVOID SoftwareInterruptVector;
  718. PVOID PrefetchAbortVector;
  719. PVOID DataAbortVector;
  720. PVOID IrqVector;
  721. PVOID FiqVector;
  722. PVOID ResetVector;
  723. } ARM_INTERRUPT_TABLE, *PARM_INTERRUPT_TABLE;
  724. /*++
  725. Structure Description:
  726. This structure describes the first level page table entry for a "Coarse
  727. Page Table". It is equivalent to a PDE for x86.
  728. Members:
  729. Format - Stores the format of this table entry, which should be set to
  730. 1 to describe this structure, a Coarse Page Table. Other formats
  731. include Section (2), and Fault (0). Not present entries should set this
  732. to 0 (Fault).
  733. Reserved - Set to 0.
  734. Domain - Stores the broad level domain this entry falls under.
  735. ImplementationDefined - Stores an implementation-defined bit.
  736. Entry - Stores the high 22 bits of the physical address for the second
  737. level page table. The low 12 bits are 0 because the second level page
  738. table must be page-aligned.
  739. --*/
  740. typedef struct _FIRST_LEVEL_TABLE {
  741. ULONG Format:2;
  742. ULONG Reserved:3;
  743. ULONG Domain:4;
  744. ULONG ImplementationDefined:1;
  745. ULONG Entry:22;
  746. } FIRST_LEVEL_TABLE, *PFIRST_LEVEL_TABLE;
  747. /*++
  748. Structure Description:
  749. This structure describes the second level page table entry format for "Small
  750. Pages", which are 4KB in size.
  751. Members:
  752. Format - Stores the format of the second level page table entry. For this
  753. structure, this should be set to 2 or 3 (Extended Small Page). Unmapped
  754. pages would be marked 0 (Fault). Large pages would be marked 1.
  755. CacheAttributes - Stores the caching attributes for the page. Options are
  756. uncached, shared device, write back, and write through.
  757. Access - Stores the access permissions for user mode and supervisor mode to
  758. the page.
  759. CacheTypeExtension - Stores extension bits to the caching attributes. Set
  760. to 0 for most cache types.
  761. AccessExtension - Stores the extension bit to the access attributes. Set to
  762. 0 for read-only modes and 1 for full access modes.
  763. Shared - Stores whether or not this page is shared among multiple processors
  764. or restricted to one. This only applies for normal memory, device
  765. memory uses the TEX + CB (CacheAttributes) bits.
  766. NotGlobal - Stores whether this page is global (0) or local to the current
  767. process.
  768. Entry - Stores the high 20 bits of the physical address of the "Small page".
  769. --*/
  770. typedef struct _SECOND_LEVEL_TABLE {
  771. ULONG Format:2;
  772. ULONG CacheAttributes:2;
  773. ULONG Access:2;
  774. ULONG CacheTypeExtension:3;
  775. ULONG AccessExtension:1;
  776. ULONG Shared:1;
  777. ULONG NotGlobal:1;
  778. ULONG Entry:20;
  779. } SECOND_LEVEL_TABLE, *PSECOND_LEVEL_TABLE;
  780. /*++
  781. Structure Description:
  782. This structure passes information about the ARM CPU Identification
  783. registers.
  784. Members:
  785. ProcessorFeatures - Stores a bitfield of processor features (ID_PFR0 and
  786. ID_PFR1).
  787. DebugFeatures - Stores a bitfield of debug hardware features (ID_DFR0).
  788. AuxiliaryFeatures - Stores an implementation-defined feature bitfield
  789. (ID_AFR0).
  790. MemoryModelFeatures - Stores bitfields of memory model features (ID_MMFR0,
  791. ID_MMFR1, ID_MMFR2, and ID_MMFR3).
  792. IsaFeatures - Stores bitfields about the supported instruction sets on
  793. this processor (ID_ISAR0, ID_ISAR1, ID_ISAR2, ID_ISAR3, ID_ISAR4, and
  794. ID_ISAR5).
  795. --*/
  796. typedef struct _ARM_CPUID {
  797. ULONG ProcessorFeatures[2];
  798. ULONG DebugFeatures;
  799. ULONG AuxiliaryFeatures;
  800. ULONG MemoryModelFeatures[4];
  801. ULONG IsaFeatures[6];
  802. } PACKED ARM_CPUID, *PARM_CPUID;
  803. /*++
  804. Structure Description:
  805. This structure defines the architecture specific form of an address space
  806. structure.
  807. Members:
  808. Common - Stores the common address space information.
  809. PageDirectory - Stores the virtual address of the top level page directory.
  810. PageDirectoryPhysical - Stores the physical address of the top level page
  811. directory.
  812. PageTableCount - Stores the number of page tables (4k) allocated on
  813. behalf of this process (user mode only).
  814. --*/
  815. typedef struct _ADDRESS_SPACE_ARM {
  816. ADDRESS_SPACE Common;
  817. PFIRST_LEVEL_TABLE PageDirectory;
  818. ULONG PageDirectoryPhysical;
  819. ULONG PageTableCount;
  820. } ADDRESS_SPACE_ARM, *PADDRESS_SPACE_ARM;
  821. //
  822. // -------------------------------------------------------------------- Globals
  823. //
  824. //
  825. // -------------------------------------------------------- Function Prototypes
  826. //
  827. ULONG
  828. ArGetCacheTypeRegister (
  829. VOID
  830. );
  831. /*++
  832. Routine Description:
  833. This routine retrieves the Cache Type Register (CTR) from the system
  834. coprocessor.
  835. Arguments:
  836. None.
  837. Return Value:
  838. Returns the value of the CTR.
  839. --*/
  840. VOID
  841. ArCleanInvalidateEntireCache (
  842. VOID
  843. );
  844. /*++
  845. Routine Description:
  846. This routine cleans and invalidates the entire data cache.
  847. Arguments:
  848. None.
  849. Return Value:
  850. None.
  851. --*/
  852. ULONG
  853. ArLockTlbEntry (
  854. ULONG TlbEntry,
  855. PVOID VirtualAddress,
  856. ULONG NextTlbEntry
  857. );
  858. /*++
  859. Routine Description:
  860. This routine locks a translation in the TLB. This translation will stick
  861. even across total TLB invalidates.
  862. Arguments:
  863. TlbEntry - Supplies the base and victim number of the TLB entry to lock.
  864. VirtualAddress - Supplies the virtual address that should be locked in the
  865. TLB. The association to physical address will be created by touching
  866. that address, so the address had better be mapped.
  867. NextTlbEntry - Supplies the base and victim number to set after locking the
  868. entry.
  869. Return Value:
  870. Returns the value of the lockdown register after the TLB miss was forced.
  871. The lowest bit of this value should be set. If it is not, this indicates
  872. that TLB lockdown is not supported.
  873. --*/
  874. VOID
  875. ArpInitializeExceptionStacks (
  876. PVOID ExceptionStacksBase,
  877. ULONG ExceptionStackSize
  878. );
  879. /*++
  880. Routine Description:
  881. This routine initializes the stack pointer for all privileged ARM modes. It
  882. switches into each mode and initializes the banked r13. This function
  883. should be called with interrupts disabled and returns with interrupts
  884. disabled.
  885. Arguments:
  886. ExceptionStacksBase - Supplies a pointer to the lowest address that should
  887. be used for exception stacks. Each stack takes up 16 bytes and there are
  888. 4 modes, so at least 64 bytes are needed.
  889. ExceptionStackSize - Supplies the size of each exception stack in bytes.
  890. Return Value:
  891. None.
  892. --*/
  893. VOID
  894. ArpInitializePerformanceMonitor (
  895. VOID
  896. );
  897. /*++
  898. Routine Description:
  899. This routine initializes the system's performance monitor.
  900. Arguments:
  901. None.
  902. Return Value:
  903. None.
  904. --*/
  905. VOID
  906. ArpUndefinedInstructionEntry (
  907. VOID
  908. );
  909. /*++
  910. Routine Description:
  911. This routine directly handles an exception generated by an undefined
  912. instruction.
  913. Arguments:
  914. None.
  915. Return Value:
  916. None.
  917. --*/
  918. INTN
  919. ArpSoftwareInterruptEntry (
  920. VOID
  921. );
  922. /*++
  923. Routine Description:
  924. This routine directly handles an exception generated by a software
  925. interrupt (a system call). Upon entry, R0 holds the system call number,
  926. and R1 holds the system call parameter.
  927. Arguments:
  928. None.
  929. Return Value:
  930. STATUS_SUCCESS or positive integer on success.
  931. Error status code on failure.
  932. --*/
  933. VOID
  934. ArpPrefetchAbortEntry (
  935. VOID
  936. );
  937. /*++
  938. Routine Description:
  939. This routine directly handles an exception generated by a prefetch abort
  940. (page fault).
  941. Arguments:
  942. None.
  943. Return Value:
  944. None.
  945. --*/
  946. VOID
  947. ArpDataAbortEntry (
  948. VOID
  949. );
  950. /*++
  951. Routine Description:
  952. This routine directly handles an exception generated by a data abort (page
  953. fault).
  954. Arguments:
  955. None.
  956. Return Value:
  957. None.
  958. --*/
  959. VOID
  960. ArpIrqEntry (
  961. VOID
  962. );
  963. /*++
  964. Routine Description:
  965. This routine directly handles an exception generated by an external
  966. interrupt on the IRQ pin.
  967. Arguments:
  968. None.
  969. Return Value:
  970. None.
  971. --*/
  972. VOID
  973. ArpFiqEntry (
  974. VOID
  975. );
  976. /*++
  977. Routine Description:
  978. This routine directly handles an exception generated by an external
  979. interrupt on the FIQ pin.
  980. Arguments:
  981. None.
  982. Return Value:
  983. None.
  984. --*/
  985. PVOID
  986. ArGetDataFaultingAddress (
  987. VOID
  988. );
  989. /*++
  990. Routine Description:
  991. This routine determines which address caused a data abort.
  992. Arguments:
  993. None.
  994. Return Value:
  995. Returns the faulting address.
  996. --*/
  997. VOID
  998. ArSetDataFaultingAddress (
  999. PVOID Value
  1000. );
  1001. /*++
  1002. Routine Description:
  1003. This routine sets the data faulting address register (DFAR).
  1004. Arguments:
  1005. Value - Supplies the value to set.
  1006. Return Value:
  1007. None.
  1008. --*/
  1009. PVOID
  1010. ArGetInstructionFaultingAddress (
  1011. VOID
  1012. );
  1013. /*++
  1014. Routine Description:
  1015. This routine determines which address caused a prefetch abort.
  1016. Arguments:
  1017. None.
  1018. Return Value:
  1019. Returns the faulting address.
  1020. --*/
  1021. VOID
  1022. ArSetInstructionFaultingAddress (
  1023. PVOID Value
  1024. );
  1025. /*++
  1026. Routine Description:
  1027. This routine sets the instruction faulting address register (IFAR).
  1028. Arguments:
  1029. Value - Supplies the value to set.
  1030. Return Value:
  1031. None.
  1032. --*/
  1033. ULONG
  1034. ArGetDataFaultStatus (
  1035. VOID
  1036. );
  1037. /*++
  1038. Routine Description:
  1039. This routine determines the reason for the fault by reading the DFSR
  1040. register.
  1041. Arguments:
  1042. None.
  1043. Return Value:
  1044. Returns the contents of the Data Fault Status Register.
  1045. --*/
  1046. VOID
  1047. ArSetDataFaultStatus (
  1048. ULONG Value
  1049. );
  1050. /*++
  1051. Routine Description:
  1052. This routine sets the data fault status register (DFSR).
  1053. Arguments:
  1054. Value - Supplies the value to set.
  1055. Return Value:
  1056. None.
  1057. --*/
  1058. ULONG
  1059. ArGetInstructionFaultStatus (
  1060. VOID
  1061. );
  1062. /*++
  1063. Routine Description:
  1064. This routine determines the reason for the prefetch abort by reading the
  1065. IFAR register.
  1066. Arguments:
  1067. None.
  1068. Return Value:
  1069. Returns the contents of the Instruction Fault Status Register.
  1070. --*/
  1071. VOID
  1072. ArSetInstructionFaultStatus (
  1073. ULONG Value
  1074. );
  1075. /*++
  1076. Routine Description:
  1077. This routine sets the instruction fault status register (IFSR).
  1078. Arguments:
  1079. Value - Supplies the value to set.
  1080. Return Value:
  1081. None.
  1082. --*/
  1083. VOID
  1084. ArCpuid (
  1085. PARM_CPUID Features
  1086. );
  1087. /*++
  1088. Routine Description:
  1089. This routine returns the set of processor features present on the current
  1090. processor.
  1091. Arguments:
  1092. Features - Supplies a pointer where the processor feature register values
  1093. will be returned.
  1094. Return Value:
  1095. None.
  1096. --*/
  1097. ULONG
  1098. ArGetSystemControlRegister (
  1099. VOID
  1100. );
  1101. /*++
  1102. Routine Description:
  1103. This routine returns the MMU system control register (SCTLR).
  1104. Arguments:
  1105. None.
  1106. Return Value:
  1107. Returns the current SCTLR value.
  1108. --*/
  1109. VOID
  1110. ArSetSystemControlRegister (
  1111. ULONG NewValue
  1112. );
  1113. /*++
  1114. Routine Description:
  1115. This routine sets the MMU system control register (SCTLR).
  1116. Arguments:
  1117. NewValue - Supplies the value to set as the new MMU SCTLR.
  1118. Return Value:
  1119. None.
  1120. --*/
  1121. ULONG
  1122. ArGetAuxiliaryControlRegister (
  1123. VOID
  1124. );
  1125. /*++
  1126. Routine Description:
  1127. This routine returns the auxiliary system control register (ACTLR).
  1128. Arguments:
  1129. None.
  1130. Return Value:
  1131. Returns the current value.
  1132. --*/
  1133. VOID
  1134. ArSetAuxiliaryControlRegister (
  1135. ULONG NewValue
  1136. );
  1137. /*++
  1138. Routine Description:
  1139. This routine sets the auxiliary system control register (ACTLR).
  1140. Arguments:
  1141. NewValue - Supplies the value to set.
  1142. Return Value:
  1143. None.
  1144. --*/
  1145. PVOID
  1146. ArGetVectorBaseAddress (
  1147. VOID
  1148. );
  1149. /*++
  1150. Routine Description:
  1151. This routine gets the vector base address register (VBAR) which determines
  1152. where the ARM exception vector table starts.
  1153. Arguments:
  1154. None.
  1155. Return Value:
  1156. Returns the current VBAR.
  1157. --*/
  1158. VOID
  1159. ArSetVectorBaseAddress (
  1160. PVOID VectorBaseAddress
  1161. );
  1162. /*++
  1163. Routine Description:
  1164. This routine sets the vector base address register (VBAR) which determines
  1165. where the ARM exception vector table starts.
  1166. Arguments:
  1167. VectorBaseAddress - Supplies a pointer to the ARM exception vector base
  1168. address. This value must be 32-byte aligned.
  1169. Return Value:
  1170. None.
  1171. --*/
  1172. PVOID
  1173. ArGetProcessorBlockRegister (
  1174. VOID
  1175. );
  1176. /*++
  1177. Routine Description:
  1178. This routine gets the register used to store a pointer to the processor
  1179. block (TPIDRPRW in the ARMARM; Thread and Process ID Registers in the
  1180. ARM1176 TRM).
  1181. Arguments:
  1182. None.
  1183. Return Value:
  1184. Returns a pointer to the processor block.
  1185. --*/
  1186. PVOID
  1187. ArGetProcessorBlockRegisterForDebugger (
  1188. VOID
  1189. );
  1190. /*++
  1191. Routine Description:
  1192. This routine gets the register used to store a pointer to the processor
  1193. block (TPIDRPRW in the ARMARM; Thread and Process ID Registers in the
  1194. ARM1176 TRM). This routine is called inside the debugger.
  1195. Arguments:
  1196. None.
  1197. Return Value:
  1198. Returns a pointer to the processor block.
  1199. --*/
  1200. VOID
  1201. ArSetProcessorBlockRegister (
  1202. PVOID ProcessorBlockRegisterValue
  1203. );
  1204. /*++
  1205. Routine Description:
  1206. This routine sets the register used to store a pointer to the processor
  1207. block (TPIDRPRW in the ARMARM; Thread and Process ID Registers in the
  1208. ARM1176 TRM).
  1209. Arguments:
  1210. ProcessorBlockRegisterValue - Supplies the value to assign to the register
  1211. used to store the processor block.
  1212. Return Value:
  1213. None.
  1214. --*/
  1215. UINTN
  1216. ArDereferenceProcessorBlock (
  1217. UINTN Offset
  1218. );
  1219. /*++
  1220. Routine Description:
  1221. This routine performs a native integer read of the processor block plus
  1222. a given offset. The C equivalent of this would be
  1223. *((PUINTN)(ProcessorBlock + Offset)).
  1224. Arguments:
  1225. Offset - Supplies the offset into the processor block to read.
  1226. Return Value:
  1227. Returns the native integer read at the given address.
  1228. --*/
  1229. ULONG
  1230. ArGetTranslationTableBaseRegister0 (
  1231. VOID
  1232. );
  1233. /*++
  1234. Routine Description:
  1235. This routine gets the translation table base register 0 (TTBR0), used as
  1236. the base for all virtual to physical memory lookups.
  1237. Arguments:
  1238. None.
  1239. Return Value:
  1240. Returns the contents of TTBR0.
  1241. --*/
  1242. VOID
  1243. ArSetTranslationTableBaseRegister0 (
  1244. ULONG Value
  1245. );
  1246. /*++
  1247. Routine Description:
  1248. This routine sets the translation table base register 0 (TTBR0).
  1249. Arguments:
  1250. Value - Supplies the value to write.
  1251. Return Value:
  1252. None.
  1253. --*/
  1254. ULONG
  1255. ArGetTranslationTableBaseRegister1 (
  1256. VOID
  1257. );
  1258. /*++
  1259. Routine Description:
  1260. This routine gets the translation table base register 1 (TTBR1).
  1261. Arguments:
  1262. None.
  1263. Return Value:
  1264. Returns the contents of TTBR1.
  1265. --*/
  1266. VOID
  1267. ArSetTranslationTableBaseRegister1 (
  1268. ULONG Value
  1269. );
  1270. /*++
  1271. Routine Description:
  1272. This routine sets the translation table base register 1 (TTBR1).
  1273. Arguments:
  1274. Value - Supplies the value to write.
  1275. Return Value:
  1276. None.
  1277. --*/
  1278. ULONG
  1279. ArGetPrimaryRegionRemapRegister (
  1280. VOID
  1281. );
  1282. /*++
  1283. Routine Description:
  1284. This routine gets the Primary Region Remap Register (PRRR).
  1285. Arguments:
  1286. None.
  1287. Return Value:
  1288. Returns the contents of the register.
  1289. --*/
  1290. VOID
  1291. ArSetPrimaryRegionRemapRegister (
  1292. ULONG Value
  1293. );
  1294. /*++
  1295. Routine Description:
  1296. This routine sets the PRRR.
  1297. Arguments:
  1298. Value - Supplies the value to write.
  1299. Return Value:
  1300. None.
  1301. --*/
  1302. ULONG
  1303. ArGetNormalMemoryRemapRegister (
  1304. VOID
  1305. );
  1306. /*++
  1307. Routine Description:
  1308. This routine gets the Normal Memory Remap Register (NMRR).
  1309. Arguments:
  1310. None.
  1311. Return Value:
  1312. Returns the contents of the register.
  1313. --*/
  1314. VOID
  1315. ArSetNormalMemoryRemapRegister (
  1316. ULONG Value
  1317. );
  1318. /*++
  1319. Routine Description:
  1320. This routine sets the NMRR.
  1321. Arguments:
  1322. Value - Supplies the value to write.
  1323. Return Value:
  1324. None.
  1325. --*/
  1326. ULONG
  1327. ArGetPhysicalAddressRegister (
  1328. VOID
  1329. );
  1330. /*++
  1331. Routine Description:
  1332. This routine gets the Physical Address Register (PAR).
  1333. Arguments:
  1334. None.
  1335. Return Value:
  1336. Returns the contents of the register.
  1337. --*/
  1338. VOID
  1339. ArSetPhysicalAddressRegister (
  1340. ULONG Value
  1341. );
  1342. /*++
  1343. Routine Description:
  1344. This routine sets the Physical Address Register (PAR).
  1345. Arguments:
  1346. Value - Supplies the value to write.
  1347. Return Value:
  1348. None.
  1349. --*/
  1350. VOID
  1351. ArSetPrivilegedReadTranslateRegister (
  1352. ULONG Value
  1353. );
  1354. /*++
  1355. Routine Description:
  1356. This routine sets the Privileged Read address translation command register.
  1357. Arguments:
  1358. Value - Supplies the value to write.
  1359. Return Value:
  1360. None.
  1361. --*/
  1362. VOID
  1363. ArSetPrivilegedWriteTranslateRegister (
  1364. ULONG Value
  1365. );
  1366. /*++
  1367. Routine Description:
  1368. This routine sets the Privileged Write address translation command register.
  1369. Arguments:
  1370. Value - Supplies the value to write.
  1371. Return Value:
  1372. None.
  1373. --*/
  1374. VOID
  1375. ArSetUnprivilegedReadTranslateRegister (
  1376. ULONG Value
  1377. );
  1378. /*++
  1379. Routine Description:
  1380. This routine sets the Unrivileged Read address translation command register.
  1381. Arguments:
  1382. Value - Supplies the value to write.
  1383. Return Value:
  1384. None.
  1385. --*/
  1386. VOID
  1387. ArSetUnprivilegedWriteTranslateRegister (
  1388. ULONG Value
  1389. );
  1390. /*++
  1391. Routine Description:
  1392. This routine sets the Unprivileged Write address translation command
  1393. register.
  1394. Arguments:
  1395. Value - Supplies the value to write.
  1396. Return Value:
  1397. None.
  1398. --*/
  1399. ULONG
  1400. ArGetMultiprocessorIdRegister (
  1401. VOID
  1402. );
  1403. /*++
  1404. Routine Description:
  1405. This routine gets the Multiprocessor ID register (MPIDR).
  1406. Arguments:
  1407. None.
  1408. Return Value:
  1409. Returns the value of the MPIDR.
  1410. --*/
  1411. ULONG
  1412. ArTranslateVirtualToPhysical (
  1413. PVOID VirtualAddress
  1414. );
  1415. /*++
  1416. Routine Description:
  1417. This routine translates a virtual address to its corresponding physical
  1418. address by using the current translation tables.
  1419. Arguments:
  1420. VirtualAddress - Supplies the virtual address to translate.
  1421. Return Value:
  1422. Returns the physical address that the virtual address corresponds to
  1423. (with some bits at the bottom relating to the cache type).
  1424. --*/
  1425. VOID
  1426. ArSetThreadPointerUserReadOnly (
  1427. PVOID NewPointer
  1428. );
  1429. /*++
  1430. Routine Description:
  1431. This routine sets the TPIDRURO user-mode-read-only thread pointer register.
  1432. Arguments:
  1433. NewPointer - Supplies the value to write.
  1434. Return Value:
  1435. None.
  1436. --*/
  1437. ULONG
  1438. ArGetThreadPointerUser (
  1439. VOID
  1440. );
  1441. /*++
  1442. Routine Description:
  1443. This routine sets the TPIDRURW user-mode thread pointer register.
  1444. Arguments:
  1445. None.
  1446. Return Value:
  1447. Returns the current value of the TPIDRURW.
  1448. --*/
  1449. VOID
  1450. ArSwitchTtbr0 (
  1451. ULONG NewValue
  1452. );
  1453. /*++
  1454. Routine Description:
  1455. This routine performs the proper sequence for changing contexts in TTBR0,
  1456. including the necessary invalidates and barriers.
  1457. Arguments:
  1458. NewValue - Supplies the new value to write.
  1459. Return Value:
  1460. None.
  1461. --*/
  1462. ULONG
  1463. ArGetPerformanceControlRegister (
  1464. VOID
  1465. );
  1466. /*++
  1467. Routine Description:
  1468. This routine retrieves the PMCR (Performance Monitor Control Register).
  1469. Arguments:
  1470. None.
  1471. Return Value:
  1472. Returns the value of the PMCR.
  1473. --*/
  1474. VOID
  1475. ArSetPerformanceControlRegister (
  1476. ULONG Value
  1477. );
  1478. /*++
  1479. Routine Description:
  1480. This routine sets the PMCR (Performance Monitor Control Register).
  1481. Arguments:
  1482. Value - Supplies the value to set in the PMCR.
  1483. Return Value:
  1484. None.
  1485. --*/
  1486. VOID
  1487. ArClearPerformanceInterruptRegister (
  1488. ULONG Value
  1489. );
  1490. /*++
  1491. Routine Description:
  1492. This routine sets the PMINTENCLR (Performance Monitor Interrupt Clear)
  1493. register.
  1494. Arguments:
  1495. Value - Supplies the value to set in the PMINTENCLR.
  1496. Return Value:
  1497. None.
  1498. --*/
  1499. VOID
  1500. ArSetPerformanceUserEnableRegister (
  1501. ULONG Value
  1502. );
  1503. /*++
  1504. Routine Description:
  1505. This routine sets the PMUSERENR (Performance Monitor User Enable Register).
  1506. Arguments:
  1507. Value - Supplies the value to set in the PMUSERENR.
  1508. Return Value:
  1509. None.
  1510. --*/
  1511. ULONG
  1512. ArGetPerformanceCounterEnableRegister (
  1513. VOID
  1514. );
  1515. /*++
  1516. Routine Description:
  1517. This routine retrieves the PMCNTENSET (Performance Monitor Counter Enable
  1518. Set) register.
  1519. Arguments:
  1520. None.
  1521. Return Value:
  1522. Returns the value of the PMCNTENSET.
  1523. --*/
  1524. VOID
  1525. ArSetPerformanceCounterEnableRegister (
  1526. ULONG Value
  1527. );
  1528. /*++
  1529. Routine Description:
  1530. This routine sets the PMCNTENSET (Performance Monitor Counter Enable
  1531. Set) register.
  1532. Arguments:
  1533. Value - Supplies the value to set in the PMCNTENSET register.
  1534. Return Value:
  1535. None.
  1536. --*/
  1537. ULONG
  1538. ArGetCycleCountRegister (
  1539. VOID
  1540. );
  1541. /*++
  1542. Routine Description:
  1543. This routine retrieves the PMCCNTR (Performance Monitor Cycle Counter)
  1544. register.
  1545. Arguments:
  1546. None.
  1547. Return Value:
  1548. Returns the value of the PMCCNTR.
  1549. --*/
  1550. VOID
  1551. ArSetCycleCountRegister (
  1552. ULONG Value
  1553. );
  1554. /*++
  1555. Routine Description:
  1556. This routine sets the PMCCNTR (Performance Monitor Cycle Counter) register.
  1557. Arguments:
  1558. Value - Supplies the value to set in the PMCCNTR register.
  1559. Return Value:
  1560. None.
  1561. --*/
  1562. KSTATUS
  1563. ArGetNextPc (
  1564. PTRAP_FRAME TrapFrame,
  1565. PGET_NEXT_PC_READ_MEMORY_FUNCTION ReadMemoryFunction,
  1566. PBOOL IsFunctionReturning,
  1567. PVOID *NextPcValue
  1568. );
  1569. /*++
  1570. Routine Description:
  1571. This routine attempts to predict the next instruction to be executed. It
  1572. will decode the current instruction, check if the condition matches, and
  1573. attempt to follow any branches.
  1574. Arguments:
  1575. TrapFrame - Supplies a pointer to the current machine state.
  1576. ReadMemoryFunction - Supplies a pointer to a function this routine can
  1577. call when it needs to read target memory.
  1578. IsFunctionReturning - Supplies an optional pointer where a boolean will be
  1579. stored indicating if the current instruction is a return of some kind.
  1580. NextPcValue - Supplies a pointer of the next executing address.
  1581. Return Value:
  1582. Status code. This routine will attempt to make a guess at the next PC even
  1583. if the status code is failing, but chances it's right go way down if a
  1584. failing status is returned.
  1585. --*/
  1586. VOID
  1587. ArBackUpIfThenState (
  1588. PTRAP_FRAME TrapFrame
  1589. );
  1590. /*++
  1591. Routine Description:
  1592. This routine backs up the Thumb if-then state in the CPSR by one
  1593. instruction, assuming that the previous instruction tested positively for
  1594. being executed.
  1595. Arguments:
  1596. TrapFrame - Supplies a pointer to the current machine state.
  1597. Return Value:
  1598. Status code. This routine will attempt to make a guess at the next PC even
  1599. if the status code is failing, but chances it's right go way down if a
  1600. failing status is returned.
  1601. --*/
  1602. ULONG
  1603. ArGetMainIdRegister (
  1604. VOID
  1605. );
  1606. /*++
  1607. Routine Description:
  1608. This routine gets the Main ID Register (MIDR).
  1609. Arguments:
  1610. None.
  1611. Return Value:
  1612. Returns the contents of the register.
  1613. --*/
  1614. ULONG
  1615. ArGetCoprocessorAccessRegister (
  1616. VOID
  1617. );
  1618. /*++
  1619. Routine Description:
  1620. This routine gets the Coprocessor Access Control Register (CPACR).
  1621. Arguments:
  1622. None.
  1623. Return Value:
  1624. Returns the contents of the register.
  1625. --*/
  1626. VOID
  1627. ArSetCoprocessorAccessRegister (
  1628. ULONG Value
  1629. );
  1630. /*++
  1631. Routine Description:
  1632. This routine sets the Coprocessor Access Control Register (CPACR).
  1633. Arguments:
  1634. Value - Supplies the value to write.
  1635. Return Value:
  1636. None.
  1637. --*/
  1638. ULONG
  1639. ArGetFloatingPointIdRegister (
  1640. VOID
  1641. );
  1642. /*++
  1643. Routine Description:
  1644. This routine gets the Floating Point unit ID register (FPSID).
  1645. Arguments:
  1646. None.
  1647. Return Value:
  1648. Returns the contents of the register.
  1649. --*/
  1650. ULONG
  1651. ArGetMvfr0Register (
  1652. VOID
  1653. );
  1654. /*++
  1655. Routine Description:
  1656. This routine gets the floating point extensions identification register
  1657. (MVFR0).
  1658. Arguments:
  1659. None.
  1660. Return Value:
  1661. Returns the contents of the register.
  1662. --*/
  1663. ULONG
  1664. ArGetVfpExceptionRegister (
  1665. VOID
  1666. );
  1667. /*++
  1668. Routine Description:
  1669. This routine gets the floating point exception control register (FPEXC).
  1670. Arguments:
  1671. None.
  1672. Return Value:
  1673. Returns the contents of the register.
  1674. --*/
  1675. VOID
  1676. ArSetVfpExceptionRegister (
  1677. ULONG Value
  1678. );
  1679. /*++
  1680. Routine Description:
  1681. This routine sets the floating point exception control register (FPEXC).
  1682. Arguments:
  1683. Value - Supplies the new value to set.
  1684. Return Value:
  1685. None.
  1686. --*/
  1687. ULONG
  1688. ArGetVfpInstructionRegister (
  1689. VOID
  1690. );
  1691. /*++
  1692. Routine Description:
  1693. This routine gets the floating point instruction register (FPINST).
  1694. Arguments:
  1695. None.
  1696. Return Value:
  1697. Returns the contents of the register.
  1698. --*/
  1699. ULONG
  1700. ArGetFpscr (
  1701. VOID
  1702. );
  1703. /*++
  1704. Routine Description:
  1705. This routine gets the floating point status and control register (FPSCR).
  1706. Arguments:
  1707. None.
  1708. Return Value:
  1709. Returns the contents of the register.
  1710. --*/
  1711. VOID
  1712. ArSaveVfp (
  1713. PFPU_CONTEXT Context,
  1714. BOOL SimdSupport
  1715. );
  1716. /*++
  1717. Routine Description:
  1718. This routine saves the Vector Floating Point unit state.
  1719. Arguments:
  1720. Context - Supplies a pointer where the context will be saved.
  1721. SimdSupport - Supplies a boolean indicating whether the VFP unit contains
  1722. 32 64-bit registers (TRUE) or 16 64-bit registers (FALSE).
  1723. Return Value:
  1724. None.
  1725. --*/
  1726. VOID
  1727. ArRestoreVfp (
  1728. PFPU_CONTEXT Context,
  1729. BOOL SimdSupport
  1730. );
  1731. /*++
  1732. Routine Description:
  1733. This routine restores the Vector Floating Point unit state into the
  1734. hardware.
  1735. Arguments:
  1736. Context - Supplies a pointer to the context to restore.
  1737. SimdSupport - Supplies a boolean indicating whether the VFP unit contains
  1738. 32 64-bit registers (TRUE) or 16 64-bit registers (FALSE).
  1739. Return Value:
  1740. None.
  1741. --*/
  1742. VOID
  1743. ArInitializeVfpSupport (
  1744. VOID
  1745. );
  1746. /*++
  1747. Routine Description:
  1748. This routine initializes processor support for the VFP unit, and sets the
  1749. related feature bits in the user shared data.
  1750. Arguments:
  1751. None.
  1752. Return Value:
  1753. None.
  1754. --*/
  1755. VOID
  1756. ArSaveFpuState (
  1757. PFPU_CONTEXT Buffer
  1758. );
  1759. /*++
  1760. Routine Description:
  1761. This routine saves the current FPU context into the given buffer.
  1762. Arguments:
  1763. Buffer - Supplies a pointer to the buffer where the information will be
  1764. saved to.
  1765. Return Value:
  1766. None.
  1767. --*/
  1768. BOOL
  1769. ArCheckForVfpException (
  1770. PTRAP_FRAME TrapFrame,
  1771. ULONG Instruction
  1772. );
  1773. /*++
  1774. Routine Description:
  1775. This routine checks for VFP or NEON undefined instruction faults, and
  1776. potentially handles them if found.
  1777. Arguments:
  1778. TrapFrame - Supplies a pointer to the state immediately before the
  1779. exception.
  1780. Instruction - Supplies the instruction that caused the abort.
  1781. Return Value:
  1782. None.
  1783. --*/
  1784. VOID
  1785. ArDisableFpu (
  1786. VOID
  1787. );
  1788. /*++
  1789. Routine Description:
  1790. This routine disallows access to the FPU on the current processor, causing
  1791. all future accesses to generate exceptions.
  1792. Arguments:
  1793. None.
  1794. Return Value:
  1795. None.
  1796. --*/