arm.inc 12 KB

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  1. /*++
  2. Copyright (c) 2012 Minoca Corp.
  3. This file is licensed under the terms of the GNU General Public License
  4. version 3. Alternative licensing terms are available. Contact
  5. info@minocacorp.com for details. See the LICENSE file at the root of this
  6. project for complete licensing information.
  7. Module Name:
  8. arm.inc
  9. Abstract:
  10. This module contains common definitions for the ARM architecture.
  11. Author:
  12. Evan Green 11-Aug-2012
  13. Environment:
  14. Kernel mode
  15. --*/
  16. //
  17. // --------------------------------------------------------------- Definitions
  18. //
  19. //
  20. // Set this to 1 to enable Thumb-2 instructions.
  21. //
  22. #ifdef __thumb__
  23. #define THUMB 1
  24. #else
  25. #define THUMB 0
  26. #endif
  27. #define NULL 0x0
  28. //
  29. // Processor flags
  30. //
  31. //
  32. // Program Status Register flags.
  33. //
  34. #define PSR_FLAG_NEGATIVE 0x80000000
  35. #define PSR_FLAG_ZERO 0x40000000
  36. #define PSR_FLAG_CARRY 0x20000000
  37. #define PSR_FLAG_OVERFLOW 0x10000000
  38. #define PSR_FLAG_SATURATION 0x08000000
  39. #define PSR_FLAG_JAZELLE 0x01000000
  40. #define PSR_FLAG_THUMB 0x00000020
  41. #define PSR_FLAG_IRQ 0x00000080
  42. #define PSR_FLAG_FIQ 0x00000040
  43. //
  44. // Processor modes
  45. //
  46. #define ARM_MODE_USER 0x00000010
  47. #define ARM_MODE_FIQ 0x00000011
  48. #define ARM_MODE_IRQ 0x00000012
  49. #define ARM_MODE_SVC 0x00000013
  50. #define ARM_MODE_MON 0x00000016
  51. #define ARM_MODE_ABORT 0x00000017
  52. #define ARM_MODE_HYP 0x0000001A
  53. #define ARM_MODE_UNDEF 0x0000001B
  54. #define ARM_MODE_SYSTEM 0x0000001F
  55. #define ARM_MODE_MASK 0x0000001F
  56. //
  57. // Basic constants.
  58. //
  59. #define FALSE 0
  60. #define TRUE 1
  61. //
  62. // Kernel constants.
  63. //
  64. #define EXCEPTION_BREAK 0x03
  65. #define EXCEPTION_SINGLE_STEP 0x04
  66. #define EXCEPTION_ACCESS_VIOLATION 0x05
  67. #define EXCEPTION_ASSERTION_FAILURE 0x07
  68. //
  69. // Translation table base register address mask.
  70. //
  71. // Bit definitions are tricky for this register because they change based on
  72. // whether or not the Multiprocessing Extensions are supported on the CPU.
  73. //
  74. #define TTBR_ADDRESS_MASK 0x00003FFF
  75. //
  76. // MMU Control bits (SCTLR, CP15, register 1).
  77. //
  78. #define MMU_ENABLED 0x00000001
  79. #define MMU_ALIGNMENT_FAULT_ENABLED 0x00000002
  80. #define MMU_DCACHE_ENABLED 0x00000004
  81. #define MMU_WRITE_BUFFER_ENABLED 0x00000008
  82. #define MMU_ENDIANNESS 0x00000080
  83. #define MMU_SYSTEM_PROTECTION 0x00000100
  84. #define MMU_ROM_PROTECTION 0x00000200
  85. #define MMU_BRANCH_PREDICTION_ENABLED 0x00000800
  86. #define MMU_ICACHE_ENABLED 0x00001000
  87. #define MMU_HIGH_EXCEPTION_VECTORS 0x00002000
  88. #define MMU_PREDICTABLE_REPLACEMENT 0x00004000
  89. #define MMU_DISABLE_THUMB_DEPRECATED 0x00008000
  90. #define MMU_FAST_INTERRUPTS 0x00200000
  91. #define MMU_UNALIGNED_ACCESS_ENABLED 0x00400000
  92. #define MMU_VMSA6_ENABLED 0x00800000
  93. #define MMU_VECTORED_INTERRUPTS_ENABLED 0x01000000
  94. #define MMU_EXCEPTION_ENDIAN 0x02000000
  95. #define MMU_THUMB_EXCEPTIONS 0x40000000
  96. #define MMU_CONTROL_DEFAULT_VALUE 0x00C0180D
  97. //
  98. // ARMv6 auxiliary control register bits (ACTLR).
  99. //
  100. #define ARMV6_AUX_16K_CACHE_SIZE 0x00000040
  101. //
  102. // Cortex A17 auxiliary control register bits (ACTLR).
  103. //
  104. #define CORTEX_A17_AUX_SMP_ENABLE 0x00000040
  105. //
  106. // Nonsecure Access Control Register bits (CP15, register 1, opcode2 2).
  107. //
  108. #define MMU_TLB_LOCKING_ENABLE 0x00020000
  109. //
  110. // Secure Configuration Register bits (SCR).
  111. //
  112. #define SCR_NON_SECURE 0x00000001
  113. #define SCR_MONITOR_MODE_IRQ 0x00000002
  114. #define SCR_MONITOR_MODE_FIQ 0x00000004
  115. #define SCR_MONITOR_MODE_EXTERNAL_ABORT 0x00000008
  116. #define SCR_CPSR_FIQ_WRITABLE 0x00000010
  117. #define SCR_CPSR_ASYNC_ABORT_WRITABLE 0x00000020
  118. #define SCR_EARLY_TERMINATION_DISABLED 0x00000040
  119. #define SCR_NON_SECURE_SMC_DISABLED 0x00000080
  120. #define SCR_NON_SECURE_HVC_ENABLED 0x00000100
  121. #define SCR_NON_SECURE_INSTRUCTION_FETCH_DISABLED 0x00000200
  122. //
  123. // Definition for the structure on the exception stacks.
  124. //
  125. #define EXCEPTION_STACK_R0 0
  126. #define EXCEPTION_STACK_CPSR 4
  127. //
  128. // Define the offsets for members of the TRAP_FRAME structure.
  129. //
  130. #define TRAP_SVCSP 0
  131. #define TRAP_USERSP 4
  132. #define TRAP_USERLR 8
  133. #define TRAP_R0 12
  134. #define TRAP_EXCEPTION_CPSR 16
  135. #define TRAP_R1 20
  136. #define TRAP_R2 24
  137. #define TRAP_R3 28
  138. #define TRAP_R4 32
  139. #define TRAP_R5 36
  140. #define TRAP_R6 40
  141. #define TRAP_R7 44
  142. #define TRAP_R8 48
  143. #define TRAP_R9 52
  144. #define TRAP_R10 56
  145. #define TRAP_R11 60
  146. #define TRAP_R12 64
  147. #define TRAP_SVCLR 68
  148. #define TRAP_PC 72
  149. #define TRAP_CPSR 76
  150. #define TRAP_FRAME_SIZE 80
  151. //
  152. // Define the size of the common SIGNAL_CONTEXT structure.
  153. //
  154. #define SIGNAL_CONTEXT_SIZE 32
  155. //
  156. // Define the size of the PROCESSOR_CONTEXT structure.
  157. //
  158. #define PROCESSOR_CONTEXT_SIZE 192
  159. //
  160. // Define the instructions for DSB/ISB, which are different in ARMv6 vs ARMv7.
  161. //
  162. #if __ARM_ARCH == 6
  163. #define DMB mcr p15, 0, %r0, %cr7, %cr10, 5
  164. #define DSB mcr p15, 0, %r0, %cr7, %cr10, 4
  165. #define ISB mcr p15, 0, %r0, %cr7, %cr5, 4
  166. #define BPIALL
  167. #elif __ARM_ARCH == 7
  168. #define DMB dmb
  169. #define DSB dsb
  170. #define ISB isb
  171. #define BPIALL mcr p15, 0, %r0, %cr7, %cr5, 6
  172. #else
  173. #error Unsupported ARM architecture version
  174. #endif
  175. //
  176. // Define the system call number for resuming after a signal and
  177. // forking a process, operations which happen from assembly.
  178. //
  179. #define SystemCallRestoreContext 1
  180. #define SystemCallForkProcess 2
  181. #define SIGNAL_PARAMETERS_SIZE 24
  182. #define SIGNAL_CONTEXT_SIZE 32
  183. //
  184. // -------------------------------------------------------------------- Macros
  185. //
  186. //
  187. // Define .cfi directives, macroed so they can be excised if unneeded.
  188. //
  189. #define CFI_DEF_CFA(_Register, _Offset) .cfi_def_cfa _Register, _Offset
  190. #define CFI_DEF_CFA_OFFSET(_Offset) .cfi_def_cfa_offset _Offset
  191. #define CFI_ADJUST_CFA_OFFSET(_Amount) .cfi_adjust_cfa_offset _Amount
  192. #define CFI_OFFSET(_Register, _Offset) .cfi_offset _Register, _Offset
  193. #define CFI_UNDEFINED(_Register) .cfi_undefined _Register
  194. #define CFI_SAME_VALUE(_Register) .cfi_same_value _Register
  195. //
  196. // This macro emits a thumb if-then instruction, if compiling in Thumb mode.
  197. //
  198. #define IT(_Condition) \
  199. .if THUMB ; \
  200. it _Condition ; \
  201. .endif
  202. #define ITE(_Condition) \
  203. .if THUMB ; \
  204. ite _Condition ; \
  205. .endif
  206. #define ITTE(_Condition) \
  207. .if THUMB ; \
  208. itte _Condition ; \
  209. .endif
  210. #define ITTTE(_Condition) \
  211. .if THUMB ; \
  212. ittte _Condition ; \
  213. .endif
  214. //
  215. // This macro goes at the top of an assembly file.
  216. // .text specifies that this code belongs in the executable section.
  217. // .thumb specifies this is Thumb code (not ARM code).
  218. // .syntax unified turns on Unified Assembly Language which is required to
  219. // enable Thumb-2 features.
  220. // .align 4 ensures functions are emitted on proper boundaries.
  221. //
  222. .macro ASSEMBLY_FILE_HEADER
  223. .text
  224. .syntax unified
  225. .cfi_sections .debug_frame
  226. .if THUMB
  227. .thumb
  228. .else
  229. .arm
  230. .endif
  231. #if __ARM_ARCH == 6
  232. .cpu arm1176jz-s
  233. #elif __ARM_ARCH == 7
  234. .arch armv7-a
  235. .arch_extension sec
  236. #else
  237. #error Unsupported ARM architecture version
  238. #endif
  239. .endm
  240. //
  241. // This macro defines a function, callable from C code within the current
  242. // module.
  243. //
  244. .macro FUNCTION FunctionName
  245. .hidden \FunctionName
  246. EXPORTED_FUNCTION \FunctionName
  247. .endm
  248. //
  249. // This macro defines a function, callable from C code in any module, but
  250. // always called locally in the current module.
  251. //
  252. .macro PROTECTED_FUNCTION FunctionName
  253. .protected \FunctionName
  254. EXPORTED_FUNCTION \FunctionName
  255. .endm
  256. //
  257. // This macro defines a function, callable from C code in any module, and
  258. // capable of being overridden by other modules.
  259. //
  260. .macro EXPORTED_FUNCTION FunctionName
  261. .func \FunctionName
  262. .type \FunctionName, %function
  263. .if THUMB
  264. .thumb_func
  265. .endif
  266. .globl \FunctionName
  267. .cfi_startproc
  268. .cfi_def_cfa r13, 0
  269. \FunctionName:
  270. .endm
  271. //
  272. // This macro defines the end of a function.
  273. //
  274. .macro END_FUNCTION FunctionName
  275. .ltorg
  276. .size \FunctionName, .-\FunctionName
  277. .cfi_endproc
  278. .endfunc
  279. .endm
  280. //
  281. // Define a macro used to generate the debugger break instruction.
  282. //
  283. .macro DEBUGGER_BREAK
  284. .if THUMB
  285. .hword 0xDE20
  286. .else
  287. .word 0xE7F000F3
  288. .endif
  289. .endm
  290. //
  291. // Define a macro used to generate the debug service instruction.
  292. //
  293. .macro DEBUG_SERVICE
  294. .if THUMB
  295. .hword 0xDE24
  296. .else
  297. .word 0xE7F000F4
  298. .endif
  299. .endm
  300. //
  301. // This macro can be run immediately after an exception or interrupt. It
  302. // switches back to SVC mode and creates a trap frame. This uses several
  303. // instructions from ARMv6T2, including srs, cpsid #mode, and clrex.
  304. //
  305. .macro ARM_ENTER_INTERRUPT
  306. srsdb %sp!, #ARM_MODE_SVC @ Push lr and spsr to SVC.
  307. mrs %lr, cpsr @ Get exception mode CPSR.
  308. stmdb %sp, {%r0, %lr} @ Push R0 and exception CPSR.
  309. sub %r0, %sp, #8 @ Remember exception stack.
  310. cpsid i, #ARM_MODE_SVC @ Switch to SVC mode.
  311. stmdb %sp!, {%r1-%r12, %lr} @ Push general registers.
  312. ldmia %r0, {%r1, %r2} @ Get R0 and exception CPSR.
  313. stmdb %sp!, {%r1, %r2} @ Save onto trap frame.
  314. mov %r0, %sp @ Get SVC stack.
  315. sub %sp, %sp, #12 @ Allocate space.
  316. cpsid i, #ARM_MODE_SYSTEM @ Move to system mode.
  317. str %lr, [%r0, #-4] @ Save usermode SP.
  318. str %sp, [%r0, #-8] @ Save usermode LR.
  319. cpsid i, #ARM_MODE_SVC @ Switch back to SVC mode.
  320. str %sp, [%sp] @ Save SVC stack pointer.
  321. clrex @ Clear exclusive monitors.
  322. CFI_OFFSET(r0, TRAP_R0)
  323. CFI_OFFSET(r1, TRAP_R1)
  324. CFI_OFFSET(r2, TRAP_R2)
  325. CFI_OFFSET(r3, TRAP_R3)
  326. CFI_OFFSET(r4, TRAP_R4)
  327. CFI_OFFSET(r5, TRAP_R5)
  328. CFI_OFFSET(r6, TRAP_R6)
  329. CFI_OFFSET(r7, TRAP_R7)
  330. CFI_OFFSET(r8, TRAP_R8)
  331. CFI_OFFSET(r9, TRAP_R9)
  332. CFI_OFFSET(r10, TRAP_R10)
  333. CFI_OFFSET(r11, TRAP_R11)
  334. CFI_OFFSET(r12, TRAP_R12)
  335. CFI_OFFSET(sp, TRAP_SVCSP) @ Assume it came from SVC mode.
  336. CFI_OFFSET(lr, TRAP_SVCLR)
  337. CFI_OFFSET(pc, TRAP_PC)
  338. .endm
  339. //
  340. // This macro can be used for an interrupt or exception that was entered with
  341. // ARM_INTERRUPT_ENTER. It restores the state in the trap frame and returns
  342. // from the exception.
  343. //
  344. .macro ARM_EXIT_INTERRUPT
  345. //
  346. // Restore the stack pointer. The rest of the context better be at the new
  347. // stack location. Then restore the user mode sp and lr.
  348. //
  349. ldr %sp, [%sp] @ Restore stack pointer.
  350. add %sp, %sp, #4 @ Pop stack pointer.
  351. //
  352. // Restore the user mode stack and link registers.
  353. //
  354. mov %r0, %sp @ Get SVC stack pointer.
  355. cpsid i, #ARM_MODE_SYSTEM @ Switch to system mode.
  356. ldr %sp, [%r0] @ Restore usermode SP.
  357. ldr %lr, [%r0, #4] @ Resotre usermode LR.
  358. cpsid i, #ARM_MODE_SVC @ Switch back to svc mode.
  359. ldr %r0, [%sp, #8] @ Restore R0.
  360. add %sp, %sp, #16 @ Pop up to R1.
  361. ldmia %sp!, {%r1-%r12, %lr} @ Restore general registers.
  362. CFI_SAME_VALUE(r0)
  363. CFI_SAME_VALUE(r1)
  364. CFI_SAME_VALUE(r2)
  365. CFI_SAME_VALUE(r3)
  366. CFI_SAME_VALUE(r4)
  367. CFI_SAME_VALUE(r5)
  368. CFI_SAME_VALUE(r6)
  369. CFI_SAME_VALUE(r7)
  370. CFI_SAME_VALUE(r8)
  371. CFI_SAME_VALUE(r9)
  372. CFI_SAME_VALUE(r10)
  373. CFI_SAME_VALUE(r11)
  374. CFI_SAME_VALUE(r12)
  375. CFI_OFFSET(sp, 8)
  376. CFI_OFFSET(lr, 0)
  377. rfeia %sp! @ Restore PC and CPSR.
  378. .endm