ata.h 18 KB

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  1. /*++
  2. Copyright (c) 2014 Minoca Corp. All Rights Reserved
  3. Module Name:
  4. ata.h
  5. Abstract:
  6. This header contains definitions for the AT Attachment (ATA) driver.
  7. Author:
  8. Evan Green 4-Jun-2014
  9. --*/
  10. //
  11. // ------------------------------------------------------------------- Includes
  12. //
  13. //
  14. // ---------------------------------------------------------------- Definitions
  15. //
  16. #define ATA_ALLOCATION_TAG 0x21617441 // '!atA'
  17. #define ATA_CABLE_COUNT 2
  18. #define ATA_CHILD_COUNT (2 * ATA_CABLE_COUNT)
  19. #define ATA_SECTOR_SIZE 512
  20. #define ATA_MAX_LBA28_SECTOR_COUNT 0x100
  21. #define ATA_MAX_LBA48_SECTOR_COUNT 0x10000
  22. //
  23. // Define the timeout in seconds before an ATA command expires.
  24. //
  25. #define ATA_TIMEOUT 60
  26. //
  27. // Define the timeout in microseconds before a device selection fails.
  28. //
  29. #define ATA_SELECT_TIMEOUT (60 * MICROSECONDS_PER_MILLISECOND)
  30. //
  31. // Define the amount of time in microseconds to wait for the selected device to
  32. // set the status appropriately.
  33. //
  34. #define ATA_SELECT_STALL MICROSECONDS_PER_MILLISECOND
  35. //
  36. // Define the known locations of the ATA controller if the PCI BARs did not
  37. // seem to specify them.
  38. //
  39. #define ATA_LEGACY_PRIMARY_IO_BASE 0x1F0
  40. #define ATA_LEGACY_PRIMARY_CONTROL_BASE 0x3F6
  41. #define ATA_LEGACY_SECONDARY_IO_BASE 0x170
  42. #define ATA_LEGACY_SECONDARY_CONTROL_BASE 0x376
  43. #define ATA_LEGACY_IO_SIZE 8
  44. #define ATA_LEGACY_CONTROL_SIZE 4
  45. //
  46. // Define the legacy interrupts assigned to the disk controller.
  47. //
  48. #define ATA_LEGACY_PRIMARY_INTERRUPT 14
  49. #define ATA_LEGACY_SECONDARY_INTERRUPT 15
  50. #define ATA_LEGACY_INTERRUPT_CHARACTERISTICS INTERRUPT_LINE_EDGE_TRIGGERED
  51. #define ATA_LEGACY_VECTOR_CHARACTERISTICS INTERRUPT_VECTOR_EDGE_TRIGGERED
  52. //
  53. // Define values that come out of the LBA1 and LBA2 registers when ATAPI or
  54. // SATA devices are interrogated using an ATA IDENTIFY command.
  55. //
  56. #define ATA_PATAPI_LBA1 0x14
  57. #define ATA_PATAPI_LBA2 0xEB
  58. #define ATA_SATAPI_LBA1 0x69
  59. #define ATA_SATAPI_LBA2 0x96
  60. #define ATA_SATA_LBA1 0x3C
  61. #define ATA_SATA_LBA2 0xC3
  62. //
  63. // Define the maximum LBA for the LBA28 command set.
  64. //
  65. #define ATA_MAX_LBA28 0x0FFFFFFFULL
  66. //
  67. // Define the total size of the PRDT for all four disks.
  68. //
  69. #define ATA_PRDT_TOTAL_SIZE 0x1000
  70. #define ATA_PRDT_DISK_SIZE (ATA_PRDT_TOTAL_SIZE / ATA_CABLE_COUNT)
  71. //
  72. // Define the boundary that DMA PRDT entries must not cross.
  73. //
  74. #define ATA_DMA_BOUNDARY 0x10000
  75. //
  76. // Define the flag set in the PRDT entry for the last descriptor.
  77. //
  78. #define ATA_DMA_LAST_DESCRIPTOR 0x8000
  79. //
  80. // Define conversions between the ATA register enum and the actual base
  81. // register segments.
  82. //
  83. #define ATA_HIGH_ADDRESSING_OFFSET (AtaRegisterSectorCountHigh - 2)
  84. #define ATA_HIGH_REGISTER_COUNT 4
  85. #define ATA_CONTROL_REGISTER_OFFSET \
  86. (ATA_HIGH_ADDRESSING_OFFSET + ATA_HIGH_ADDRESSING_OFFSET)
  87. #define ATA_BUS_MASTER_REGISTER_OFFSET AtaRegisterBusMasterCommand
  88. #define ATA_BUS_MASTER_TABLE_REGISTER 0x4
  89. //
  90. // ATA Status register definitions.
  91. //
  92. #define ATA_STATUS_ERROR 0x01
  93. #define ATA_STATUS_INDEX 0x02
  94. #define ATA_STATUS_CORRECTED_ERROR 0x04
  95. #define ATA_STATUS_DATA_REQUEST 0x08
  96. #define ATA_STATUS_SEEK_COMPLETE 0x10
  97. #define ATA_STATUS_FAULT 0x20
  98. #define ATA_STATUS_DRIVE_READY 0x40
  99. #define ATA_STATUS_BUSY 0x80
  100. #define ATA_STATUS_BUSY_MASK (ATA_STATUS_BUSY | ATA_STATUS_DATA_REQUEST)
  101. #define ATA_STATUS_ERROR_MASK (ATA_STATUS_ERROR | ATA_STATUS_FAULT)
  102. //
  103. // Define ATA control register bits.
  104. //
  105. #define ATA_CONTROL_HIGH_ORDER 0x80
  106. #define ATA_CONTROL_SOFTWARE_RESET 0x04
  107. #define ATA_CONTROL_INTERRUPT_DISABLE 0x02
  108. //
  109. // Define ATA drive select register bits.
  110. //
  111. #define ATA_DRIVE_SELECT_LBA 0x40
  112. #define ATA_DRIVE_SELECT_MASTER 0xA0
  113. #define ATA_DRIVE_SELECT_SLAVE 0xB0
  114. //
  115. // IDE Bus Master Status Register definitions.
  116. //
  117. //
  118. // Set if the drive is active.
  119. //
  120. #define IDE_STATUS_ACTIVE 0x01
  121. //
  122. // Set if the last operation had an error.
  123. //
  124. #define IDE_STATUS_ERROR 0x02
  125. //
  126. // Set if the INTRQ signal is asserted.
  127. //
  128. #define IDE_STATUS_INTERRUPT 0x04
  129. //
  130. // Set if drive 0 can do DMA.
  131. //
  132. #define IDE_STATUS_DRIVE0_DMA 0x20
  133. //
  134. // Set if drive 1 can do DMA.
  135. //
  136. #define IDE_STATUS_DRIVE1_DMA 0x40
  137. //
  138. // Set if only simplex operations are supported.
  139. //
  140. #define IDE_STATUS_SIMPLEX_ONLY 0x80
  141. //
  142. // Define the IDE programming interface register offset and bits.
  143. //
  144. #define IDE_INTERFACE_OFFSET 8
  145. #define IDE_INTERFACE_SIZE sizeof(USHORT)
  146. #define IDE_INTERFACE_PRIMARY_NATIVE_SUPPORTED 0x0800
  147. #define IDE_INTERFACE_PRIMARY_NATIVE_ENABLED 0x0400
  148. #define IDE_INTERFACE_SECONDARY_NATIVE_SUPPORTED 0x0200
  149. #define IDE_INTERFACE_SECONDARY_NATIVE_ENABLED 0x0100
  150. //
  151. // Define the bus master command bits.
  152. //
  153. #define ATA_BUS_MASTER_COMMAND_DMA_ENABLE 0x01
  154. #define ATA_BUS_MASTER_COMMAND_DMA_READ 0x08
  155. //
  156. // Define ATA supported command set bits.
  157. //
  158. #define ATA_SUPPORTED_COMMAND_LBA48 (1 << 26)
  159. //
  160. // ------------------------------------------------------ Data Type Definitions
  161. //
  162. typedef enum _ATA_CONTEXT_TYPE {
  163. AtaContextInvalid,
  164. AtaControllerContext,
  165. AtaChildContext
  166. } ATA_CONTEXT_TYPE, *PATA_CONTEXT_TYPE;
  167. typedef struct _ATA_CONTROLLER ATA_CONTROLLER, *PATA_CONTROLLER;
  168. typedef struct _ATA_CHILD ATA_CHILD, *PATA_CHILD;
  169. //
  170. // Define the ATA registers. Values >= 7 go the control base.
  171. //
  172. typedef enum _ATA_REGISTER {
  173. AtaRegisterData = 0x0,
  174. AtaRegisterError = 0x1,
  175. AtaRegisterFeatures = 0x1,
  176. AtaRegisterSectorCountLow = 0x2,
  177. AtaRegisterLba0 = 0x3,
  178. AtaRegisterLba1 = 0x4,
  179. AtaRegisterLba2 = 0x5,
  180. AtaRegisterDeviceSelect = 0x6,
  181. AtaRegisterCommand = 0x7,
  182. AtaRegisterStatus = 0x7,
  183. AtaRegisterSectorCountHigh = 0x8,
  184. AtaRegisterLba3 = 0x9,
  185. AtaRegisterLba4 = 0xA,
  186. AtaRegisterLba5 = 0xB,
  187. AtaRegisterControl = 0xC,
  188. AtaRegisterAlternateStatus = 0xC,
  189. AtaRegisterDeviceAddress = 0xD,
  190. AtaRegisterBusMasterCommand = 0xE,
  191. AtaRegisterBusMasterStatus = 0x10,
  192. AtaRegisterBusMasterTableAddress = 0x12,
  193. } ATA_REGISTER, *PATA_REGISTER;
  194. typedef enum _ATA_COMMAND {
  195. AtaCommandReadPio28 = 0x20,
  196. AtaCommandReadPio48 = 0x24,
  197. AtaCommandReadDma48 = 0x25,
  198. AtaCommandWritePio28 = 0x30,
  199. AtaCommandWritePio48 = 0x34,
  200. AtaCommandWriteDma48 = 0x35,
  201. AtaCommandPacket = 0xA0,
  202. AtaCommandIdentifyPacket = 0xA1,
  203. AtaCommandReadDma28 = 0xC8,
  204. AtaCommandWriteDma28 = 0xCA,
  205. AtaCommandCacheFlush28 = 0xE7,
  206. AtaCommandCacheFlush48 = 0xEA,
  207. AtaCommandIdentify = 0xEC,
  208. } ATA_COMMAND, *PATA_COMMAND;
  209. /*++
  210. Structure Description:
  211. This structure defines the Physical Region Descriptor Table format, which
  212. tells the ATA bus mastering controller where the memory is to DMA to.
  213. Members:
  214. PhysicalAddress - Stores the physical address to DMA to. This buffer
  215. cannot cross a 64k boundary.
  216. Size - Stores the size of the region in bytes. 0 is 64k.
  217. Flags - Stores flags, which should all be zero except the most significant
  218. bit, which indicates that this is the last entry in the PRDT.
  219. --*/
  220. typedef struct _ATA_PRDT {
  221. ULONG PhysicalAddress;
  222. USHORT Size;
  223. USHORT Flags;
  224. } PACKED ATA_PRDT, *PATA_PRDT;
  225. /*++
  226. Structure Description:
  227. This structure defines register bases for one ATA channel.
  228. Members:
  229. IoBase - Supplies the base I/O port of the I/O registers used for issuing
  230. ATA commands.
  231. ControlBase - Supplies the base I/O port of the control registers.
  232. BusMasterBase - Supplies the base I/O port of the bus master registers.
  233. InterruptDisable - Stores the bit to OR in to the control mask to indicate
  234. if interrupts are disabled or not.
  235. SelectedDevice - Stores the currently selected device.
  236. Lock - Stores a pointer to the lock used to synchronize this channel.
  237. Irp - Stores a pointer to the I/O IRP actively running on the channel.
  238. IoSize - Stores the size of this I/O operation.
  239. OwningChild - Stores a pointer to the child that has the channel locked.
  240. Prdt - Stores a pointer to the array of Physical Region Descriptor Table
  241. entries.
  242. PrdtPhysicalAddress - Stores the physical address of the PRDT.
  243. --*/
  244. typedef struct _ATA_CHANNEL {
  245. USHORT IoBase;
  246. USHORT ControlBase;
  247. USHORT BusMasterBase;
  248. UCHAR InterruptDisable;
  249. UCHAR SelectedDevice;
  250. PQUEUED_LOCK Lock;
  251. PIRP Irp;
  252. UINTN IoSize;
  253. PATA_CHILD OwningChild;
  254. PATA_PRDT Prdt;
  255. PHYSICAL_ADDRESS PrdtPhysicalAddress;
  256. } ATA_CHANNEL, *PATA_CHANNEL;
  257. /*++
  258. Structure Description:
  259. This structure defines state associated with an ATA child device (the
  260. bus driver's context for a disk itself).
  261. Members:
  262. Type - Stores the context type.
  263. Controller - Stores a pointer back up to the controller.
  264. Channel - Stores a pointer to the channel context.
  265. OsDevice - Stores a pointer to the OS device.
  266. Slave - Stores whether or not this device is the slave device or the master
  267. device.
  268. DmaSupported - Stores a boolean indicating whether or not this device
  269. supports DMA transfers.
  270. Lba48Supported - Stores a boolean indicating whether or not LBA48 is
  271. supported.
  272. TotalSectors - Stores the total number of sectors in the device.
  273. DiskInterface - Stores the disk interface.
  274. --*/
  275. struct _ATA_CHILD {
  276. ATA_CONTEXT_TYPE Type;
  277. PATA_CONTROLLER Controller;
  278. PATA_CHANNEL Channel;
  279. PDEVICE OsDevice;
  280. UCHAR Slave;
  281. BOOL DmaSupported;
  282. BOOL Lba48Supported;
  283. ULONGLONG TotalSectors;
  284. DISK_INTERFACE DiskInterface;
  285. };
  286. /*++
  287. Structure Description:
  288. This structure defines state associated with an ATA controller.
  289. Members:
  290. Type - Stores the context type.
  291. PrimaryInterruptLine - Stores the interrupt line that this controller's
  292. primary (or only) interrupt comes in on.
  293. SecondaryInterruptLine - Stores the secondary interrupt line for the
  294. controller.
  295. PrimaryInterruptVector - Stores the interrupt vector that this controller's
  296. primary interrupt comes in on.
  297. SecondaryInterruptVector - Stores the secondary interrupt vector.
  298. PrimaryInterruptFound - Stores a boolean indicating whether or not the
  299. primary interrupt line and interrupt vector fields are valid.
  300. SecondaryInterruptFound - Stores a boolean indicating whether or not
  301. secondary interrupt resources were found.
  302. SkipFirstInterrupt - Stores a boolean indicating whether or not to skip the
  303. first interrupt line resource found in favor of legacy ones later.
  304. PrimaryInterruptHandle - Stores a pointer to the handle received when the
  305. primary interrupt was connected. If the device only has one interrupt,
  306. it will be this one.
  307. SecondaryInterruptHandle - Stores a pointer to the handle received when
  308. the secondary interrupt was connected. This is only used in
  309. "compatibility" mode.
  310. Handle - Stores a pointer to the interrupt handle.
  311. PrimaryLock - Stores a pointer to the lock serializing access to the primary
  312. registers.
  313. SecondaryLock - Stores a pointer to the lock serializing access to the
  314. secondary registers.
  315. DpcLock - Stores a spinlock used to serialize DPC execution.
  316. Channel - Stores the array (size two) of ATA channels.
  317. PciConfigInterface - Stores the interface to access PCI configuration space.
  318. PciConfigInterfaceAvailable - Stores a boolean indicating if the PCI
  319. config interface is actively available.
  320. RegisteredForPciConfigInterfaces - Stores a boolean indicating whether or
  321. not the driver has regsistered for PCI Configuration Space interface
  322. access.
  323. Interface - Stores the programming interface of the controller.
  324. PrdtIoBuffer - Stores a pointer to the I/O buffer containing the
  325. physical region descriptor table.
  326. PendingStatus - Stores the pending bus master status register bits. The
  327. secondary controller's bits are shifted left by 8.
  328. --*/
  329. struct _ATA_CONTROLLER {
  330. ATA_CONTEXT_TYPE Type;
  331. ULONGLONG PrimaryInterruptLine;
  332. ULONGLONG SecondaryInterruptLine;
  333. ULONGLONG PrimaryInterruptVector;
  334. ULONGLONG SecondaryInterruptVector;
  335. BOOL PrimaryInterruptFound;
  336. BOOL SecondaryInterruptFound;
  337. BOOL SkipFirstInterrupt;
  338. HANDLE PrimaryInterruptHandle;
  339. HANDLE SecondaryInterruptHandle;
  340. KSPIN_LOCK DpcLock;
  341. ATA_CHANNEL Channel[ATA_CABLE_COUNT];
  342. PDEVICE ChildDevices[ATA_CHILD_COUNT];
  343. ATA_CHILD ChildContexts[ATA_CHILD_COUNT];
  344. INTERFACE_PCI_CONFIG_ACCESS PciConfigInterface;
  345. BOOL PciConfigInterfaceAvailable;
  346. BOOL RegisteredForPciConfigInterfaces;
  347. USHORT Interface;
  348. PIO_BUFFER PrdtIoBuffer;
  349. volatile ULONG PendingStatusBits;
  350. };
  351. /*++
  352. Structure Description:
  353. This structure defines the result of an IDENTIFY DEVICE command sent to a
  354. drive.
  355. Members:
  356. Configuration - Stores configuration information about the device such as
  357. whether it's a removable device and whether it's an ATA device.
  358. SerialNumber - Stores a 20 byte ASCII string representing the device's
  359. serial number.
  360. FirmwareRevision - Stores an 8 byte ASCII string representing the device's
  361. firmware revision.
  362. ModelNumber - Stores a 40 byte ASCII string representing the device model.
  363. MaxMultipleSectorTransfer - Stores the maximum number of sectors that can
  364. be transferred per interrupt on READ/WRITE MULTIPLE commands.
  365. Capabilities - Stores device capability bits such as whether LBA is
  366. supported, IORDY is supporetd, DMA is supported, etc.
  367. ValidFields - Stores bits indicating whether the words in fields 64-70 and
  368. word 88 are valid.
  369. CurrentMaxSectorTransfer - Stores the current setting for the number of
  370. sectors that can be transferred per interrupts on a READ/WRITE MULTIPLE
  371. command.
  372. TotalSectors - Stores the total number of user addressable sectors. If the
  373. LBA48 command set is supported, use that value instead of this one.
  374. MultiwordDmaSettings - Stores which Multiword DMA modes are supported, and
  375. which mode is selected.
  376. PioModesSupported - Stores which Polled I/O modes are supported on this
  377. device.
  378. MinMultiwordTransferCycles - Stores the minimum Multiword DMA transfer
  379. cycle time in nanoseconds.
  380. RecommendedMultiwordTransferCycles - Stores the manufacturer's
  381. recommended Multiword DMA transfer cycle time in nanoseconds.
  382. MinPioTransferCyclesNoFlow - Stores the minimum PIO transfer cycle time
  383. without flow control, in nanoseconds.
  384. MinPioTransferCyclesWithFlow - Stores the minimum PIO transfer cycle time
  385. with IORDY flow control, in nanoseconds.
  386. QueueDepth - Stores the maximum queue depth minus one.
  387. MajorVersion - Stores the major version of the ATA/ATAPI protocol
  388. supported.
  389. MinorVersion - Stores the device minor version.
  390. CommandSetSupported - Stores the command/feature sets that are supported on
  391. this device.
  392. FeatureSetSupported - Stores the command/feature extensions that are
  393. supported on this device.
  394. CommandSetEnabled - Stores a bitmask showing which command/features sets
  395. are currently enabled.
  396. CommandSetDefault - Stores the default features enabled.
  397. UltraDmaSettings - Stores which Ultra DMA modes are supported and currently
  398. enabled on this device.
  399. SecurityEraseTime - Stores the time required for security erase unit
  400. completion.
  401. EnhancedSecurityEraseTime - Stores the time required for enhanced security
  402. erase completion.
  403. CurrentPowerManagementValue - Stores the current power managment value.
  404. PasswordRevisionCode - Stores the Master Password Revision Code.
  405. ResetResult - Stores various statistics about how the drives behaved during
  406. a hardware reset.
  407. AcousticManagement - Stores the recommended and current acoustic
  408. management value.
  409. TotalSectorsLba48 - Stores the one beyond the maximum valid block number if
  410. the LBA48 command set is supported.
  411. RemovableMediaStatus - Stores whether or not the removable media status
  412. notification feature set is supported.
  413. SecurityStatus - Stores the current security state of the drive.
  414. PowerMode1 - Stores whether or not the CFA power mode 1 is supported or
  415. required for some commands.
  416. MediaSerialNumber - Stores the current media serial number.
  417. Checksum - Stores the two's complement of the sum of all bytes in words
  418. 0-254 and the byte in bits 0-7 of word 255, if bits 0-7 of word 255
  419. contains the value 0xA5. Each byte shall be added with unsigned
  420. arithmetic, and overflow shall be ignored. The sum of all 512 bytes is
  421. zero when the checksum is correct.
  422. --*/
  423. typedef struct _ATA_IDENTIFY_PACKET {
  424. USHORT Configuration;
  425. USHORT Reserved1[9];
  426. CHAR SerialNumber[20];
  427. USHORT Reserved2[3];
  428. CHAR FirmwareRevision[8];
  429. CHAR ModelNumber[40];
  430. USHORT MaxMultipleSectorTransfer;
  431. USHORT Reserved3;
  432. ULONG Capabilities;
  433. USHORT Reserved4[2];
  434. USHORT ValidFields;
  435. USHORT Reserved5[5];
  436. USHORT CurrentMaxSectorTransfer;
  437. ULONG TotalSectors;
  438. USHORT Reserved6;
  439. USHORT MultiwordDmaSettings;
  440. USHORT PioModesSupported;
  441. USHORT MinMultiwordTransferCycles;
  442. USHORT RecommendedMultiwordTransferCycles;
  443. USHORT MinPioTransferCyclesNoFlow;
  444. USHORT MinPioTransferCyclesWithFlow;
  445. USHORT Reserved7[6];
  446. USHORT QueueDepth;
  447. USHORT Reserved8[4];
  448. USHORT MajorVersion;
  449. USHORT MinorVersion;
  450. ULONG CommandSetSupported;
  451. USHORT FeatureSetSupported;
  452. ULONG CommandSetEnabled;
  453. USHORT CommandSetDefault;
  454. USHORT UltraDmaSettings;
  455. USHORT SecurityEraseTime;
  456. USHORT EnhancedSecurityEraseTime;
  457. USHORT CurrentPowerManagementValue;
  458. USHORT PasswordRevisionCode;
  459. USHORT ResetResult;
  460. USHORT AcousticManagement;
  461. USHORT Reserved9[5];
  462. ULONGLONG TotalSectorsLba48;
  463. USHORT Reserved10[23];
  464. USHORT RemovableMediaStatus;
  465. USHORT SecurityStatus;
  466. USHORT Reserved11[31];
  467. USHORT PowerMode1;
  468. USHORT Reserved12[15];
  469. USHORT MediaSerialNumber[30];
  470. USHORT Reserved13[49];
  471. USHORT Checksum;
  472. } PACKED ATA_IDENTIFY_PACKET, *PATA_IDENTIFY_PACKET;
  473. //
  474. // -------------------------------------------------------------------- Globals
  475. //
  476. //
  477. // -------------------------------------------------------- Function Prototypes
  478. //