edma3.h 8.2 KB

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  1. /*++
  2. Copyright (c) 2016 Minoca Corp. All Rights Reserved
  3. Module Name:
  4. edma3.h
  5. Abstract:
  6. This header contains definitions for using the TI EDMA3 controller.
  7. Author:
  8. Evan Green 2-Feb-2016
  9. --*/
  10. //
  11. // ------------------------------------------------------------------- Includes
  12. //
  13. //
  14. // --------------------------------------------------------------------- Macros
  15. //
  16. //
  17. // These macros convert a channel to its queue number register and offset.
  18. //
  19. #define EDMA_CHANNEL_QUEUE_REGISTER(_Channel) \
  20. (EdmaDmaQueue0 + (((_Channel) / 8) * 4))
  21. #define EDMA_CHANNEL_QUEUE_SHIFT(_Channel) (((_Channel) % 8) * 4)
  22. //
  23. // This macro returns the register for the DMA channel map of a given channel.
  24. //
  25. #define EDMA_DMA_CHANNEL_MAP(_Channel) (EdmaDmaChannelMap0 + ((_Channel) * 4))
  26. #define EDMA_GET_PARAM(_Controller, _Param) \
  27. (EdmaParam + ((_Param) * sizeof(EDMA_PARAM)))
  28. //
  29. // These macros return region access registers for the given region.
  30. //
  31. #define EDMA_DMA_REGION_ACCESS(_Region) \
  32. (EdmaDmaRegionAccessEnable0 + ((_Region) * 8))
  33. #define EDMA_QDMA_REGION_ACCESS(_Region) \
  34. (EdmaQDmaRegionAccessEnable0 + ((_Region) * 8))
  35. //
  36. // ---------------------------------------------------------------- Definitions
  37. //
  38. #define UUID_EDMA_CONTROLLER {{0x010378B8, 0xADC044E1, 0x81D6A857, 0x1CB79BD5}}
  39. #define EDMA_CHANNEL_COUNT 64
  40. #define EDMA_PARAM_COUNT 256
  41. #define EDMA_LINK_TERMINATE 0xFFFF
  42. //
  43. // Define the maximum transfer size for one PaRAM entry, rounded down to the
  44. // nearest page boundary to prevent awkward remainders.
  45. //
  46. #define EDMA_MAX_TRANSFER_SIZE 0xF000
  47. //
  48. // Define EDMA transfer options.
  49. //
  50. #define EDMA_TRANSFER_SUPERVISOR (1 << 31)
  51. #define EDMA_TRANSFER_PRIVILEGE_ID_SHIFT 24
  52. #define EDMA_TRANSFER_PRIVILEGE_ID_MASK (0xF << 24)
  53. #define EDMA_TRANSFER_INTERMEDIATE_COMPLETION_CHAIN (1 << 23)
  54. #define EDMA_TRANSFER_COMPLETION_CHAIN (1 << 22)
  55. #define EDMA_TRANSFER_INTERMEDIATE_COMPLETION_INTERRUPT (1 << 21)
  56. #define EDMA_TRANSFER_COMPLETION_INTERRUPT (1 << 20)
  57. #define EDMA_TRANSFER_COMPLETION_CODE_SHIFT 12
  58. #define EDMA_TRANSFER_COMPLETION_CODE_MASK (0x3F << 12)
  59. #define EDMA_TRANSFER_EARLY_COMPLETION (1 << 11)
  60. #define EDMA_TRANSFER_FIFO_WIDTH_8 (0 << 8)
  61. #define EDMA_TRANSFER_FIFO_WIDTH_16 (1 << 8)
  62. #define EDMA_TRANSFER_FIFO_WIDTH_32 (2 << 8)
  63. #define EDMA_TRANSFER_FIFO_WIDTH_64 (3 << 8)
  64. #define EDMA_TRANSFER_FIFO_WIDTH_128 (4 << 8)
  65. #define EDMA_TRANSFER_FIFO_WIDTH_256 (5 << 8)
  66. #define EDMA_TRANSFER_STATIC (1 << 3)
  67. #define EDMA_TRANSFER_A_SYNCHRONIZED (0 << 2)
  68. #define EDMA_TRANSFER_AB_SYNCHRONIZED (1 << 2)
  69. #define EDMA_TRANSFER_DESTINATION_FIFO (1 << 1)
  70. #define EDMA_TRANSFER_SOURCE_FIFO (1 << 0)
  71. #define EDMA_QUEUE_NUMBER_MASK 0x0000000F
  72. //
  73. // ------------------------------------------------------ Data Type Definitions
  74. //
  75. typedef enum _EDMA3_TRIGGER_MODE {
  76. EdmaTriggerModeInvalid,
  77. EdmaTriggerModeManual,
  78. EdmaTriggerModeEvent
  79. } EDMA3_TRIGGER_MODE, *PEDMA3_TRIGGER_MODE;
  80. typedef enum _EDMA3_REGISTER {
  81. EdmaPid = 0x0000,
  82. EdmaCcConfig = 0x0004,
  83. EdmaSysConfig = 0x0010,
  84. EdmaDmaChannelMap0 = 0x0100,
  85. EdmaQDmaChannelMap0 = 0x0200,
  86. EdmaDmaQueue0 = 0x0240,
  87. EdmaQDmaQueue = 0x0260,
  88. EdmaQueuePriority = 0x0284,
  89. EdmaEventMissedLow = 0x0300,
  90. EdmaEventMissedHigh = 0x0304,
  91. EdmaEventMissedClearLow = 0x0308,
  92. EdmaEventMissedClearHigh = 0x030C,
  93. EdmaQDmaEventMissed = 0x0310,
  94. EdmaQDmaEventMissedClear = 0x0314,
  95. EdmaCcError = 0x0318,
  96. EdmaCcErrorClear = 0x031C,
  97. EdmaErrorEvaluate = 0x0320,
  98. EdmaDmaRegionAccessEnable0 = 0x0340,
  99. EdmaDmaRegionAccessEnableHigh0 = 0x0344,
  100. EdmaQDmaRegionAccessEnable0 = 0x0380,
  101. EdmaEventQueue0 = 0x0400,
  102. EdmaEventQueue1 = 0x0440,
  103. EdmaEventQueue2 = 0x0480,
  104. EdmaQueueStatus0 = 0x0600,
  105. EdmaQueueStatus1 = 0x0604,
  106. EdmaQueueStatus2 = 0x0608,
  107. EdmaQueueWatermarkThresholdA = 0x0620,
  108. EdmaCcStatus = 0x0640,
  109. EdmaMemoryProtectionFaultAddress = 0x0800,
  110. EdmaMemoryProtectionFaultStatus = 0x0804,
  111. EdmaMemoryProtectionFaultCommand = 0x0808,
  112. EdmaMemoryProtectionPageAttribute = 0x080C,
  113. EdmaMemoryProtectionPageAttribute0 = 0x0810,
  114. EdmaEventLow = 0x1000,
  115. EdmaEventHigh = 0x1004,
  116. EdmaEventClearLow = 0x1008,
  117. EdmaEventClearHigh = 0x100C,
  118. EdmaEventSetLow = 0x1010,
  119. EdmaEventSetHigh = 0x1014,
  120. EdmaChainedEventLow = 0x1018,
  121. EdmaChainedEventHigh = 0x101C,
  122. EdmaEventEnableLow = 0x1020,
  123. EdmaEventEnableHigh = 0x1024,
  124. EdmaEventEnableClearLow = 0x1028,
  125. EdmaEventEnableClearHigh = 0x102C,
  126. EdmaEventEnableSetLow = 0x1030,
  127. EdmaEventEnableSetHigh = 0x1034,
  128. EdmaSecondaryEventLow = 0x1038,
  129. EdmaSecondaryEventHigh = 0x103C,
  130. EdmaSecondaryEventClearLow = 0x1040,
  131. EdmaSecondaryEventClearHigh = 0x1044,
  132. EdmaInterruptEnableLow = 0x1050,
  133. EdmaInterruptEnableHigh = 0x1054,
  134. EdmaInterruptEnableClearLow = 0x1058,
  135. EdmaInterruptEnableClearHigh = 0x105C,
  136. EdmaInterruptEnableSetLow = 0x1060,
  137. EdmaInterruptEnableSetHigh = 0x1064,
  138. EdmaInterruptPendingLow = 0x1068,
  139. EdmaInterruptPendingHigh = 0x106C,
  140. EdmaInterruptClearLow = 0x1070,
  141. EdmaInterruptClearHigh = 0x1074,
  142. EdmaInterruptEvaluate = 0x1078,
  143. EdmaQDmaEvent = 0x1080,
  144. EdmaQDmaEventEnable = 0x1084,
  145. EdmaQDmaEventEnableClear = 0x1088,
  146. EdmaQDmaEventEnableSet = 0x108C,
  147. EdmaQDmaSecondaryEvent = 0x1090,
  148. EdmaQDmaSecondaryEventClear = 0x1094,
  149. EdmaParam = 0x4000,
  150. } EDMA3_REGISTER, *PEDMA3_REGISTER;
  151. /*++
  152. Structure Description:
  153. This structure defines the format of an EDMA3 PaRAM parameter set, as
  154. mandated by the hardware.
  155. Members:
  156. Options - Stores the configuration options.
  157. Source - Stores the byte-aligned physical address from which data is
  158. transferred.
  159. ACount - Stores the number of contiguous bytes for each transfer in the
  160. first (most inner) dimension.
  161. BCount - Stores the number of elements in the A array (second most inner
  162. dimension).
  163. Destination - Stores the byte aligned physical address to which data is
  164. transferred.
  165. SourceBIndex - Stores the byte offset between A arrays in the source. This
  166. probably shouldn't be less than the A count unless it's zero.
  167. DestinationBIndex - Stores the byte offset between A arrays in the
  168. destination. This probably shouldn't be less than the A count unless
  169. it's zero.
  170. Link - Stores the PaRAM set to be copied from when this one completes.
  171. Supply 0xFFFF to end the transfer.
  172. BCountReload - Stores the count value used to reload BCount when BCount
  173. decrements to zero. This is only relevant in A-synchronized transfers.
  174. SourceCIndex - Stores the byte address offset between frames (B arrays).
  175. For A-synchronized transfers, this is the byte address offset from the
  176. beginning of the last source array in a frame to the beginning of the
  177. first source array in the next frame. For AB-synchronized transfers,
  178. this is the byte address offset from the beginning of the first source
  179. array in a frame to the beginning of the first source array in the
  180. next frame.
  181. DestinationCIndex - Stores the byte address offset between frames (B arrays)
  182. in the destination. This is analagous to the source C index.
  183. CCount - Stores the number of frames in a block (the outermost loop).
  184. Reserved - Stores a reserved value. Set this to zero.
  185. --*/
  186. typedef struct _EDMA_PARAM {
  187. ULONG Options;
  188. ULONG Source;
  189. USHORT ACount;
  190. USHORT BCount;
  191. ULONG Destination;
  192. SHORT SourceBIndex;
  193. SHORT DestinationBIndex;
  194. USHORT Link;
  195. USHORT BCountReload;
  196. SHORT SourceCIndex;
  197. SHORT DestinationCIndex;
  198. USHORT CCount;
  199. USHORT Reserved;
  200. } PACKED EDMA_PARAM, *PEDMA_PARAM;
  201. /*++
  202. Structure Description:
  203. This structure defines the format of an EDMA3 transfer configuration.
  204. Members:
  205. Param - Stores the PaRAM values for the transfer.
  206. Mode - Stores the trigger mode.
  207. Queue - Stores the event queue to associate the channel with. There are 3
  208. independent queues.
  209. --*/
  210. typedef struct _EDMA_CONFIGURATION {
  211. EDMA_PARAM Param;
  212. EDMA3_TRIGGER_MODE Mode;
  213. ULONG Queue;
  214. } EDMA_CONFIGURATION, *PEDMA_CONFIGURATION;
  215. //
  216. // -------------------------------------------------------------------- Globals
  217. //
  218. //
  219. // -------------------------------------------------------- Function Prototypes
  220. //