x86.h 39 KB

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  1. /*++
  2. Copyright (c) 2012 Minoca Corp. All Rights Reserved
  3. Module Name:
  4. x86.h
  5. Abstract:
  6. This header contains definitions for aspects of the system that are specific
  7. to the x86 architecture.
  8. Author:
  9. Evan Green 3-Jul-2012
  10. --*/
  11. //
  12. // ---------------------------------------------------------------- Definitions
  13. //
  14. #define TASK_GATE_TYPE 0x05
  15. #define CALL_GATE_TYPE 0x0C
  16. #define INTERRUPT_GATE_TYPE 0x0E
  17. #define TRAP_GATE_TYPE 0x0F
  18. #define SEGMENT_PRIVILEGE_MASK 0x0003
  19. #define SEGMENT_PRIVILEGE_KERNEL 0x0000
  20. #define SEGMENT_PRIVILEGE_USER 0x0003
  21. #define KERNEL_CS 0x08
  22. #define KERNEL_DS 0x10
  23. #define USER_CS (0x18 | SEGMENT_PRIVILEGE_USER)
  24. #define USER_DS (0x20 | SEGMENT_PRIVILEGE_USER)
  25. #define GDT_PROCESSOR 0x28
  26. #define GDT_THREAD (0x30 | SEGMENT_PRIVILEGE_USER)
  27. #define KERNEL_TSS 0x38
  28. #define DOUBLE_FAULT_TSS 0x40
  29. #define NMI_TSS 0x48
  30. #define GDT_ENTRIES 10
  31. #define DEFAULT_GDT_ACCESS 0x80
  32. #define DEFAULT_GDT_GRANULARITY 0x40
  33. #define MAX_GDT_LIMIT 0xFFFFF
  34. #define GDT_SYSTEM_SEGMENT 0x00
  35. #define GDT_CODE_DATA_SEGMENT 0x10
  36. #define GDT_TSS_BUSY 0x02
  37. #define IDT_SIZE 0x100
  38. #define VECTOR_DIVIDE_ERROR 0x00
  39. #define VECTOR_DEBUG 0x01
  40. #define VECTOR_NMI 0x02
  41. #define VECTOR_BREAKPOINT 0x03
  42. #define VECTOR_OVERFLOW 0x04
  43. #define VECTOR_BOUND 0x05
  44. #define VECTOR_INVALID_OPCODE 0x06
  45. #define VECTOR_DEVICE_NOT_AVAILABLE 0x07
  46. #define VECTOR_DOUBLE_FAULT 0x08
  47. #define VECTOR_SEGMENT_OVERRUN 0x09
  48. #define VECTOR_INVALID_TSS 0x0A
  49. #define VECTOR_INVALID_SEGMENT 0x0B
  50. #define VECTOR_STACK_EXCEPTION 0x0C
  51. #define VECTOR_PROTECTION_FAULT 0x0D
  52. #define VECTOR_PAGE_FAULT 0x0E
  53. #define VECTOR_MATH_FAULT 0x10
  54. #define VECTOR_ALIGNMENT_CHECK 0x11
  55. #define VECTOR_MACHINE_CHECK 0x12
  56. #define VECTOR_SIMD_EXCEPTION 0x13
  57. #define VECTOR_DEBUG_SERVICE 0x21
  58. #define VECTOR_SYSTEM_CALL 0x2F
  59. #define VECTOR_CLOCK_INTERRUPT 0xD0
  60. #define VECTOR_CLOCK_IPI 0xD1
  61. #define VECTOR_IPI_INTERRUPT 0xE0
  62. #define VECTOR_TLB_IPI 0xE1
  63. #define VECTOR_PROFILER_INTERRUPT 0xF0
  64. #define PROCESSOR_VECTOR_COUNT 0x20
  65. #define MINIMUM_VECTOR 0x30
  66. #define MAXIMUM_VECTOR 0xFF
  67. #define MAXIMUM_DEVICE_VECTOR 0xBF
  68. #define INTERRUPT_VECTOR_COUNT IDT_SIZE
  69. #define IO_PORT_COUNT 0x10000
  70. #define IA32_EFLAG_CF 0x00000001
  71. #define IA32_EFLAG_PF 0x00000004
  72. #define IA32_EFLAG_AF 0x00000010
  73. #define IA32_EFLAG_ZF 0x00000040
  74. #define IA32_EFLAG_SF 0x00000080
  75. #define IA32_EFLAG_TF 0x00000100
  76. #define IA32_EFLAG_IF 0x00000200
  77. #define IA32_EFLAG_DF 0x00000400
  78. #define IA32_EFLAG_OF 0x00000800
  79. #define IA32_EFLAG_IOPL_MASK 0x00003000
  80. #define IA32_EFLAG_IOPL_USER 0x00003000
  81. #define IA32_EFLAG_IOPL_SHIFT 12
  82. #define IA32_EFLAG_NT 0x00004000
  83. #define IA32_EFLAG_RF 0x00010000
  84. #define IA32_EFLAG_VM 0x00020000
  85. #define IA32_EFLAG_AC 0x00040000
  86. #define IA32_EFLAG_VIF 0x00080000
  87. #define IA32_EFLAG_VIP 0x00100000
  88. #define IA32_EFLAG_ID 0x00200000
  89. #define IA32_EFLAG_ALWAYS_0 0xFFC08028
  90. #define IA32_EFLAG_ALWAYS_1 0x00000002
  91. #define IA32_EFLAG_STATUS \
  92. (IA32_EFLAG_CF | IA32_EFLAG_PF | IA32_EFLAG_AF | IA32_EFLAG_ZF | \
  93. IA32_EFLAG_SF | IA32_EFLAG_OF)
  94. #define IA32_EFLAG_USER \
  95. (IA32_EFLAG_STATUS | IA32_EFLAG_DF | IA32_EFLAG_TF | IA32_EFLAG_RF)
  96. #define CR0_PAGING_ENABLE 0x80000000
  97. #define CR0_WRITE_PROTECT_ENABLE 0x00010000
  98. #define CR0_TASK_SWITCHED 0x00000008
  99. #define CR4_OS_XMM_EXCEPTIONS 0x00000400
  100. #define CR4_OS_FX_SAVE_RESTORE 0x00000200
  101. #define CR4_PAGE_GLOBAL_ENABLE 0x00000080
  102. #define PAGE_SIZE 4096
  103. #define PAGE_MASK 0x00000FFF
  104. #define PAGE_SHIFT 12
  105. #define PAGE_DIRECTORY_SHIFT 22
  106. #define PDE_INDEX_MASK 0xFFC00000
  107. #define PTE_INDEX_MASK 0x003FF000
  108. #define X86_FAULT_FLAG_PROTECTION_VIOLATION 0x00000001
  109. #define X86_FAULT_ERROR_CODE_WRITE 0x00000002
  110. //
  111. // Define the location of the legacy keyboard controller. While not strictly
  112. // architectural, it's pretty close.
  113. //
  114. #define PC_8042_CONTROL_PORT 0x64
  115. #define PC_8042_RESET_VALUE 0xFE
  116. #define PC_8042_INPUT_BUFFER_FULL 0x02
  117. //
  118. // Define CPUID EAX values.
  119. //
  120. #define X86_CPUID_IDENTIFICATION 0x00000000
  121. #define X86_CPUID_BASIC_INFORMATION 0x00000001
  122. #define X86_CPUID_MWAIT 0x00000005
  123. #define X86_CPUID_EXTENDED_IDENTIFICATION 0x80000000
  124. #define X86_CPUID_EXTENDED_INFORMATION 0x80000001
  125. #define X86_CPUID_ADVANCED_POWER_MANAGEMENT 0x80000007
  126. //
  127. // Define basic information CPUID bits (eax is 1).
  128. //
  129. #define X86_CPUID_BASIC_EAX_STEPPING_MASK 0x00000003
  130. #define X86_CPUID_BASIC_EAX_BASE_MODEL_MASK (0xF << 4)
  131. #define X86_CPUID_BASIC_EAX_BASE_MODEL_SHIFT 4
  132. #define X86_CPUID_BASIC_EAX_BASE_FAMILY_MASK (0xF << 8)
  133. #define X86_CPUID_BASIC_EAX_BASE_FAMILY_SHIFT 8
  134. #define X86_CPUID_BASIC_EAX_EXTENDED_MODEL_MASK (0xF << 16)
  135. #define X86_CPUID_BASIC_EAX_EXTENDED_MODEL_SHIFT 16
  136. #define X86_CPUID_BASIC_EAX_EXTENDED_FAMILY_MASK (0xFF << 20)
  137. #define X86_CPUID_BASIC_EAX_EXTENDED_FAMILY_SHIFT 20
  138. #define X86_CPUID_BASIC_ECX_MONITOR (1 << 3)
  139. #define X86_CPUID_BASIC_EDX_SYSENTER (1 << 11)
  140. #define X86_CPUID_BASIC_EDX_CMOV (1 << 15)
  141. #define X86_CPUID_BASIC_EDX_FX_SAVE_RESTORE (1 << 24)
  142. //
  143. // Define known CPU vendors.
  144. //
  145. #define X86_VENDOR_INTEL 0x756E6547
  146. #define X86_VENDOR_AMD 0x68747541
  147. //
  148. // Define monitor/mwait leaf bits.
  149. //
  150. #define X86_CPUID_MWAIT_ECX_EXTENSIONS_SUPPORTED 0x00000001
  151. #define X86_CPUID_MWAIT_ECX_INTERRUPT_BREAK 0x00000002
  152. //
  153. // Define extended information CPUID bits (eax is 0x80000001).
  154. //
  155. #define X86_CPUID_EXTENDED_INFORMATION_EDX_SYSCALL (1 << 11)
  156. //
  157. // Define advanced power management CPUID bits (eax 0x80000007).
  158. //
  159. //
  160. // This bit is set to indicate that the TSC is invariant across all P-states
  161. // and C-states
  162. //
  163. #define X86_CPUID_ADVANCED_POWER_EDX_TSC_INVARIANT (1 << 8)
  164. //
  165. // Define the required alignment for FPU context.
  166. //
  167. #define FPU_CONTEXT_ALIGNMENT 64
  168. //
  169. // Define MSR values.
  170. //
  171. #define X86_MSR_SYSENTER_CS 0x00000174
  172. #define X86_MSR_SYSENTER_ESP 0x00000175
  173. #define X86_MSR_SYSENTER_EIP 0x00000176
  174. #define X86_MSR_POWER_CONTROL 0x000001FC
  175. #define X86_MSR_STAR 0xC0000081
  176. #define X86_MSR_LSTAR 0xC0000082
  177. #define X86_MSR_FMASK 0xC0000084
  178. #define X86_MSR_POWER_CONTROL_C1E_PROMOTION 0x00000002
  179. //
  180. // Define the PTE bits.
  181. #define PTE_FLAG_PRESENT 0x00000001
  182. #define PTE_FLAG_WRITABLE 0x00000002
  183. #define PTE_FLAG_USER_MODE 0x00000004
  184. #define PTE_FLAG_WRITE_THROUGH 0x00000008
  185. #define PTE_FLAG_CACHE_DISABLED 0x00000010
  186. #define PTE_FLAG_ACCESSED 0x00000020
  187. #define PTE_FLAG_DIRTY 0x00000040
  188. #define PTE_FLAG_LARGE_PAGE 0x00000080
  189. #define PTE_FLAG_GLOBAL 0x00000100
  190. #define PTE_FLAG_ENTRY_MASK 0xFFFFF000
  191. #define PTE_FLAG_ENTRY_SHIFT 12
  192. //
  193. // Define the location of the identity mapped stub. Since x86 doesn't have
  194. // relative addressing the AP code really is hardwired for this address. This
  195. // needs to be in the first megabyte since it starts running in real mode, and
  196. // needs to avoid known BIOS regions.
  197. //
  198. #define IDENTITY_STUB_ADDRESS 0x00001000
  199. //
  200. // --------------------------------------------------------------------- Macros
  201. //
  202. //
  203. // This macro gets a value at the given offset from the current processor block.
  204. // _Result should be a ULONG.
  205. //
  206. #define GET_PROCESSOR_BLOCK_OFFSET(_Result, _Offset) \
  207. asm volatile ("mov %%fs:(%1), %0" : "=r" (_Result) : "r" (_Offset))
  208. //
  209. // This macro determines whether or not the given trap frame is from privileged
  210. // mode.
  211. //
  212. #define IS_TRAP_FRAME_FROM_PRIVILEGED_MODE(_TrapFrame) \
  213. (((_TrapFrame)->Cs & SEGMENT_PRIVILEGE_MASK) == 0)
  214. //
  215. // This macro determines whether or not the given trap frame is complete or
  216. // left mostly uninitialized by the system call handler. The system call
  217. // handler sets CS to user DS as a hint that the trap frame is incomplete.
  218. //
  219. #define IS_TRAP_FRAME_COMPLETE(_TrapFrame) \
  220. (IS_TRAP_FRAME_FROM_PRIVILEGED_MODE(_TrapFrame) || \
  221. ((_TrapFrame)->Cs == USER_CS))
  222. //
  223. // ------------------------------------------------------ Data Type Definitions
  224. //
  225. /*++
  226. Structure Description:
  227. This structure defines the format of a task, interrupt, or call gate
  228. descriptor. This structure must not be padded, since the hardware relies on
  229. this exact format.
  230. Members:
  231. LowOffset - Stores the lower 16 bits of the gate's destination address.
  232. Selector - Stores the code segment selector the gate code should run in.
  233. Count - Must be 0 for entries in the IDT.
  234. Access - Stores various properties of the gate.
  235. Bit 7: Present. 1 if the gate is present, 0 if not present.
  236. Bits 6-5: DPL. Sets the ring number this handler executes in. Zero is
  237. the most privileged ring, 3 is least privileged.
  238. Bit 4: Reserved (set to 0).
  239. Bits 3-0: The gate type. Set to CALL_GATE_TYPE, INTERRUPT_GATE_TYPE,
  240. TASK_GATE_TYPE, or TRAP_GATE_TYPE.
  241. HighOffset - Stores the upper 16 bits of the interrupt handler's address.
  242. --*/
  243. typedef struct _PROCESSOR_GATE {
  244. USHORT LowOffset;
  245. USHORT Selector;
  246. BYTE Count;
  247. BYTE Access;
  248. USHORT HighOffset;
  249. } PACKED PROCESSOR_GATE, *PPROCESSOR_GATE;
  250. /*++
  251. Structure Description:
  252. This structure defines the format of the GDTR, IDTR, or TR. This structure
  253. must be packed since it represents a hardware construct.
  254. Members:
  255. Limit - Stores the last valid byte of the table, essentially size - 1.
  256. Base - Stores a pointer to the Global Descriptor Table, Interrupt
  257. Descriptor Table, or Task Table.
  258. --*/
  259. typedef struct _TABLE_REGISTER {
  260. USHORT Limit;
  261. ULONG Base;
  262. } PACKED TABLE_REGISTER, *PTABLE_REGISTER;
  263. /*++
  264. Structure Description:
  265. This structure defines the x86 Task State Segment. It represents a complete
  266. task state as understood by the hardware.
  267. Members:
  268. BackLink - Stores a pointer to the previous executing task. This value is
  269. written by the processor.
  270. Esp0-2 - Stores the stack pointer to load for each of the privilege levels.
  271. Ss0-2 - Stores the stack segment to load for each of the privilege levels.
  272. Pad0-9 - Stores padding in the structure. The processor does not use these
  273. fields, but they should not be modified.
  274. Cr3 - Stores the value of CR3 used by the task.
  275. Eip - Stores the currently executing instruction pointer.
  276. Eflags through Edi - Stores the state of the general registers when this
  277. task was last run.
  278. Es through Gs - Stores the state of the segment registers when this task
  279. was last run.
  280. LdtSelector - Stores the selector of the Local Descriptor Table when this
  281. task was last run.
  282. DebugTrap - Stores information only relevant when doing on-chip debugging.
  283. IoMapBase - Stores the 16 bit offset from the TSS base to the 8192 byte I/O
  284. Bitmap.
  285. --*/
  286. typedef struct _TSS {
  287. ULONG BackLink;
  288. ULONG Esp0;
  289. USHORT Ss0;
  290. USHORT Pad0;
  291. ULONG Esp1;
  292. USHORT Ss1;
  293. USHORT Pad1;
  294. ULONG Esp2;
  295. USHORT Ss2;
  296. USHORT Pad2;
  297. ULONG Cr3;
  298. ULONG Eip;
  299. ULONG Eflags;
  300. ULONG Eax;
  301. ULONG Ecx;
  302. ULONG Edx;
  303. ULONG Ebx;
  304. ULONG Esp;
  305. ULONG Ebp;
  306. ULONG Esi;
  307. ULONG Edi;
  308. USHORT Es;
  309. USHORT Pad3;
  310. USHORT Cs;
  311. USHORT Pad4;
  312. USHORT Ss;
  313. USHORT Pad5;
  314. USHORT Ds;
  315. USHORT Pad6;
  316. USHORT Fs;
  317. USHORT Pad7;
  318. USHORT Gs;
  319. USHORT Pad8;
  320. USHORT LdtSelector;
  321. USHORT Pad9;
  322. USHORT DebugTrap;
  323. USHORT IoMapBase;
  324. } PACKED TSS, *PTSS;
  325. typedef enum _GDT_GRANULARITY {
  326. GdtByteGranularity = 0x00,
  327. GdtKilobyteGranularity = 0x80
  328. } GDT_GRANULARITY, *PGDT_GRANULARITY;
  329. typedef enum _GDT_SEGMENT_TYPE {
  330. GdtDataReadOnly = 0x0,
  331. GdtDataReadWrite = 0x2,
  332. GdtCodeExecuteOnly = 0x8,
  333. Gdt32BitTss = 0x9
  334. } GDT_SEGMENT_TYPE, *PGDT_SEGMENT_TYPE;
  335. /*++
  336. Structure Description:
  337. This structure define a Global Descriptor Table entry. The GDT table sets
  338. up the segmentation features of the processor and privilege levels.
  339. Members:
  340. LimitLow - Stores the lower 16 bits of the descriptor limit.
  341. BaseLow - Stores the lower 16 bits of the descriptor base.
  342. BaseMiddle - Stores the next 8 bits of the base.
  343. Access - Stores the access flags. The access byte has the following format:
  344. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
  345. | | | | |
  346. | P | DPL | S | Type |
  347. P - Is segment present (1 = Yes)
  348. DPL - Descriptor privilege level: Ring 0-3. Zero is the highest
  349. privilege, 3 is the lowest (least privileged).
  350. S - System flag. Set to 0 if it's a system segment, or 1 if it's a
  351. code/data segment.
  352. Type - Segment type: code segment / data segment. The Type field
  353. has the following definition:
  354. Bit 3 - Set to 1 for Code, or 0 for Data.
  355. Bit 2 - Expansion direction. Set to 0 for expand-up, or 1 for
  356. expand-down.
  357. Bit 1 - Write-Enable. Set to 0 for Read Only, or 1 for
  358. Read/Write.
  359. Bit 0 - Accessed. This bit is set by the processor when memory
  360. in this segment is accessed. It is never cleared by
  361. hardware.
  362. Granularity - Stores the granularity for the descriptor. The granularity
  363. byte has the following format:
  364. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
  365. | | | | | |
  366. | G | D | 0 | A | Segment length 19:16 |
  367. G - Granularity. 0 = 1 byte, 1 = 1 KByte.
  368. D - Operand Size. 0 = 16 bit, 1 = 32 bit.
  369. 0 - Always zero.
  370. A - Available for system use (always zero).
  371. BaseHigh - Stores the high 8 bits of the base address.
  372. --*/
  373. typedef struct _GDT_ENTRY {
  374. USHORT LimitLow;
  375. USHORT BaseLow;
  376. UCHAR BaseMiddle;
  377. UCHAR Access;
  378. UCHAR Granularity;
  379. UCHAR BaseHigh;
  380. } PACKED GDT_ENTRY, *PGDT_ENTRY;
  381. /*++
  382. Structure Description:
  383. This structure defines the format of an entry in a page table or directory.
  384. Members:
  385. Present - Stores whether or not the page is present in memory.
  386. Writable - Stores whether or not this page is read-only (0) or writable (1).
  387. User - Stores whether or not this page is accessible by user mode (1) or
  388. only by kernel mode (0).
  389. WriteThrough - Stores whether or not write-through caching is enabled (1)
  390. or write-back caching (0).
  391. CacheDisabled - Stores whether or not to use caching. If this bit is set,
  392. the page will not be cached.
  393. Accessed - Stores whether or not the page has been accessed. This bit is
  394. set automatically by the processor, but will never be cleared by the
  395. processor.
  396. Dirty - Stores whether or not this page has been written to. This bit is
  397. set automatically by the processor, but must be cleared by software.
  398. LargePage - Stores whether or not large 4MB pages are in use (1) or 4kB
  399. pages (0).
  400. Global - Stores whether or not the TLB should avoid flushing this address
  401. if CR3 is changed. If this bit is set, then the TLB entry for this page
  402. will not be invalidated when CR3 is reset.
  403. Unused - These bits are unused by both the processor and the OS.
  404. Entry - Stores a pointer to the 4kB aligned page.
  405. --*/
  406. typedef struct _PTE {
  407. ULONG Present:1;
  408. ULONG Writable:1;
  409. ULONG User:1;
  410. ULONG WriteThrough:1;
  411. ULONG CacheDisabled:1;
  412. ULONG Accessed:1;
  413. ULONG Dirty:1;
  414. ULONG LargePage:1;
  415. ULONG Global:1;
  416. ULONG Unused:3;
  417. ULONG Entry:20;
  418. } PACKED PTE, *PPTE;
  419. /*++
  420. Structure Description:
  421. This structure defines the extended state of the x86 architecture. This
  422. structure is architecturally defined by the FXSAVE and FXRSTOR instructions.
  423. Members:
  424. Registers - Stores the extended processor state.
  425. --*/
  426. struct _FPU_CONTEXT {
  427. USHORT Fcw;
  428. USHORT Fsw;
  429. USHORT Ftw;
  430. USHORT Fop;
  431. ULONG FpuIp;
  432. USHORT Cs;
  433. USHORT Reserved1;
  434. ULONG FpuDp;
  435. USHORT Ds;
  436. USHORT Reserved2;
  437. ULONG Mxcsr;
  438. ULONG MxcsrMask;
  439. UCHAR St0Mm0[16];
  440. UCHAR St1Mm1[16];
  441. UCHAR St2Mm2[16];
  442. UCHAR St3Mm3[16];
  443. UCHAR St4Mm4[16];
  444. UCHAR St5Mm5[16];
  445. UCHAR St6Mm6[16];
  446. UCHAR St7Mm7[16];
  447. UCHAR Xmm0[16];
  448. UCHAR Xmm1[16];
  449. UCHAR Xmm2[16];
  450. UCHAR Xmm3[16];
  451. UCHAR Xmm4[16];
  452. UCHAR Xmm5[16];
  453. UCHAR Xmm6[16];
  454. UCHAR Xmm7[16];
  455. UCHAR Padding[224];
  456. } PACKED ALIGNED64;
  457. /*++
  458. Structure Description:
  459. This structure outlines a trap frame that will be generated during most
  460. interrupts and exceptions.
  461. Members:
  462. Registers - Stores the current state of the machine's registers. These
  463. values will be restored upon completion of the interrupt or exception.
  464. --*/
  465. struct _TRAP_FRAME {
  466. ULONG Ds;
  467. ULONG Es;
  468. ULONG Fs;
  469. ULONG Gs;
  470. ULONG Ss;
  471. ULONG Eax;
  472. ULONG Ebx;
  473. ULONG Ecx;
  474. ULONG Edx;
  475. ULONG Esi;
  476. ULONG Edi;
  477. ULONG Ebp;
  478. ULONG ErrorCode;
  479. ULONG Eip;
  480. ULONG Cs;
  481. ULONG Eflags;
  482. ULONG Esp;
  483. } PACKED;
  484. /*++
  485. Structure Description:
  486. This structure outlines the register state saved by the kernel when a
  487. user mode signal is dispatched. This generally contains 1) control
  488. registers which are clobbered by switching to the signal handler, and
  489. 2) volatile registers.
  490. Members:
  491. Common - Stores the common signal context information.
  492. TrapFrame - Stores the general register state.
  493. FpuContext - Stores the FPU state.
  494. --*/
  495. typedef struct _SIGNAL_CONTEXT_X86 {
  496. SIGNAL_CONTEXT Common;
  497. TRAP_FRAME TrapFrame;
  498. FPU_CONTEXT FpuContext;
  499. } PACKED SIGNAL_CONTEXT_X86, *PSIGNAL_CONTEXT_X86;
  500. /*++
  501. Structure Description:
  502. This structure contains the state of the processor, including both the
  503. non-volatile general registers and the system registers configured by the
  504. kernel. This structure is used in a manner similar to the C library
  505. setjmp/longjmp routines, the save context function appears to return
  506. twice. It returns once after the saving is complete, and then again with
  507. a different return value after restoring. Be careful when modifying this
  508. structure, as its offsets are used directly in assembly by the save/restore
  509. routines.
  510. Members:
  511. Eax - Stores the value to return when restoring.
  512. Eip - Stores the instruction pointer to jump back to on restore. By default
  513. this is initialized to the return from whoever called save.
  514. Cs - Stores the code segment.
  515. Eflags - Stores the eflags register.
  516. Ebx - Stores a non-volatile general register.
  517. Esi - Stores a non-volatile general register.
  518. Edi - Stores a non-volatile general register.
  519. Esp - Stores a non-volatile general register.
  520. Ebp - Stores a non-volatile general register.
  521. Esp - Stores the stack pointer. This should be restored after the final
  522. page tables are in place to avoid NMIs having an invalid stack.
  523. Dr7 - Stores a debug register. This should be restored last of the debug
  524. registers.
  525. Dr6 - Stores a debug register.
  526. Dr0 - Stores a debug register.
  527. Dr1 - Stores a debug register.
  528. Dr2 - Stores a debug register.
  529. Dr3 - Stores a debug register.
  530. VirtualAddress - Stores the virtual address of this structure member, which
  531. is used in case the restore of CR0 that just happened enabled paging
  532. suddenly.
  533. Cr0 - Stores the CR0 control register value.
  534. Cr2 - Stores the CR2 control register value (faulting address).
  535. Cr3 - Stores the CR3 control register value (top level page directory).
  536. Cr4 - Stores the CR4 control register value.
  537. Tr - Stores the task register (must be restored after the GDT).
  538. Idt - Stores the interrupt descriptor table. The stack should be restored
  539. before this because once this is restored NMIs could come in and use
  540. stack (rather than the stub function they may currently be on).
  541. Gdt - Stores the global descriptor table.
  542. --*/
  543. struct _PROCESSOR_CONTEXT {
  544. ULONG Eax;
  545. ULONG Eip;
  546. ULONG Cs;
  547. ULONG Eflags;
  548. ULONG Ebx;
  549. ULONG Esi;
  550. ULONG Edi;
  551. ULONG Ebp;
  552. ULONG Esp;
  553. ULONG Dr7;
  554. ULONG Dr6;
  555. ULONG Dr0;
  556. ULONG Dr1;
  557. ULONG Dr2;
  558. ULONG Dr3;
  559. ULONG VirtualAddress;
  560. ULONG Cr0;
  561. ULONG Cr2;
  562. ULONG Cr3;
  563. ULONG Cr4;
  564. ULONG Tr;
  565. TABLE_REGISTER Idt;
  566. TABLE_REGISTER Gdt;
  567. } PACKED;
  568. typedef
  569. VOID
  570. (*PAR_SAVE_RESTORE_FPU_CONTEXT) (
  571. PFPU_CONTEXT Buffer
  572. );
  573. /*++
  574. Routine Description:
  575. This routine saves or restores floating point context from the processor.
  576. Arguments:
  577. Buffer - Supplies a pointer to the buffer where the information will be
  578. saved to or loaded from. This buffer must be 16-byte aligned.
  579. Return Value:
  580. None.
  581. --*/
  582. /*++
  583. Structure Description:
  584. This structure defines the architecture specific form of an address space
  585. structure.
  586. Members:
  587. Common - Stores the common address space information.
  588. PageDirectory - Stores the virtual address of the top level page directory.
  589. PageDirectoryPhysical - Stores the physical address of the top level page
  590. directory.
  591. PageTableCount - Stores the number of page tables that were allocated on
  592. behalf of this process (user mode only).
  593. --*/
  594. typedef struct _ADDRESS_SPACE_X86 {
  595. ADDRESS_SPACE Common;
  596. PPTE PageDirectory;
  597. ULONG PageDirectoryPhysical;
  598. ULONG PageTableCount;
  599. } ADDRESS_SPACE_X86, *PADDRESS_SPACE_X86;
  600. //
  601. // -------------------------------------------------------------------- Globals
  602. //
  603. //
  604. // Store pointers to functions used to save and restore floating point state.
  605. //
  606. extern PAR_SAVE_RESTORE_FPU_CONTEXT ArSaveFpuState;
  607. extern PAR_SAVE_RESTORE_FPU_CONTEXT ArRestoreFpuState;
  608. //
  609. // -------------------------------------------------------- Function Prototypes
  610. //
  611. VOID
  612. ArLoadKernelDataSegments (
  613. VOID
  614. );
  615. /*++
  616. Routine Description:
  617. This routine switches the data segments DS and ES to the kernel data
  618. segment selectors.
  619. Arguments:
  620. None.
  621. Return Value:
  622. None.
  623. --*/
  624. VOID
  625. ArLoadTr (
  626. USHORT TssSegment
  627. );
  628. /*++
  629. Routine Description:
  630. This routine loads a TSS (Task Selector State).
  631. Arguments:
  632. TssSegment - Supplies the segment selector in the GDT that describes the
  633. TSS.
  634. Return Value:
  635. None.
  636. --*/
  637. VOID
  638. ArStoreTr (
  639. PULONG TssSegment
  640. );
  641. /*++
  642. Routine Description:
  643. This routine retrieves the current TSS (Task Selector State) register.
  644. Arguments:
  645. TssSegment - Supplies a pointer where the current TSS segment register will
  646. be returned.
  647. Return Value:
  648. None.
  649. --*/
  650. VOID
  651. ArLoadIdtr (
  652. PVOID IdtBase
  653. );
  654. /*++
  655. Routine Description:
  656. This routine loads the given Interrupt Descriptor Table.
  657. Arguments:
  658. IdtBase - Supplies a pointer to the base of the IDT.
  659. Return Value:
  660. None.
  661. --*/
  662. VOID
  663. ArStoreIdtr (
  664. PTABLE_REGISTER IdtRegister
  665. );
  666. /*++
  667. Routine Description:
  668. This routine stores the interrupt descriptor table register into the given
  669. value.
  670. Arguments:
  671. IdtRegister - Supplies a pointer that will receive the value.
  672. Return Value:
  673. None.
  674. --*/
  675. VOID
  676. ArLoadGdtr (
  677. TABLE_REGISTER Gdt
  678. );
  679. /*++
  680. Routine Description:
  681. This routine loads a global descriptor table.
  682. Arguments:
  683. Gdt - Supplies a pointer to the Gdt pointer, which contains the base and
  684. limit for the GDT.
  685. Return Value:
  686. None.
  687. --*/
  688. VOID
  689. ArStoreGdtr (
  690. PTABLE_REGISTER GdtRegister
  691. );
  692. /*++
  693. Routine Description:
  694. This routine stores the GDT register into the given value.
  695. Arguments:
  696. GdtRegister - Supplies a pointer that will receive the value.
  697. Return Value:
  698. None.
  699. --*/
  700. PVOID
  701. ArGetFaultingAddress (
  702. );
  703. /*++
  704. Routine Description:
  705. This routine determines which address caused a page fault.
  706. Arguments:
  707. None.
  708. Return Value:
  709. Returns the faulting address.
  710. --*/
  711. VOID
  712. ArSetFaultingAddress (
  713. PVOID Value
  714. );
  715. /*++
  716. Routine Description:
  717. This routine sets the CR2 register.
  718. Arguments:
  719. Value - Supplies the value to set.
  720. Return Value:
  721. None.
  722. --*/
  723. ULONG
  724. ArGetCurrentPageDirectory (
  725. VOID
  726. );
  727. /*++
  728. Routine Description:
  729. This routine returns the active page directory.
  730. Arguments:
  731. None.
  732. Return Value:
  733. Returns the page directory currently in use by the system.
  734. --*/
  735. VOID
  736. ArSetCurrentPageDirectory (
  737. ULONG Value
  738. );
  739. /*++
  740. Routine Description:
  741. This routine sets the CR3 register.
  742. Arguments:
  743. Value - Supplies the value to set.
  744. Return Value:
  745. None.
  746. --*/
  747. VOID
  748. ArDoubleFaultHandlerAsm (
  749. );
  750. /*++
  751. Routine Description:
  752. This routine is entered via an IDT entry when a double fault exception
  753. occurs. Double faults are non-recoverable. This machine loops attempting
  754. to enter the debugger indefinitely.
  755. Arguments:
  756. None.
  757. Return Value:
  758. None, this routine does not return.
  759. --*/
  760. VOID
  761. ArProtectionFaultHandlerAsm (
  762. ULONG ReturnEip,
  763. ULONG ReturnCodeSelector,
  764. ULONG ReturnEflags
  765. );
  766. /*++
  767. Routine Description:
  768. This routine is called directly when a general protection fault occurs.
  769. It's job is to prepare the trap frame, call the appropriate handler, and
  770. then restore the trap frame.
  771. Arguments:
  772. ReturnEip - Supplies the address after the instruction that caused the trap.
  773. ReturnCodeSelector - Supplies the code selector the code that trapped was
  774. running under.
  775. ReturnEflags - Supplies the EFLAGS register immediately before the trap.
  776. Return Value:
  777. None.
  778. --*/
  779. VOID
  780. ArMathFaultHandlerAsm (
  781. ULONG ReturnEip,
  782. ULONG ReturnCodeSelector,
  783. ULONG ReturnEflags
  784. );
  785. /*++
  786. Routine Description:
  787. This routine is called directly when a x87 FPU fault occurs.
  788. Arguments:
  789. ReturnEip - Supplies the address after the instruction that caused the trap.
  790. ReturnCodeSelector - Supplies the code selector the code that trapped was
  791. running under.
  792. ReturnEflags - Supplies the EFLAGS register immediately before the trap.
  793. Return Value:
  794. None.
  795. --*/
  796. VOID
  797. ArTrapSystemCallHandlerAsm (
  798. ULONG ReturnEip,
  799. ULONG ReturnCodeSelector,
  800. ULONG ReturnEflags
  801. );
  802. /*++
  803. Routine Description:
  804. This routine is entered when the sysenter routine is entered with the TF
  805. flag set. It performs a normal save and sets the TF.
  806. Arguments:
  807. ReturnEip - Supplies the address after the instruction that caused the trap.
  808. ReturnCodeSelector - Supplies the code selector the code that trapped was
  809. running under.
  810. ReturnEflags - Supplies the EFLAGS register immediately before the trap.
  811. Return Value:
  812. None.
  813. --*/
  814. INTN
  815. ArSystemCallHandlerAsm (
  816. ULONG ReturnEip,
  817. ULONG ReturnCodeSelector,
  818. ULONG ReturnEflags
  819. );
  820. /*++
  821. Routine Description:
  822. This routine is entered via an IDT entry to service a user mode request.
  823. Ecx contains the system call number, and Edx contains the argument.
  824. Arguments:
  825. ReturnEip - Supplies the address after the instruction that caused the trap.
  826. ReturnCodeSelector - Supplies the code selector the code that trapped was
  827. running under.
  828. ReturnEflags - Supplies the EFLAGS register immediately before the trap.
  829. Return Value:
  830. STATUS_SUCCESS or positive integer on success.
  831. Error status code on failure.
  832. --*/
  833. INTN
  834. ArSysenterHandlerAsm (
  835. VOID
  836. );
  837. /*++
  838. Routine Description:
  839. This routine is executed when user mode invokes the SYSENTER instruction.
  840. Upon entry, CS, EIP, and ESP are set to predefined values set in MSRs.
  841. Arguments:
  842. None.
  843. Return Value:
  844. STATUS_SUCCESS or positive integer on success.
  845. Error status code on failure.
  846. --*/
  847. VOID
  848. ArCpuid (
  849. PULONG Eax,
  850. PULONG Ebx,
  851. PULONG Ecx,
  852. PULONG Edx
  853. );
  854. /*++
  855. Routine Description:
  856. This routine executes the CPUID instruction to get processor architecture
  857. information.
  858. Arguments:
  859. Eax - Supplies a pointer to the value that EAX should be set to when the
  860. CPUID instruction is executed. On output, contains the contents of
  861. EAX immediately after the CPUID instruction.
  862. Ebx - Supplies a pointer to the value that EBX should be set to when the
  863. CPUID instruction is executed. On output, contains the contents of
  864. EAX immediately after the CPUID instruction.
  865. Ecx - Supplies a pointer to the value that ECX should be set to when the
  866. CPUID instruction is executed. On output, contains the contents of
  867. EAX immediately after the CPUID instruction.
  868. Edx - Supplies a pointer to the value that EDX should be set to when the
  869. CPUID instruction is executed. On output, contains the contents of
  870. EAX immediately after the CPUID instruction.
  871. Return Value:
  872. None.
  873. --*/
  874. ULONG
  875. ArGetControlRegister0 (
  876. VOID
  877. );
  878. /*++
  879. Routine Description:
  880. This routine returns the current value of CR0.
  881. Arguments:
  882. None.
  883. Return Value:
  884. Returns CR0.
  885. --*/
  886. VOID
  887. ArSetControlRegister0 (
  888. ULONG Value
  889. );
  890. /*++
  891. Routine Description:
  892. This routine sets the CR0 register.
  893. Arguments:
  894. Value - Supplies the value to set.
  895. Return Value:
  896. None.
  897. --*/
  898. ULONG
  899. ArGetControlRegister4 (
  900. VOID
  901. );
  902. /*++
  903. Routine Description:
  904. This routine returns the current value of CR4.
  905. Arguments:
  906. None.
  907. Return Value:
  908. Returns CR4.
  909. --*/
  910. VOID
  911. ArSetControlRegister4 (
  912. ULONG Value
  913. );
  914. /*++
  915. Routine Description:
  916. This routine sets the CR4 register.
  917. Arguments:
  918. Value - Supplies the value to set.
  919. Return Value:
  920. None.
  921. --*/
  922. ULONG
  923. ArGetDebugRegister0 (
  924. VOID
  925. );
  926. /*++
  927. Routine Description:
  928. This routine returns the current value of DR0.
  929. Arguments:
  930. None.
  931. Return Value:
  932. Returns DR0.
  933. --*/
  934. VOID
  935. ArSetDebugRegister0 (
  936. ULONG Value
  937. );
  938. /*++
  939. Routine Description:
  940. This routine sets the DR0 register.
  941. Arguments:
  942. Value - Supplies the value to set.
  943. Return Value:
  944. None.
  945. --*/
  946. ULONG
  947. ArGetDebugRegister1 (
  948. VOID
  949. );
  950. /*++
  951. Routine Description:
  952. This routine returns the current value of DR1.
  953. Arguments:
  954. None.
  955. Return Value:
  956. Returns DR1.
  957. --*/
  958. VOID
  959. ArSetDebugRegister1 (
  960. ULONG Value
  961. );
  962. /*++
  963. Routine Description:
  964. This routine sets the DR1 register.
  965. Arguments:
  966. Value - Supplies the value to set.
  967. Return Value:
  968. None.
  969. --*/
  970. ULONG
  971. ArGetDebugRegister2 (
  972. VOID
  973. );
  974. /*++
  975. Routine Description:
  976. This routine returns the current value of DR2.
  977. Arguments:
  978. None.
  979. Return Value:
  980. Returns DR2.
  981. --*/
  982. VOID
  983. ArSetDebugRegister2 (
  984. ULONG Value
  985. );
  986. /*++
  987. Routine Description:
  988. This routine sets the DR2 register.
  989. Arguments:
  990. Value - Supplies the value to set.
  991. Return Value:
  992. None.
  993. --*/
  994. ULONG
  995. ArGetDebugRegister3 (
  996. VOID
  997. );
  998. /*++
  999. Routine Description:
  1000. This routine returns the current value of DR3.
  1001. Arguments:
  1002. None.
  1003. Return Value:
  1004. Returns DR3.
  1005. --*/
  1006. VOID
  1007. ArSetDebugRegister3 (
  1008. ULONG Value
  1009. );
  1010. /*++
  1011. Routine Description:
  1012. This routine sets the DR3 register.
  1013. Arguments:
  1014. Value - Supplies the value to set.
  1015. Return Value:
  1016. None.
  1017. --*/
  1018. ULONG
  1019. ArGetDebugRegister6 (
  1020. VOID
  1021. );
  1022. /*++
  1023. Routine Description:
  1024. This routine returns the current value of DR6.
  1025. Arguments:
  1026. None.
  1027. Return Value:
  1028. Returns DR6.
  1029. --*/
  1030. VOID
  1031. ArSetDebugRegister6 (
  1032. ULONG Value
  1033. );
  1034. /*++
  1035. Routine Description:
  1036. This routine sets the DR6 register.
  1037. Arguments:
  1038. Value - Supplies the value to set.
  1039. Return Value:
  1040. None.
  1041. --*/
  1042. ULONG
  1043. ArGetDebugRegister7 (
  1044. VOID
  1045. );
  1046. /*++
  1047. Routine Description:
  1048. This routine returns the current value of DR7.
  1049. Arguments:
  1050. None.
  1051. Return Value:
  1052. Returns DR7.
  1053. --*/
  1054. VOID
  1055. ArSetDebugRegister7 (
  1056. ULONG Value
  1057. );
  1058. /*++
  1059. Routine Description:
  1060. This routine sets the DR7 register.
  1061. Arguments:
  1062. Value - Supplies the value to set.
  1063. Return Value:
  1064. None.
  1065. --*/
  1066. VOID
  1067. ArFxSave (
  1068. PFPU_CONTEXT Buffer
  1069. );
  1070. /*++
  1071. Routine Description:
  1072. This routine saves the current x87 FPU, MMX, XMM, and MXCSR registers to a
  1073. 512 byte memory location.
  1074. Arguments:
  1075. Buffer - Supplies a pointer to the buffer where the information will be
  1076. saved. This buffer must be 16-byte aligned.
  1077. Return Value:
  1078. None.
  1079. --*/
  1080. VOID
  1081. ArFxRestore (
  1082. PFPU_CONTEXT Buffer
  1083. );
  1084. /*++
  1085. Routine Description:
  1086. This routine restores the current x87 FPU, MMX, XMM, and MXCSR registers
  1087. from a 512 byte memory location.
  1088. Arguments:
  1089. Buffer - Supplies a pointer to the buffer where the information will be
  1090. loaded from. This buffer must be 16-byte aligned.
  1091. Return Value:
  1092. None.
  1093. --*/
  1094. VOID
  1095. ArSaveX87State (
  1096. PFPU_CONTEXT Buffer
  1097. );
  1098. /*++
  1099. Routine Description:
  1100. This routine saves the current x87 FPU (floating point unit) state.
  1101. Arguments:
  1102. Buffer - Supplies a pointer to the buffer where the information will be
  1103. saved. This buffer must be 16-byte aligned.
  1104. Return Value:
  1105. None.
  1106. --*/
  1107. VOID
  1108. ArRestoreX87State (
  1109. PFPU_CONTEXT Buffer
  1110. );
  1111. /*++
  1112. Routine Description:
  1113. This routine restores the x87 FPU (floating point unit) state.
  1114. Arguments:
  1115. Buffer - Supplies a pointer to the buffer where the information will be
  1116. loaded from. This buffer must be 16-byte aligned.
  1117. Return Value:
  1118. None.
  1119. --*/
  1120. VOID
  1121. ArEnableFpu (
  1122. VOID
  1123. );
  1124. /*++
  1125. Routine Description:
  1126. This routine clears the TS bit of CR0, allowing access to the FPU.
  1127. Arguments:
  1128. None.
  1129. Return Value:
  1130. None.
  1131. --*/
  1132. VOID
  1133. ArDisableFpu (
  1134. VOID
  1135. );
  1136. /*++
  1137. Routine Description:
  1138. This routine sets the TS bit of CR0, disallowing access to the FPU.
  1139. Arguments:
  1140. None.
  1141. Return Value:
  1142. None.
  1143. --*/
  1144. VOID
  1145. ArInitializeFpu (
  1146. VOID
  1147. );
  1148. /*++
  1149. Routine Description:
  1150. This routine resets the FPU state.
  1151. Arguments:
  1152. None.
  1153. Return Value:
  1154. None.
  1155. --*/
  1156. ULONGLONG
  1157. ArReadTimeStampCounter (
  1158. VOID
  1159. );
  1160. /*++
  1161. Routine Description:
  1162. This routine reads the time stamp counter from the current processor. It
  1163. is essential that callers of this function understand that this returns
  1164. instruction cycles, which does not always translate directly into units
  1165. of time. For example, some processors halt the timestamp counter during
  1166. performance and CPU idle state transitions. In other cases, the timestamp
  1167. counters of all processors are not in sync, so as execution of a thread
  1168. bounces unpredictably from one core to another, different timelines may be
  1169. observed. Additionally, one must understand that this intrinsic is not a
  1170. serializing instruction to the hardware, so the processor may decide to
  1171. execute any number of instructions after this one before actually snapping
  1172. the timestamp counter. To all those who choose to continue to use this
  1173. primitive to measure time, you have been warned.
  1174. Arguments:
  1175. None.
  1176. Return Value:
  1177. Returns the current instruction cycle count since the processor was started.
  1178. --*/
  1179. ULONGLONG
  1180. ArReadMsr (
  1181. ULONG Msr
  1182. );
  1183. /*++
  1184. Routine Description:
  1185. This routine reads the requested Model Specific Register.
  1186. Arguments:
  1187. Msr - Supplies the MSR to read.
  1188. Return Value:
  1189. Returns the 64-bit MSR value.
  1190. --*/
  1191. VOID
  1192. ArWriteMsr (
  1193. ULONG Msr,
  1194. ULONGLONG Value
  1195. );
  1196. /*++
  1197. Routine Description:
  1198. This routine writes the requested Model Specific Register.
  1199. Arguments:
  1200. Msr - Supplies the MSR to write.
  1201. Value - Supplies the 64-bit value to write.
  1202. Return Value:
  1203. None.
  1204. --*/
  1205. VOID
  1206. ArReloadThreadSegment (
  1207. VOID
  1208. );
  1209. /*++
  1210. Routine Description:
  1211. This routine reloads the thread segment register.
  1212. Arguments:
  1213. None.
  1214. Return Value:
  1215. None.
  1216. --*/
  1217. KERNEL_API
  1218. VOID
  1219. ArMonitor (
  1220. PVOID Address,
  1221. UINTN Ecx,
  1222. UINTN Edx
  1223. );
  1224. /*++
  1225. Routine Description:
  1226. This routine arms the monitoring hardware in preparation for an mwait
  1227. instruction.
  1228. Arguments:
  1229. Address - Supplies the address pointer to monitor.
  1230. Ecx - Supplies the contents to load into the ECX (RCX in 64-bit) register
  1231. when executing the monitor instruction. These are defined as hints.
  1232. Edx - Supplies the contents to load into the EDX/RDX register. These are
  1233. also hints.
  1234. Return Value:
  1235. None.
  1236. --*/
  1237. KERNEL_API
  1238. VOID
  1239. ArMwait (
  1240. UINTN Eax,
  1241. UINTN Ecx
  1242. );
  1243. /*++
  1244. Routine Description:
  1245. This routine executes the mwait instruction, which is used to halt the
  1246. processor until a specified memory location is written to. It is also used
  1247. on Intel processors to enter C-states. A monitor instruction must have
  1248. been executed prior to this to set up the monitoring region.
  1249. Arguments:
  1250. Eax - Supplies the contents to load into EAX/RAX when executing the mwait
  1251. instruction. This is a set of hints, including which C-state to enter
  1252. on Intel processors.
  1253. Ecx - Supplies the contents to load into the ECX (RCX in 64-bit) register
  1254. when executing the mwait instruction. This is 1 when entering a C-state
  1255. with interrupts disabled to indicate that an interrupt should still
  1256. break out.
  1257. Return Value:
  1258. None.
  1259. --*/
  1260. KERNEL_API
  1261. VOID
  1262. ArIoReadAndHalt (
  1263. USHORT IoPort
  1264. );
  1265. /*++
  1266. Routine Description:
  1267. This routine performs a single 8-bit I/O port read and then halts the
  1268. processor until the next interrupt comes in. This routine should be called
  1269. with interrupts disabled, and will return with interrupts enabled.
  1270. Arguments:
  1271. IoPort - Supplies the I/O port to read from.
  1272. Return Value:
  1273. None.
  1274. --*/
  1275. VOID
  1276. ArGetKernelTssTrapFrame (
  1277. PTRAP_FRAME TrapFrame
  1278. );
  1279. /*++
  1280. Routine Description:
  1281. This routine converts the kernel TSS to a trap frame.
  1282. Arguments:
  1283. TrapFrame - Supplies a pointer where the filled out trap frame information
  1284. will be returned.
  1285. Return Value:
  1286. None.
  1287. --*/
  1288. VOID
  1289. ArSetKernelTssTrapFrame (
  1290. PTRAP_FRAME TrapFrame
  1291. );
  1292. /*++
  1293. Routine Description:
  1294. This routine converts writes the given trap frame into the kernel TSS.
  1295. Arguments:
  1296. TrapFrame - Supplies a pointer to the trap frame data to write.
  1297. Return Value:
  1298. None.
  1299. --*/
  1300. VOID
  1301. ArClearTssBusyBit (
  1302. USHORT TssSegment
  1303. );
  1304. /*++
  1305. Routine Description:
  1306. This routine clears the busy bit in the GDT for the given segment. It is
  1307. assumed this segment is used on the current processor.
  1308. Arguments:
  1309. TssSegment - Supplies the TSS segment for the busy bit to clear.
  1310. Return Value:
  1311. None.
  1312. --*/
  1313. VOID
  1314. ArpPageFaultHandlerAsm (
  1315. ULONG ReturnEip,
  1316. ULONG ReturnCodeSelector,
  1317. ULONG ReturnEflags
  1318. );
  1319. /*++
  1320. Routine Description:
  1321. This routine is called directly when a page fault occurs.
  1322. Arguments:
  1323. ReturnEip - Supplies the address after the instruction that caused the
  1324. fault.
  1325. ReturnCodeSelector - Supplies the code selector the code that faulted was
  1326. running under.
  1327. ReturnEflags - Supplies the EFLAGS register immediately before the fault.
  1328. Return Value:
  1329. None.
  1330. --*/
  1331. VOID
  1332. ArpCreateSegmentDescriptor (
  1333. PGDT_ENTRY GdtEntry,
  1334. PVOID Base,
  1335. ULONG Limit,
  1336. GDT_GRANULARITY Granularity,
  1337. GDT_SEGMENT_TYPE Access,
  1338. UCHAR PrivilegeLevel,
  1339. BOOL System
  1340. );
  1341. /*++
  1342. Routine Description:
  1343. This routine initializes a GDT entry given the parameters.
  1344. Arguments:
  1345. GdtEntry - Supplies a pointer to the GDT entry that will be initialized.
  1346. Base - Supplies the base address where this segment begins.
  1347. Limit - Supplies the size of the segment, either in bytes or kilobytes,
  1348. depending on the Granularity parameter.
  1349. Granularity - Supplies the granularity of the segment. Valid values are byte
  1350. granularity or kilobyte granularity.
  1351. Access - Supplies the access permissions on the segment.
  1352. PrivilegeLevel - Supplies the privilege level that this segment requires.
  1353. Valid values are 0 (most privileged, kernel) to 3 (user mode, least
  1354. privileged).
  1355. System - Supplies a flag indicating whether this is a system segment (TRUE)
  1356. or a code/data segment.
  1357. Return Value:
  1358. None.
  1359. --*/