sddwc.h 15 KB

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  1. /*++
  2. Copyright (c) 2015 Minoca Corp. All Rights Reserved
  3. Module Name:
  4. sddwc.h
  5. Abstract:
  6. This header contains definitions for the DesignWare SD Controller.
  7. Author:
  8. Chris Stevens 30-Jul-2015
  9. --*/
  10. //
  11. // ------------------------------------------------------------------- Includes
  12. //
  13. //
  14. // --------------------------------------------------------------------- Macros
  15. //
  16. //
  17. // ---------------------------------------------------------------- Definitions
  18. //
  19. //
  20. // Define the SD control register bits.
  21. //
  22. #define SD_DWC_CONTROL_USE_INTERNAL_DMAC (1 << 25)
  23. #define SD_DWC_CONTROL_ENABLE_OD_PULLUP (1 << 24)
  24. #define SD_DWC_CONTROL_CARD_VOLTAGE_B_MASK (0xF << 20)
  25. #define SD_DWC_CONTROL_CARD_VOLTAGE_B_SHIFT 20
  26. #define SD_DWC_CONTROL_CARD_VOLTAGE_A_MASK (0xF << 16)
  27. #define SD_DWC_CONTROL_CARD_VOLTAGE_A_SHIFT 16
  28. #define SD_DWC_CONTROL_CE_ATA_INTERRUPT_ENABLE (1 << 11)
  29. #define SD_DWC_CONTROL_SEND_AUTO_STOP_CCSD (1 << 10)
  30. #define SD_DWC_CONTROL_SEND_CCSD (1 << 9)
  31. #define SD_DWC_CONTROL_ABORT_READ_DATA (1 << 8)
  32. #define SD_DWC_CONTROL_SEND_IRQ_RESPONSE (1 << 7)
  33. #define SD_DWC_CONTROL_READ_WAIT (1 << 6)
  34. #define SD_DWC_CONTROL_DMA_ENABLE (1 << 5)
  35. #define SD_DWC_CONTROL_INTERRUPT_ENABLE (1 << 4)
  36. #define SD_DWC_CONTROL_DMA_RESET (1 << 2)
  37. #define SD_DWC_CONTROL_FIFO_RESET (1 << 1)
  38. #define SD_DWC_CONTROL_CONTROLLER_RESET (1 << 0)
  39. //
  40. // Define the SD power register bits.
  41. //
  42. #define SD_DWC_POWER_DISABLE (0 << 0)
  43. #define SD_DWC_POWER_ENABLE (1 << 0)
  44. //
  45. // Define the SD clock divider register bits.
  46. //
  47. #define SD_DWC_CLOCK_DIVIDER_3_MASK (0xFF << 24)
  48. #define SD_DWC_CLOCK_DIVIDER_3_SHIFT 24
  49. #define SD_DWC_CLOCK_DIVIDER_2_MASK (0xFF << 16)
  50. #define SD_DWC_CLOCK_DIVIDER_2_SHIFT 16
  51. #define SD_DWC_CLOCK_DIVIDER_1_MASK (0xFF << 8)
  52. #define SD_DWC_CLOCK_DIVIDER_1_SHIFT 8
  53. #define SD_DWC_CLOCK_DIVIDER_0_MASK (0xFF << 0)
  54. #define SD_DWC_CLOCK_DIVIDER_0_SHIFT 0
  55. #define SD_DWC_MAX_DIVISOR (0xFF * 2)
  56. //
  57. // Define the SD clock source register bits.
  58. //
  59. #define SD_DWC_CLOCK_SOURCE_DIVIDER_3 0x3
  60. #define SD_DWC_CLOCK_SOURCE_DIVIDER_2 0x2
  61. #define SD_DWC_CLOCK_SOURCE_DIVIDER_1 0x1
  62. #define SD_DWC_CLOCK_SOURCE_DIVIDER_0 0x0
  63. #define SD_DWC_CLOCK_SOURCE_DIVIDER_MASK (0x3 << 0)
  64. #define SD_DWC_CLOCK_SOURCE_DIVIDER_SHIFT 0
  65. //
  66. // Define the SD clock enable register bits.
  67. //
  68. #define SD_DWC_CLOCK_ENABLE_LOW_POWER (1 << 16)
  69. #define SD_DWC_CLOCK_ENABLE_ON (1 << 0)
  70. //
  71. // Define the SD clock timeout register bits.
  72. //
  73. #define SD_DWC_TIMEOUT_DATA_MASK (0xFFFFFF << 8)
  74. #define SD_DWC_TIMEOUT_DATA_SHIFT 8
  75. #define SD_DWC_TIMEOUT_RESPONSE_MASK (0xFF << 0)
  76. #define SD_DWC_TIMEOUT_RESPONSE_SHIFT 0
  77. #define SD_DWC_TIMEOUT_DEFAULT 0xFFFFFF40
  78. //
  79. // Define the SD card type register bits.
  80. //
  81. #define SD_DWC_CARD_TYPE_8_BIT_WIDTH (1 << 16)
  82. #define SD_DWC_CARD_TYPE_4_BIT_WIDTH (1 << 0)
  83. #define SD_DWC_CARD_TYPE_1_BIT_WIDTH (0 << 0)
  84. //
  85. // Define the SD block size register bits.
  86. //
  87. #define SD_DWC_BLOCK_SIZE_MASK (0xFFFF << 0)
  88. #define SD_DWC_BLOCK_SIZE_SHIFT 0
  89. #define SD_DWC_BLOCK_SIZE_MAX 0xFFFF
  90. //
  91. // Define the SD interrupt mask register bits.
  92. //
  93. #define SD_DWC_INTERRUPT_MASK_SDIO (1 << 24)
  94. #define SD_DWC_INTERRUPT_MASK_DATA_NO_BUSY (1 << 16)
  95. #define SD_DWC_INTERRUPT_MASK_ERROR_END_BIT (1 << 15)
  96. #define SD_DWC_INTERRUPT_MASK_AUTO_COMMAND_DONE (1 << 14)
  97. #define SD_DWC_INTERRUPT_MASK_ERROR_START_BIT (1 << 13)
  98. #define SD_DWC_INTERRUPT_MASK_ERROR_HARDWARE_LOCKED (1 << 12)
  99. #define SD_DWC_INTERRUPT_MASK_ERROR_FIFO_UNDERRUN (1 << 11)
  100. #define SD_DWC_INTERRUPT_MASK_ERROR_HOST_TIMEOUT (1 << 10)
  101. #define SD_DWC_INTERRUPT_MASK_VOLT_SWITCH (1 << 10)
  102. #define SD_DWC_INTERRUPT_MASK_ERROR_DATA_READ_TIMEOUT (1 << 9)
  103. #define SD_DWC_INTERRUPT_MASK_ERROR_RESPONSE_TIMEOUT (1 << 8)
  104. #define SD_DWC_INTERRUPT_MASK_ERROR_DATA_CRC (1 << 7)
  105. #define SD_DWC_INTERRUPT_MASK_ERROR_RESPONSE_CRC (1 << 6)
  106. #define SD_DWC_INTERRUPT_MASK_RECEIVE_FIFO_DATA_REQUEST (1 << 5)
  107. #define SD_DWC_INTERRUPT_MASK_TRANSMIT_FIFO_DATA_REQUEST (1 << 4)
  108. #define SD_DWC_INTERRUPT_MASK_DATA_TRANSFER_OVER (1 << 3)
  109. #define SD_DWC_INTERRUPT_MASK_COMMAND_DONE (1 << 2)
  110. #define SD_DWC_INTERRUPT_MASK_ERROR_RESPONSE (1 << 1)
  111. #define SD_DWC_INTERRUPT_MASK_CARD_DETECT (1 << 0)
  112. #define SD_DWC_INTERRUPT_ERROR_MASK \
  113. (SD_DWC_INTERRUPT_MASK_ERROR_END_BIT | \
  114. SD_DWC_INTERRUPT_MASK_ERROR_START_BIT | \
  115. SD_DWC_INTERRUPT_MASK_ERROR_DATA_READ_TIMEOUT | \
  116. SD_DWC_INTERRUPT_MASK_ERROR_RESPONSE_TIMEOUT | \
  117. SD_DWC_INTERRUPT_MASK_ERROR_DATA_CRC | \
  118. SD_DWC_INTERRUPT_MASK_ERROR_RESPONSE_CRC | \
  119. SD_DWC_INTERRUPT_MASK_ERROR_RESPONSE)
  120. #define SD_DWC_INTERRUPT_DEFAULT_MASK SD_DWC_INTERRUPT_MASK_CARD_DETECT
  121. //
  122. // Define the SD interrupt status register bits.
  123. //
  124. #define SD_DWC_INTERRUPT_STATUS_SDIO (1 << 24)
  125. #define SD_DWC_INTERRUPT_STATUS_DATA_NO_BUSY_DISABLE (1 << 16)
  126. #define SD_DWC_INTERRUPT_STATUS_ERROR_END_BIT (1 << 15)
  127. #define SD_DWC_INTERRUPT_STATUS_AUTO_COMMAND_DONE (1 << 14)
  128. #define SD_DWC_INTERRUPT_STATUS_ERROR_START_BIT (1 << 13)
  129. #define SD_DWC_INTERRUPT_STATUS_ERROR_HARDWARE_LOCKED (1 << 12)
  130. #define SD_DWC_INTERRUPT_STATUS_ERROR_FIFO_UNDERRUN (1 << 11)
  131. #define SD_DWC_INTERRUPT_STATUS_ERROR_HOST_TIMEOUT (1 << 10)
  132. #define SD_DWC_INTERRUPT_STATUS_VOLT_SWITCH (1 << 10)
  133. #define SD_DWC_INTERRUPT_STATUS_ERROR_DATA_READ_TIMEOUT (1 << 9)
  134. #define SD_DWC_INTERRUPT_STATUS_ERROR_RESPONSE_TIMEOUT (1 << 8)
  135. #define SD_DWC_INTERRUPT_STATUS_ERROR_DATA_CRC (1 << 7)
  136. #define SD_DWC_INTERRUPT_STATUS_ERROR_RESPONSE_CRC (1 << 6)
  137. #define SD_DWC_INTERRUPT_STATUS_RECEIVE_FIFO_DATA_REQUEST (1 << 5)
  138. #define SD_DWC_INTERRUPT_STATUS_TRANSMIT_FIFO_DATA_REQUEST (1 << 4)
  139. #define SD_DWC_INTERRUPT_STATUS_DATA_TRANSFER_OVER (1 << 3)
  140. #define SD_DWC_INTERRUPT_STATUS_COMMAND_DONE (1 << 2)
  141. #define SD_DWC_INTERRUPT_STATUS_ERROR_RESPONSE (1 << 1)
  142. #define SD_DWC_INTERRUPT_STATUS_CARD_DETECT (1 << 0)
  143. #define SD_DWC_INTERRUPT_STATUS_ALL_MASK 0xFFFFFFFF
  144. #define SD_DWC_INTERRUPT_STATUS_COMMAND_ERROR_MASK \
  145. (SD_DWC_INTERRUPT_STATUS_ERROR_RESPONSE | \
  146. SD_DWC_INTERRUPT_STATUS_ERROR_RESPONSE_CRC)
  147. #define SD_DWC_INTERRUPT_STATUS_DATA_ERROR_MASK \
  148. (SD_DWC_INTERRUPT_STATUS_ERROR_DATA_CRC | \
  149. SD_DWC_INTERRUPT_STATUS_ERROR_DATA_READ_TIMEOUT | \
  150. SD_DWC_INTERRUPT_STATUS_ERROR_HOST_TIMEOUT | \
  151. SD_DWC_INTERRUPT_STATUS_ERROR_START_BIT | \
  152. SD_DWC_INTERRUPT_STATUS_ERROR_END_BIT)
  153. //
  154. // Define the SD command register bits.
  155. //
  156. #define SD_DWC_COMMAND_START (1 << 31)
  157. #define SD_DWC_COMMAND_USE_HOLD_REGISTER (1 << 29)
  158. #define SD_DWC_COMMAND_VOLT_SWITCH (1 << 28)
  159. #define SD_DWC_COMMAND_BOOT_MODE (1 << 27)
  160. #define SD_DWC_COMMAND_DISABLE_BOOT (1 << 26)
  161. #define SD_DWC_COMMAND_EXPECT_BOOT_ACK (1 << 25)
  162. #define SD_DWC_COMMAND_ENABLE_BOOT (1 << 24)
  163. #define SD_DWC_COMMAND_CSS_EXPECTED (1 << 23)
  164. #define SD_DWC_COMMAND_READ_CE_ATA (1 << 22)
  165. #define SD_DWC_COMMAND_UPDATE_CLOCK_REGISTERS (1 << 21)
  166. #define SD_DWC_COMMAND_CARD_NUMBER_MASK (0x1F << 16)
  167. #define SD_DWC_COMMAND_CARD_NUMBER_SHIFT 16
  168. #define SD_DWC_COMMAND_SEND_INITIALIZATION (1 << 15)
  169. #define SD_DWC_COMMAND_STOP_ABORT (1 << 14)
  170. #define SD_DWC_COMMAND_WAIT_PREVIOUS_DATA_COMPLETE (1 << 13)
  171. #define SD_DWC_COMMAND_SEND_AUTO_STOP (1 << 12)
  172. #define SD_DWC_COMMAND_TRANSFER_MODE_BLOCK (0 << 11)
  173. #define SD_DWC_COMMAND_TRANSFER_MODE_STREAM (1 << 11)
  174. #define SD_DWC_COMMAND_READ (0 << 10)
  175. #define SD_DWC_COMMAND_WRITE (1 << 10)
  176. #define SD_DWC_COMMAND_DATA_EXPECTED (1 << 9)
  177. #define SD_DWC_COMMAND_CHECK_RESPONSE_CRC (1 << 8)
  178. #define SD_DWC_COMMAND_LONG_RESPONSE (1 << 7)
  179. #define SD_DWC_COMMAND_RESPONSE_EXPECTED (1 << 6)
  180. #define SD_DWC_COMMAND_INDEX_MASK (0x3F << 0)
  181. #define SD_DWC_COMMAND_INDEX_SHIFT 0
  182. //
  183. // Define the SD status register bits.
  184. //
  185. #define SD_DWC_STATUS_DMA_REQUEST (1 << 31)
  186. #define SD_DWC_STATUS_DMA_ACK (1 << 30)
  187. #define SD_DWC_STATUS_FIFO_COUNT_MASK (0x1FFF << 17)
  188. #define SD_DWC_STATUS_FIFO_COUNT_SHIFT 17
  189. #define SD_DWC_STATUS_RESPONSE_INDEX_MASK (0x3F << 11)
  190. #define SD_DWC_STATUS_RESPONSE_INDEX_SHIFT 11
  191. #define SD_DWC_STATUS_DATA_STATE_MACHINE_BUSY (1 << 10)
  192. #define SD_DWC_STATUS_DATA_BUSY (1 << 9)
  193. #define SD_DWC_STATUS_DATA_3_STATUS (1 << 8)
  194. #define SD_DWC_STATUS_COMMAND_FSM_STATE_MASK (0xF << 4)
  195. #define SD_DWC_STATUS_COMMAND_FSM_STATE_SHIFT 4
  196. #define SD_DWC_STATUS_FIFO_FULL (1 << 3)
  197. #define SD_DWC_STATUS_FIFO_EMPTY (1 << 2)
  198. #define SD_DWC_STATUS_FIFO_TRANSMIT_WATERMARK (1 << 1)
  199. #define SD_DWC_STATUS_FIFO_RECEIVE_WATERMARK (1 << 0)
  200. //
  201. // Define the SD FIFO threshold register bits.
  202. //
  203. #define SD_DWC_FIFO_THRESHOLD_DMA_MULTIPLE_TRANSACTION_SIZE_1 0
  204. #define SD_DWC_FIFO_THRESHOLD_DMA_MULTIPLE_TRANSACTION_SIZE_4 1
  205. #define SD_DWC_FIFO_THRESHOLD_DMA_MULTIPLE_TRANSACTION_SIZE_8 2
  206. #define SD_DWC_FIFO_THRESHOLD_DMA_MULTIPLE_TRANSACTION_SIZE_16 3
  207. #define SD_DWC_FIFO_THRESHOLD_DMA_MULTIPLE_TRANSACTION_SIZE_32 4
  208. #define SD_DWC_FIFO_THRESHOLD_DMA_MULTIPLE_TRANSACTION_SIZE_64 5
  209. #define SD_DWC_FIFO_THRESHOLD_DMA_MULTIPLE_TRANSACTION_SIZE_128 6
  210. #define SD_DWC_FIFO_THRESHOLD_DMA_MULTIPLE_TRANSACTION_SIZE_256 7
  211. #define SD_DWC_FIFO_THRESHOLD_DMA_MULTIPLE_TRANSACTION_SIZE_MASK (0x7 << 28)
  212. #define SD_DWC_FIFO_THRESHOLD_DMA_MULTIPLE_TRANSACTION_SIZE_SHIFT 28
  213. #define SD_DWC_FIFO_THRESHOLD_RECEIVE_WATERMARK_MASK (0xFFF << 16)
  214. #define SD_DWC_FIFO_THRESHOLD_RECEIVE_WATERMARK_SHIFT 16
  215. #define SD_DWC_FIFO_THRESHOLD_TRANSMIT_WATERMARK_MASK (0xFFF << 0)
  216. #define SD_DWC_FIFO_THRESHOLD_TRANSMIT_WATERMARK_SHIFT 0
  217. #define SD_DWC_FIFO_THRESHOLD_DEFAULT \
  218. ((SD_DWC_FIFO_THRESHOLD_DMA_MULTIPLE_TRANSACTION_SIZE_16 << \
  219. SD_DWC_FIFO_THRESHOLD_DMA_MULTIPLE_TRANSACTION_SIZE_SHIFT) | \
  220. ((((SD_DWC_FIFO_DEPTH / 2) - 1) << \
  221. SD_DWC_FIFO_THRESHOLD_RECEIVE_WATERMARK_SHIFT) & \
  222. SD_DWC_FIFO_THRESHOLD_RECEIVE_WATERMARK_MASK) | \
  223. (((SD_DWC_FIFO_DEPTH / 2) << \
  224. SD_DWC_FIFO_THRESHOLD_TRANSMIT_WATERMARK_SHIFT) & \
  225. SD_DWC_FIFO_THRESHOLD_TRANSMIT_WATERMARK_MASK))
  226. #define SD_DWC_FIFO_DEPTH 0x100
  227. //
  228. // Define the SD UHS register bits.
  229. //
  230. #define SD_DWC_UHS_DDR_MODE (1 << 16)
  231. #define SD_DWC_UHS_VOLTAGE_MASK (1 << 0)
  232. #define SD_DWC_UHS_VOLTAGE_3V3 (0 << 0)
  233. #define SD_DWC_UHS_VOLTAGE_1V8 (1 << 0)
  234. //
  235. // Define the SD reset register bits.
  236. //
  237. #define SD_DWC_RESET_ENABLE (1 << 0)
  238. //
  239. // Define the SD bus mode register bits.
  240. //
  241. #define SD_DWC_BUS_MODE_BURST_LENGTH_1 0
  242. #define SD_DWC_BUS_MODE_BURST_LENGTH_4 1
  243. #define SD_DWC_BUS_MODE_BURST_LENGTH_8 2
  244. #define SD_DWC_BUS_MODE_BURST_LENGTH_16 3
  245. #define SD_DWC_BUS_MODE_BURST_LENGTH_32 4
  246. #define SD_DWC_BUS_MODE_BURST_LENGTH_64 5
  247. #define SD_DWC_BUS_MODE_BURST_LENGTH_128 6
  248. #define SD_DWC_BUS_MODE_BURST_LENGTH_256 7
  249. #define SD_DWC_BUS_MODE_BURST_LENGTH_MASK (0x7 << 8)
  250. #define SD_DWC_BUS_MODE_BURST_LENGTH_SHIFT 8
  251. #define SD_DWC_BUS_MODE_IDMAC_ENABLE (1 << 7)
  252. #define SD_DWC_BUS_MODE_DESCRIPTOR_SKIP_LENGTH_MASK (0x1F << 2)
  253. #define SD_DWC_BUS_MODE_DESCRIPTOR_SKIP_LENGTH_SHIFT 2
  254. #define SD_DWC_BUS_MODE_FIXED_BURST (1 << 1)
  255. #define SD_DWC_BUS_MODE_INTERNAL_DMA_RESET (1 << 0)
  256. //
  257. // Define the DMA descriptor control and status bits.
  258. //
  259. #define SD_DWC_DMA_DESCRIPTOR_CONTROL_OWN (1 << 31)
  260. #define SD_DWC_DMA_DESCRIPTOR_CONTROL_CARD_ERROR_SUMMARY (1 << 30)
  261. #define SD_DWC_DMA_DESCRIPTOR_CONTROL_END_OF_RING (1 << 5)
  262. #define SD_DWC_DMA_DESCRIPTOR_CONTROL_SECOND_ADDRESS_CHAINED (1 << 4)
  263. #define SD_DWC_DMA_DESCRIPTOR_CONTROL_FIRST_DESCRIPTOR (1 << 3)
  264. #define SD_DWC_DMA_DESCRIPTOR_CONTROL_LAST_DESCRIPTOR (1 << 2)
  265. #define SD_DWC_DMA_DESCRIPTOR_CONTROL_DISABLE_INTERRUPT_ON_COMPLETION (1 << 1)
  266. //
  267. // Define the maximum buffer size for a DMA descriptor. Technically it is
  268. // 0x1FFF, but round down to the nearest page for better arithmetic.
  269. //
  270. #define SD_DWC_DMA_DESCRIPTOR_MAX_BUFFER_SIZE 0x1000
  271. //
  272. // Define card read threshold register bits.
  273. //
  274. #define SD_DWC_CARD_READ_THRESHOLD_ENABLE 0x00000001
  275. #define SD_DWC_CARD_READ_THRESHOLD_SIZE_SHIFT 16
  276. //
  277. // ------------------------------------------------------ Data Type Definitions
  278. //
  279. typedef enum _SD_DWC_REGISTER {
  280. SdDwcControl = 0x000,
  281. SdDwcPower = 0x004,
  282. SdDwcClockDivider = 0x008,
  283. SdDwcClockSource = 0x00C,
  284. SdDwcClockEnable = 0x010,
  285. SdDwcTimeout = 0x014,
  286. SdDwcCardType = 0x018,
  287. SdDwcBlockSize = 0x01C,
  288. SdDwcByteCount = 0x020,
  289. SdDwcInterruptMask = 0x024,
  290. SdDwcCommandArgument = 0x028,
  291. SdDwcCommand = 0x02C,
  292. SdDwcResponse0 = 0x030,
  293. SdDwcResponse1 = 0x034,
  294. SdDwcResponse2 = 0x038,
  295. SdDwcResponse3 = 0x03C,
  296. SdDwcMaskedInterruptStatus = 0x040,
  297. SdDwcInterruptStatus = 0x044,
  298. SdDwcStatus = 0x048,
  299. SdDwcFifoThreshold = 0x04C,
  300. SdDwcCardDetect = 0x050,
  301. SdDwcWriteProtect = 0x054,
  302. SdDwcTransferredCiuByteCount = 0x058,
  303. SdDwcTransferredBiuByteCount = 0x05C,
  304. SdDwcUhs = 0x074,
  305. SdDwcResetN = 0x078,
  306. SdDwcBusMode = 0x080,
  307. SdDwcPollDemand = 0x084,
  308. SdDwcDescriptorBaseAddress = 0x088,
  309. SdDwcCardThresholdControl = 0x100,
  310. SdDwcFifoBase = 0x200,
  311. } SD_DWC_REGISTER, *PSD_DWC_REGISTER;
  312. /*++
  313. Structure Description:
  314. This structure defines the DesignWare SD DMA descriptor.
  315. Members:
  316. Control - Stores control and status bits for the descriptor. See
  317. SD_DWC_DMA_DESCRIPTOR_CONTROL_* for definitions.
  318. Size - Stores the size of the buffer.
  319. Address - Stores the physical address of the data buffer to use for the DMA.
  320. NextDescriptor - Stores the physical address of the next DMA descriptor.
  321. --*/
  322. typedef struct _SD_DWC_DMA_DESCRIPTOR {
  323. ULONG Control;
  324. ULONG Size;
  325. ULONG Address;
  326. ULONG NextDescriptor;
  327. } PACKED SD_DWC_DMA_DESCRIPTOR, *PSD_DWC_DMA_DESCRIPTOR;
  328. //
  329. // -------------------------------------------------------------------- Globals
  330. //
  331. //
  332. // -------------------------------------------------------- Function Prototypes
  333. //