entry.S 2.6 KB

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  1. /*++
  2. Copyright (c) 2015 Minoca Corp. All Rights Reserved
  3. Module Name:
  4. entry.S
  5. Abstract:
  6. This module implements the initial entry point into the ARMv7 firmware. Its
  7. job is to do essential initialization and call the C main function.
  8. Author:
  9. Chris Stevens 6-Jul-2015
  10. Environment:
  11. MBR
  12. --*/
  13. ##
  14. ## ------------------------------------------------------------------- Includes
  15. ##
  16. #include <minoca/kernel/arm.inc>
  17. #include "smp.inc"
  18. ##
  19. ## ---------------------------------------------------------------- Definitions
  20. ##
  21. .equ STACK_SIZE, 0x4000
  22. ##
  23. ## ----------------------------------------------------------------------- Code
  24. ##
  25. ##
  26. ## .text specifies that this code belongs in the executable section. This is
  27. ## the only section in the MBR code, data also lives in the text section.
  28. ## .arm specifies that this code should be compiled in ARM mode.
  29. ##
  30. .text
  31. .arm
  32. ##
  33. ## .global allows this label to be visible to the linker. _start is the entry
  34. ## point to the MBR code, so it needs to be globally visible.
  35. ##
  36. .global _start
  37. ##
  38. ## This is the entry point for the ARM boot loader. It changes to SVC mode,
  39. ## sets up the initial stack, and jumps to the main loader.
  40. ##
  41. _start:
  42. ##
  43. ## Disable interrupts and switch to SVC mode.
  44. ##
  45. mov %r2, #(PSR_FLAG_IRQ | ARM_MODE_SVC)
  46. msr CPSR_c, %r2
  47. ##
  48. ## Flip some essential MMU bits allowing unaligned accesses.
  49. ##
  50. mrc p15, 0, %r0, %cr1, %cr0, 0
  51. bic %r0, %r0, #MMU_ALIGNMENT_FAULT_ENABLED
  52. orr %r0, %r0, #MMU_UNALIGNED_ACCESS_ENABLED
  53. mcr p15, 0, %r0, %cr1, %cr0, 0
  54. ##
  55. ## Perform initialization steps that must be taken on each core.
  56. ##
  57. RK32_SMP_INIT
  58. ##
  59. ## Zero out the BSS section.
  60. ##
  61. ldr %r1, =__bss_start__
  62. ldr %r2, =__bss_end__
  63. mov %r0, #0
  64. BssZeroLoop:
  65. str %r0, [%r1], #4
  66. cmp %r1, %r2
  67. blt BssZeroLoop
  68. ##
  69. ## The stack starts at the image base and works downwards.
  70. ##
  71. adr %r0, _start @ Get the current address for the stack top.
  72. bic %r0, %r0, #0xF00 @ Align the top of the stack to a page.
  73. bic %r0, %r0, #0x0FF @
  74. ldr %r1, =STACK_SIZE @ Get the stack size.
  75. mov %sp, %r0 @ Set the stack.
  76. mov %r11, #0 @ Zero the ARM frame pointer.
  77. mov %r7, #0 @ Zero out the Thumb frame pointer.
  78. mov %r2, %r7 @ Zero out another temporary register.
  79. push {%r2, %r7} @ Create an empty stack frame for debugging.
  80. blx EfiVeyronMain
  81. LoopForever:
  82. b LoopForever