archsup.S 4.8 KB

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  1. /*++
  2. Copyright (c) 2014 Minoca Corp. All Rights Reserved
  3. Module Name:
  4. archsup.S
  5. Abstract:
  6. This module implements ARMv6 processor architecture features not
  7. implementable in C.
  8. Author:
  9. Chris Stevens 2-Feb-2014
  10. Environment:
  11. Kernel mode
  12. --*/
  13. ##
  14. ## ------------------------------------------------------------------ Includes
  15. ##
  16. #include <minoca/kernel/arm.inc>
  17. ##
  18. ## --------------------------------------------------------------- Definitions
  19. ##
  20. ##
  21. ## ---------------------------------------------------------------------- Code
  22. ##
  23. ASSEMBLY_FILE_HEADER
  24. ##
  25. ## VOID
  26. ## ArCleanEntireCache (
  27. ## VOID
  28. ## )
  29. ##
  30. /*++
  31. Routine Description:
  32. This routine cleans the entire data cache.
  33. Arguments:
  34. None.
  35. Return Value:
  36. None.
  37. --*/
  38. FUNCTION ArCleanEntireCache
  39. mov %r1, #0
  40. mcr p15, 0, %r1, %cr7, %cr10, 0 @ Clean entire data cache.
  41. mcr p15, 0, %r1, %cr7, %cr10, 4 @ Data Synchronization barrier.
  42. bx %lr
  43. END_FUNCTION ArCleanEntireCache
  44. ##
  45. ## VOID
  46. ## ArCleanInvalidateEntireCache (
  47. ## VOID
  48. ## )
  49. ##
  50. /*++
  51. Routine Description:
  52. This routine cleans and invalidates the entire data cache.
  53. Arguments:
  54. None.
  55. Return Value:
  56. None.
  57. --*/
  58. FUNCTION ArCleanInvalidateEntireCache
  59. mov %r1, #0
  60. mcr p15, 0, %r1, %cr7, %cr14, 0 @ Clean/invalidate entire data cache.
  61. mcr p15, 0, %r1, %cr7, %cr10, 4 @ Data Synchronization barrier.
  62. bx %lr
  63. END_FUNCTION ArCleanInvalidateEntireCache
  64. ##
  65. ## ULONG
  66. ## ArGetMultiprocessorIdRegister (
  67. ## VOID
  68. ## )
  69. ##
  70. /*++
  71. Routine Description:
  72. This routine gets the Multiprocessor ID register (MPIDR).
  73. Arguments:
  74. None.
  75. Return Value:
  76. Returns the value of the MPIDR.
  77. --*/
  78. FUNCTION ArGetMultiprocessorIdRegister
  79. ##
  80. ## The MPIDR does not exist on ARMv6; return 0.
  81. ##
  82. mov %r0, #0
  83. bx %lr
  84. END_FUNCTION ArGetMultiprocessorIdRegister
  85. ##
  86. ## ULONG
  87. ## ArGetPerformanceControlRegister (
  88. ## VOID
  89. ## )
  90. ##
  91. /*++
  92. Routine Description:
  93. This routine retrieves the PMCR (Performance Monitor Control Register).
  94. Arguments:
  95. None.
  96. Return Value:
  97. Returns the value of the PMCR.
  98. --*/
  99. FUNCTION ArGetPerformanceControlRegister
  100. mrc p15, 0, %r0, %c15, %c12, 0 @ Get the PMCR.
  101. bx %lr @
  102. END_FUNCTION ArGetPerformanceControlRegister
  103. ##
  104. ## VOID
  105. ## ArSetPerformanceControlRegister (
  106. ## ULONG Value
  107. ## )
  108. ##
  109. /*++
  110. Routine Description:
  111. This routine sets the PMCR (Performance Monitor Control Register).
  112. Arguments:
  113. Value - Supplies the value to set in the PMCR.
  114. Return Value:
  115. None.
  116. --*/
  117. FUNCTION ArSetPerformanceControlRegister
  118. mcr p15, 0, %r0, %c15, %c12, 0 @ Set the PMCR.
  119. bx %lr @
  120. END_FUNCTION ArSetPerformanceControlRegister
  121. ##
  122. ## VOID
  123. ## ArClearPerformanceInterruptRegister (
  124. ## ULONG Value
  125. ## )
  126. ##
  127. /*++
  128. Routine Description:
  129. This routine sets the PMINTENCLR (Performance Monitor Interrupt Clear)
  130. register.
  131. Arguments:
  132. Value - Supplies the value to set in the PMINTENCLR.
  133. Return Value:
  134. None.
  135. --*/
  136. FUNCTION ArClearPerformanceInterruptRegister
  137. DEBUGGER_BREAK @ Debugger break.
  138. bx %lr @
  139. END_FUNCTION ArClearPerformanceInterruptRegister
  140. ##
  141. ## VOID
  142. ## ArSetPerformanceUserEnableRegister (
  143. ## ULONG Value
  144. ## )
  145. ##
  146. /*++
  147. Routine Description:
  148. This routine sets the PMUSERENR (Performance Monitor User Enable Register).
  149. Arguments:
  150. Value - Supplies the value to set in the PMUSERENR.
  151. Return Value:
  152. None.
  153. --*/
  154. FUNCTION ArSetPerformanceUserEnableRegister
  155. mcr p15, 0, %r0, %c15, %c9, 0 @ Set the PMUSERENR.
  156. bx %lr @
  157. END_FUNCTION ArSetPerformanceUserEnableRegister
  158. ##
  159. ## ULONG
  160. ## ArGetCycleCountRegister (
  161. ## VOID
  162. ## )
  163. ##
  164. /*++
  165. Routine Description:
  166. This routine retrieves the PMCCNTR (Performance Monitor Cycle Counter)
  167. register.
  168. Arguments:
  169. None.
  170. Return Value:
  171. Returns the value of the PMCCNTR.
  172. --*/
  173. FUNCTION ArGetCycleCountRegister
  174. mrc p15, 0, %r0, %c15, %c12, 1 @ Get the PMCCNTR register.
  175. bx %lr @
  176. END_FUNCTION ArGetCycleCountRegister
  177. ##
  178. ## VOID
  179. ## ArSetCycleCountRegister (
  180. ## ULONG Value
  181. ## )
  182. ##
  183. /*++
  184. Routine Description:
  185. This routine sets the PMCCNTR (Performance Monitor Cycle Counter) register.
  186. Arguments:
  187. Value - Supplies the value to set in the PMCCNTR register.
  188. Return Value:
  189. None.
  190. --*/
  191. FUNCTION ArSetCycleCountRegister
  192. mcr p15, 0, %r0, %c15, %c12, 1 @ Set the PMCCNTR register.
  193. bx %lr @
  194. END_FUNCTION ArSetCycleCountRegister
  195. ##
  196. ## --------------------------------------------------------- Internal Functions
  197. ##