Plan 9 from Bell Labs 2009-11-26

sys/src/9/kw/arch.c

@@ -151,6 +151,11 @@ userureg(Ureg* ureg)
 	return (ureg->psr & PsrMask) == PsrMusr;
 }
 
+/*
+ * atomic ops
+ * make sure that we don't drag in the C library versions
+ */
+
 long
 _xdec(long *p)
 {
@@ -172,6 +177,28 @@ _xinc(long *p)
 	splx(s);
 }
 
+int
+ainc(int *p)
+{
+	int s, v;
+
+	s = splhi();
+	v = ++*p;
+	splx(s);
+	return v;
+}
+
+int
+adec(int *p)
+{
+	int s, v;
+
+	s = splhi();
+	v = --*p;
+	splx(s);
+	return v;
+}
+
 int
 cas32(void* addr, u32int old, u32int new)
 {
@@ -181,6 +208,7 @@ cas32(void* addr, u32int old, u32int new)
 	if(r = (*(u32int*)addr == old))
 		*(u32int*)addr = new;
 	splx(s);
-
+	if (r)
+		coherence();
 	return r;
 }

sys/src/9/kw/archkw.c

@@ -191,8 +191,7 @@ archreset(void)
 	ulong clocks;
 	CpucsReg *cpu;
 
-	/* watchdog disabled */
-	TIMERREG->ctl = 0;
+	TIMERREG->ctl = 0;		/* watchdog disabled */
 
 	/* configure gpios */
 	((GpioReg*)AddrGpio0)->dataout = KWOEValLow;

sys/src/9/kw/clock.c

@@ -17,7 +17,9 @@ enum {
 static void
 clockintr(Ureg *ureg, void*)
 {
+	TIMERREG->timerwd = CLOCKFREQ;		/* reassure the watchdog */
 	m->fastclock++;
+	coherence();
 	timerintr(ureg, 0);
 	intrclear(Irqbridge, IRQcputimer0);
 }
@@ -65,7 +67,10 @@ clockinit(void)
 	coherence();
 	tmr->timer0  = Tcycles;
 	tmr->reload0 = Tcycles;
-	tmr->ctl = Tmr0enable | Tmr0periodic;
+	tmr->timerwd = CLOCKFREQ;
+	coherence();
+	tmr->ctl = Tmr0enable | Tmr0periodic | TmrWDenable;
+	CPUCSREG->rstout |= RstoutWatchdog;
 	coherence();
 }
 

sys/src/9/kw/io.h

@@ -316,6 +316,7 @@ enum {
 	IRQcputimer0,
 	IRQcputimer1,
 	IRQcputimerwd,
+	IRQaccesserr,
 };
 
 /*

sys/src/9/kw/l.s

@@ -56,6 +56,7 @@ _main:
 
 	/* disable l2 cache.  do this while l1 caches are off */
 	MRC	CpSC, CpL2, R1, C(CpTESTCFG), C(CpTCl2cfg), CpTCl2conf
+	/* disabling write allocation is probably for cortex-a8 errata 460075 */
 	BIC	$(1<<22 | 1<<28 | 1<<29), R1 /* l2 off, no wr alloc, no streaming */
 	MCR	CpSC, CpL2, R1, C(CpTESTCFG), C(CpTCl2cfg), CpTCl2conf
 	BARRIERS

sys/src/9/kw/trap.c

@@ -13,7 +13,8 @@
 #include "arm.h"
 
 enum {
-	Ntimevec = 20			/* # of time buckets for each intr */
+	Ntimevec = 20,			/* # of time buckets for each intr */
+	Nvecs = 256,
 };
 
 extern int notify(Ureg*);
@@ -33,7 +34,7 @@ static Vctl* vctl[32];
 
 uvlong ninterrupt;
 uvlong ninterruptticks;
-ulong intrtimes[256][Ntimevec];
+ulong intrtimes[Nvecs][Ntimevec];
 
 typedef struct Handler Handler;
 struct Handler {
@@ -85,6 +86,7 @@ intrtime(Mach*, int vno)
 	diff /= (m->cpuhz/1000000)*100;		/* quantum = 100µsec */
 	if(diff >= Ntimevec)
 		diff = Ntimevec-1;
+	assert(vno >= 0 && vno < Nvecs);
 	intrtimes[vno][diff]++;
 }
 
@@ -185,6 +187,7 @@ intrs(Ureg *ur, int sort)
 	Handler *h;
 	Irq irq;
 
+	assert(sort >= 0 && sort < nelem(irqs));
 	irq = irqs[sort];
 	ibits = *irq.irq;
 	ibits &= *irq.irqmask;
@@ -262,6 +265,9 @@ trapinit(void)
 
 	intrenable(Irqlo, IRQ0hisum, intrhi, nil, "hi");
 	intrenable(Irqlo, IRQ0bridge, intrbridge, nil, "bridge");
+
+	/* enable watchdog & access-error interrupts */
+	cpu->irqmask = 1<<IRQcputimerwd | 1<<IRQaccesserr;
 }
 
 static char *trapnames[PsrMask+1] = {