Plan 9 from Bell Labs 2010-04-11

sys/src/9/kw/arm.h

@@ -109,6 +109,9 @@
 
 /*
  * CpTESTCFG Secondary (CRm) registers and opcode2 fields; sheeva only.
+ * opcode1 == CpL2 (1).  L2 cache operations block the CPU until finished.
+ * Specifically, write-back (clean) blocks until all dirty lines have been
+ * drained from the L2 buffers.
  */
 #define CpTCl2cfg	1
 #define CpTCl2flush	9			/* cpu blocks until flush done */
@@ -156,18 +159,18 @@
 
 /*
  * MMU page table entries.
- * Impl (0x10) bit is implementation-defined and is mandatory on pre-v7 arms.
+ * Mbo (0x10) bit is implementation-defined and mandatory on some pre-v7 arms.
  */
-#define Impl		0x10			/* earlier arms */
+#define Mbo		0x10			/* must be 1 on earlier arms */
 #define Fault		0x00000000		/* L[12] pte: unmapped */
 
-#define Coarse		(Impl|1)		/* L1 */
-#define Section		(Impl|2)		/* L1 1MB */
-#define Fine		(Impl|3)		/* L1 */
+#define Coarse		(Mbo|1)			/* L1 */
+#define Section		(Mbo|2)			/* L1 1MB */
+#define Fine		(Mbo|3)			/* L1 */
 
 #define Large		0x00000001u		/* L2 64KB */
 #define Small		0x00000002u		/* L2 4KB */
-#define Tiny		0x00000003u		/* L2 1KB */
+#define Tiny		0x00000003u		/* L2 1KB, deprecated */
 #define Buffered	0x00000004u		/* L[12]: write-back not -thru */
 #define Cached		0x00000008u		/* L[12] */
 
@@ -184,4 +187,4 @@
 #define L2AP(ap) (AP(3, (ap))|AP(2, (ap))|AP(1, (ap))|AP(0, (ap))) /* pre-armv7 */
 #define DAC(n, v) F((v), (n)*2, 2)
 
-#define HVECTORS	0xffff0000		/* physical addr of vectors */
+#define HVECTORS	0xffff0000		/* addr of vectors */

sys/src/9/kw/clock.c

@@ -16,6 +16,7 @@
 
 enum {
 	Tcycles		= CLOCKFREQ / HZ,	/* cycles per clock tick */
+	Dogperiod	= 5 * CLOCKFREQ,	// TODO tune
 	MaxPeriod	= Tcycles,
 	MinPeriod	= MaxPeriod / 100,
 
@@ -48,7 +49,7 @@ clockintr(Ureg *ureg, void *arg)
 {
 	TimerReg *tmr = arg;
 
-	tmr->timerwd = CLOCKFREQ;		/* reassure the watchdog */
+	tmr->timerwd = Dogperiod;		/* reassure the watchdog */
 	ticks++;
 	coherence();
 	timerintr(ureg, 0);
@@ -110,7 +111,7 @@ clockinit(void)
 	clockshutdown();
 	tmr->reload0 = tmr->timer0 = Tcycles;	/* tick clock */
 	tmr->reload1 = tmr->timer1 = ~0;	/* cycle clock */
-	tmr->timerwd = CLOCKFREQ;		/* watch dog timer */
+	tmr->timerwd = Dogperiod;		/* watch dog timer */
 	coherence();
 	tmr->ctl = Tmr0enable | Tmr1enable | Tmr1periodic | TmrWDenable;
 	CPUCSREG->rstout |= RstoutWatchdog;

sys/src/9/kw/io.h

@@ -390,7 +390,7 @@ enum {
 	/* l2cfg bits */
 	L2ecc		= 1<<2,
 	L2exists	= 1<<3,		/* l2 cache doesn't ignore cpu */
-	L2writethru	= 1<<4,		/* else write-back */
+	L2writethru	= 1<<4,		/* always WT, else see PTE C & B */
 };
 
 enum {

sys/src/9/kw/mem.h

@@ -127,6 +127,7 @@
  * Physical machine information from here on.
  */
 #define PHYSDRAM	0
+/* from 0x80000000 up is uncached by L2 (see archkw.c) */
 #define PHYSCESASRAM	0xc8010000
 #define PHYSNAND	0xd8000000
 #define FLASHSIZE	(128*MiB)

sys/src/9/kw/usbehci.c

@@ -3352,7 +3352,7 @@ ehcireset(Ctlr *ctlr)
 	 * AMP_2_0 = 4 for 6281-A0 (but 3 for A1).
 	 * also set REG_EXT_FS_RCALL_EN | REG_RCAL_START.
 	 */
-	kw->phytxctl = v | 1 << 26 | 1 << 12 | 4;
+	kw->phytxctl = v | 1 << 26 | 1 << 12 | 4;	// TODO
 	coherence();
 	microdelay(100);
 	kw->phytxctl &= ~(1 << 12);
@@ -3361,7 +3361,7 @@ ehcireset(Ctlr *ctlr)
 	kw->phyrxctl = v | 1 << 2 | 8 << 4;
 
 	v = kw->phyivref & ~(3 << 8);		/* TXVDD12 */
-	kw->phyivref = v | 1 << 8;		/* 1 for 6281-A0; 3 for A1 */
+	kw->phyivref = v | 1 << 8;		/* TODO: 1 for 6281-A0; 3 for A1 */
 
 	coherence();