Browse Source

Plan 9 from Bell Labs 2012-07-07

David du Colombier 7 years ago
parent
commit
249ab867b7

+ 2 - 2
sys/man/8/mkflashfs

@@ -1,6 +1,6 @@
 .TH MKFLASHFS 8
 .SH NAME
-mkflashfs \- make a journalling file system for flash memory
+mkflashfs - make a journalling file system for flash memory
 .SH SYNOPSIS
 .B aux/mkflashfs
 [
@@ -32,7 +32,7 @@ to contain exactly
 .I nsect
 sectors.
 .SH SOURCE
-.B /sys/src/cmd/aux/flashfs/mkflashfs.c
+.B /sys/src/cmd/aux/flashfs
 .SH "SEE ALSO"
 .IR flashfs (4),
 .IR paqfs (4)

+ 33 - 18
sys/src/9/bitsy/fpiarm.c

@@ -4,16 +4,16 @@
  * all arithmetic is done in double precision.
  * the FP trap status isn't updated.
  */
-#include	<u.h>
+#include	"u.h"
 #include	"../port/lib.h"
 #include	"mem.h"
 #include	"dat.h"
 #include	"fns.h"
-#include	"io.h"
 
-#include	<ureg.h>
+#include	"ureg.h"
 
-#include "fpi.h"
+#include	"arm.h"
+#include	"fpi.h"
 
 /* undef this if correct kernel r13 isn't in Ureg;
  * check calculation in fpiarm below
@@ -44,7 +44,9 @@ enum {
 	REGPC = 15,
 };
 
-int	fpemudebug = 0;
+enum {
+	fpemudebug = 0,
+};
 
 #undef OFR
 #define	OFR(X)	((ulong)&((Ureg*)0)->X)
@@ -338,10 +340,12 @@ fpemu(ulong pc, ulong op, Ureg *ur, FPsave *ufp)
 			fn = &FR(ufp, rn);
 			if(op & (1<<3)){
 				fm = &fpconst[op&7];
-				tag = 'C';
+				if(fpemudebug)
+					tag = 'C';
 			}else{
 				fm = &FR(ufp, op&7);
-				tag = 'F';
+				if(fpemudebug)
+					tag = 'F';
 			}
 			switch((op>>21)&7){
 			default:
@@ -360,7 +364,8 @@ fpemu(ulong pc, ulong op, Ureg *ur, FPsave *ufp)
 				break;
 			}
 			if(fpemudebug)
-				print("CMPF	%c%d,F%ld =%lux\n", tag, rn, op&7, ur->psr>>28);
+				print("CMPF	%c%d,F%ld =%#lux\n",
+					tag, rn, op&7, ur->psr>>28);
 			return;
 		}
 
@@ -415,10 +420,12 @@ fpemu(ulong pc, ulong op, Ureg *ur, FPsave *ufp)
 
 	if(op & (1<<3)){	/* constant */
 		fm = &fpconst[op&7];
-		tag = 'C';
+		if(fpemudebug)
+			tag = 'C';
 	}else{
 		fm = &FR(ufp, op&7);
-		tag = 'F';
+		if(fpemudebug)
+			tag = 'F';
 	}
 	rd = (op>>12)&7;
 	o = (op>>20)&0xF;
@@ -481,6 +488,14 @@ ldrex(ulong pc, ulong op, Ureg *ur)
 			op>>12 & 0x7, op>>16 & 0x7, addr, rp[op>>12 & 0x7]);
 }
 
+void
+clrex(ulong, ulong, Ureg *)
+{
+	ldrexvalid = 0;
+	if(fpemudebug)
+		print("clrex");
+}
+
 void
 strex(ulong pc, ulong op, Ureg *ur)
 {
@@ -516,11 +531,11 @@ struct {
 } specialopc[] = {
 	{ 0x01900f9f, 0x0ff00fff, ldrex },
 	{ 0x01800f90, 0x0ff00ff0, strex },
+	{ 0xf57ff01f, 0xffffffff, clrex },
 	{ 0x0ed00100, 0x0ef08100, casemu },
 	{ 0x00000000, 0x00000000, nil }
 };
 
-
 /*
  * returns the number of FP instructions emulated
  */
@@ -531,13 +546,13 @@ fpiarm(Ureg *ur)
 	FPsave *ufp;
 	int i, n;
 
-	if (up == nil)
+	if(up == nil)
 		panic("fpiarm not in a process");
 	ufp = &up->fpsave;
-		/* because all the state is in the proc structure,
-		 * it need not be saved/restored
-		 */
-	if(up->fpstate != FPactive) {
+	/* because all the state is in the proc structure,
+	 * it need not be saved/restored
+	 */
+	if(up->fpstate != FPactive){
 //		assert(sizeof(Internal) == sizeof(ufp->regs[0]));
 		up->fpstate = FPactive;
 		ufp->control = 0;
@@ -546,10 +561,10 @@ fpiarm(Ureg *ur)
 			FR(ufp, n) = fpconst[0];
 	}
 	for(n=0; ;n++){
-		if(fpemudebug)
-			print("0x%8.8lux ", ur->pc);
 		validaddr(ur->pc, 4, 0);
 		op = *(ulong*)(ur->pc);
+		if(fpemudebug)
+			print("%#lux: %#8.8lux ", ur->pc, op);
 		o = (op>>24) & 0xF;
 		if(condok(ur->psr, op>>28)){
 			for(i = 0; specialopc[i].f; i++)

+ 1 - 1
sys/src/9/bitsy/mmu.c

@@ -310,7 +310,7 @@ mmu_kaddr(ulong pa)
 	/* try the easy stuff first (the first case is true most of the time) */
 	if(pa >= PHYSDRAM0 && pa <= PHYSDRAM0+(DRAMTOP-DRAMZERO))
 		return DRAMZERO+(pa-PHYSDRAM0);
-	if(pa >= PHYSFLASH0 && pa <= PHYSFLASH0+(FLASHTOP-FLASHZERO))
+	if(/* pa >= PHYSFLASH0 && */ pa <= PHYSFLASH0+(FLASHTOP-FLASHZERO))
 		return FLASHZERO+(pa-PHYSFLASH0);
 	if(pa >= PHYSNULL0 && pa <= PHYSNULL0+(NULLTOP-NULLZERO))
 		return NULLZERO+(pa-PHYSNULL0);

+ 9 - 0
sys/src/9/kw/fpiarm.c

@@ -488,6 +488,14 @@ ldrex(ulong pc, ulong op, Ureg *ur)
 			op>>12 & 0x7, op>>16 & 0x7, addr, rp[op>>12 & 0x7]);
 }
 
+void
+clrex(ulong, ulong, Ureg *)
+{
+	ldrexvalid = 0;
+	if(fpemudebug)
+		print("clrex");
+}
+
 void
 strex(ulong pc, ulong op, Ureg *ur)
 {
@@ -523,6 +531,7 @@ struct {
 } specialopc[] = {
 	{ 0x01900f9f, 0x0ff00fff, ldrex },
 	{ 0x01800f90, 0x0ff00ff0, strex },
+	{ 0xf57ff01f, 0xffffffff, clrex },
 	{ 0x0ed00100, 0x0ef08100, casemu },
 	{ 0x00000000, 0x00000000, nil }
 };

+ 9 - 0
sys/src/9/omap/fpiarm.c

@@ -488,6 +488,14 @@ ldrex(ulong pc, ulong op, Ureg *ur)
 			op>>12 & 0x7, op>>16 & 0x7, addr, rp[op>>12 & 0x7]);
 }
 
+void
+clrex(ulong, ulong, Ureg *)
+{
+	ldrexvalid = 0;
+	if(fpemudebug)
+		print("clrex");
+}
+
 void
 strex(ulong pc, ulong op, Ureg *ur)
 {
@@ -523,6 +531,7 @@ struct {
 } specialopc[] = {
 	{ 0x01900f9f, 0x0ff00fff, ldrex },
 	{ 0x01800f90, 0x0ff00ff0, strex },
+	{ 0xf57ff01f, 0xffffffff, clrex },
 	{ 0x0ed00100, 0x0ef08100, casemu },
 	{ 0x00000000, 0x00000000, nil }
 };

+ 2 - 4
sys/src/9/teg2/atom.s

@@ -4,10 +4,8 @@
  * int cas(ulong *p, ulong ov, ulong nv);
  */
 
-TEXT	cas+0(SB),0,$12		/* r0 holds p */
-	B	_casp		/* must not fall through; would push LR again */
-TEXT	casp+0(SB),0,$12	/* r0 holds p */
-_casp:
+TEXT	cas+0(SB),0,$0		/* r0 holds p */
+TEXT	casp+0(SB),0,$0		/* r0 holds p */
 	MOVW	ov+4(FP), R1
 	MOVW	nv+8(FP), R2
 	BARRIERS

+ 2 - 4
sys/src/libc/arm/atom.s

@@ -7,10 +7,8 @@
 /* `The order of operands is from left to right in dataflow order' - asm man */
 #define	STREX(v,a,r)	WORD	$(0xe<<28|0x01800f90 | (a)<<16 | (r)<<12 | (v)<<0)
 
-TEXT	cas+0(SB),0,$12		/* r0 holds p */
-	B	_casp		/* must not fall through; would push LR again */
-TEXT	casp+0(SB),0,$12	/* r0 holds p */
-_casp:
+TEXT	cas+0(SB),0,$0		/* r0 holds p */
+TEXT	casp+0(SB),0,$0		/* r0 holds p */
 	MOVW	ov+4(FP), R1
 	MOVW	nv+8(FP), R2
 spincas: