Plan 9 from Bell Labs 2012-05-01

cfg/pxe/example-kw

@@ -6,3 +6,4 @@ nobootprompt=tcp
 
 # aoeif=ether0
 # aoedev=e!#æ/aoe/1.0
+readparts=1

cfg/pxe/example-omap

@@ -12,6 +12,7 @@ nvram=/boot/nvram
 nvroff=0
 nvrlen=512
 nobootprompt=tcp
+readparts=1
 
 # aoeif=ether0
 # aoedev=e!#æ/aoe/1.0

cfg/pxe/example-pxa

@@ -3,6 +3,7 @@ nvram=/boot/nvram
 nvroff=0
 nvrlen=512
 nobootprompt=tcp
+readparts=1
 
 # aoeif=ether0
 # aoedev=e!#æ/aoe/1.0

sys/src/9/kw/arm.s

@@ -20,7 +20,7 @@
 #define PTEIO		(Dom0|L1AP(Krw)|Section)
 
 /* wave at the user; clobbers R1 & R7; needs R12 (SB) set */
-#define WAVE(c) \
+#define PUTC(c) \
 	ISB; \
 	MOVW	$PHYSCONS, R7; \
 	MOVW	$(c), R1; \

sys/src/9/kw/l.s

@@ -76,7 +76,7 @@ _dwbinv1:
 	BNE	_dwbinv1
 	BARRIERS
 
-WAVE('\r')
+PUTC('\r')
 	/* clear Mach */
 	MOVW	$PADDR(MACHADDR), R4		/* address of Mach */
 _machZ:
@@ -90,7 +90,7 @@ _machZ:
 	 */
 
 	/* clear all PTEs first, to provide a default */
-WAVE('\n')
+PUTC('\n')
 	MOVW	$PADDR(L1+L1X(0)), R4		/* address of PTE for 0 */
 _ptenv0:
 	ZEROPTE()
@@ -135,7 +135,7 @@ _ptekrw:					/* set PTEs for 512MiB */
 	 */
 	MOVW	$(PHYSDRAM | (128*1024*1024)), R13
 
-WAVE('P')
+PUTC('P')
 	/* set the domain access control */
 	MOVW	$Client, R0
 	BL	dacput(SB)
@@ -148,12 +148,12 @@ WAVE('P')
 	BL	pidput(SB)		/* paranoia */
 
 	/* the little dance to turn the MMU & caches on */
-WAVE('l')
+PUTC('l')
 	BL	cacheuwbinv(SB)
 	BL	mmuinvalidate(SB)
 	BL	mmuenable(SB)
 
-WAVE('a')
+PUTC('a')
 	/* warp the PC into the virtual map */
 	MOVW	$KZERO, R0
 	BL	_r15warp(SB)
@@ -174,7 +174,7 @@ WAVE('a')
 
 	BL	cacheuwbinv(SB)
 
-WAVE('n')
+PUTC('n')
 	/* undo double map of 0, KZERO */
 	MOVW	$PADDR(L1+L1X(0)), R4		/* address of PTE for 0 */
 	MOVW	$0, R0
@@ -190,7 +190,7 @@ _ptudbl:
 	MCR	CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
 	BARRIERS
 
-WAVE(' ')
+PUTC(' ')
 	/* pass Mach to main and set up the stack */
 	MOVW	$(MACHADDR), R0			/* Mach */
 	MOVW	R0, R13
@@ -212,7 +212,7 @@ TEXT _reset(SB), 1, $-4
 	BIC	$(CpCwb|CpCicache|CpCdcache|CpCalign), R0
 	MCR     CpSC, 0, R0, C(CpCONTROL), C(0)
 	BARRIERS
-WAVE('R')
+PUTC('R')
 
 	/* redo double map of 0, KZERO */
 	MOVW	$(L1+L1X(0)), R4		/* address of PTE for 0 */
@@ -228,7 +228,7 @@ _ptrdbl:
 	BNE	_ptrdbl
 
 	BARRIERS
-WAVE('e')
+PUTC('e')
 	MOVW	$0, R0
 	MCR	CpSC, 0, R0, C(CpTLB), C(CpTLBinvd), CpTLBinv
 	MCR	CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
@@ -246,19 +246,19 @@ WAVE('e')
 	BL	mmuinvalidate(SB)
 	BL	mmudisable(SB)
 
-WAVE('s')
+PUTC('s')
 	/* set new reset vector */
 	MOVW	$0, R2
 	MOVW	$0xe59ff018, R3			/* MOVW 0x18(R15), R15 */
 	MOVW	R3, (R2)
-WAVE('e')
+PUTC('e')
 
 	MOVW	$PHYSBOOTROM, R3
 	MOVW	R3, 0x20(R2)			/* where $0xe59ff018 jumps to */
 	BARRIERS
-WAVE('t')
-WAVE('\r')
-WAVE('\n')
+PUTC('t')
+PUTC('\r')
+PUTC('\n')
 
 	/* ...and jump to it */
 	MOVW	R2, R15				/* software reboot */

sys/src/9/kw/rebootcode.s

@@ -21,12 +21,12 @@ TEXT	main(SB), 1, $-4
 	MOVW	p2+4(FP), R9		/* source */
 	MOVW	n+8(FP), R10		/* byte count */
 
-WAVE('R')
+PUTC('R')
 	BL	cachesoff(SB)
 	/* now back in 29- or 26-bit addressing, mainly for SB */
 
 	/* turn the MMU off */
-WAVE('e')
+PUTC('e')
 	MOVW	$KSEGM, R7
 	MOVW	$PHYSDRAM, R0
 	BL	_r15warp(SB)
@@ -35,12 +35,12 @@ WAVE('e')
 	BIC	R7, R13			/* SP */
 	/* don't care about R14 */
 
-WAVE('b')
+PUTC('b')
 	BL	mmuinvalidate(SB)
-WAVE('o')
+PUTC('o')
 	BL	mmudisable(SB)
 
-WAVE('o')
+PUTC('o')
 	MOVW	R9, R4			/* restore regs across function calls */
 	MOVW	R10, R5
 	MOVW	R8, R6
@@ -55,7 +55,7 @@ WAVE('o')
 	MOVW	R6, 44(SP)		/* save dest/entry */
 	MOVW	R5, 40(SP)		/* save count */
 
-WAVE('t')
+PUTC('t')
 
 	MOVW	R6, 0(SP)
 	MOVW	R6, 4(SP)		/* push dest */
@@ -66,15 +66,15 @@ WAVE('t')
 
 	MOVW	44(SP), R6		/* restore R6 (dest/entry) */
 	MOVW	40(SP), R5		/* restore R5 (count) */
-WAVE('-')
+PUTC('-')
 	/*
 	 * flush caches
 	 */
 	BL	cacheuwbinv(SB)
 
-WAVE('>')
-WAVE('\r');
-WAVE('\n');
+PUTC('>')
+PUTC('\r');
+PUTC('\n');
 /*
  * jump to kernel entry point.  Note the true kernel entry point is
  * the virtual address KZERO|R6, but this must wait until

sys/src/9/omap/arm.s

@@ -30,7 +30,7 @@ label: \
 	BNE	label
 
 /* wave at the user; clobbers R0, R1 & R6; needs R12 (SB) set */
-#define WAVE(c) \
+#define PUTC(c) \
 	BARRIERS; \
 	MOVW	$(c), R1; \
 	MOVW	$PHYSCONS, R6; \

sys/src/9/omap/cache.v7.s

@@ -202,7 +202,7 @@ inner:
 	RET
 
 buggery:
-WAVE('?')
+PUTC('?')
 	MOVW	PC, R0
 //	B	pczeroseg(SB)
 	RET

sys/src/9/omap/l.s

@@ -35,9 +35,9 @@ TEXT _start(SB), 1, $-4
 	BARRIERS
 
 	DELAY(printloopret, 1)
-WAVE('\r')
+PUTC('\r')
 	DELAY(printloopnl, 1)
-WAVE('\n')
+PUTC('\n')
 	/*
 	 * work around errata
 	 */
@@ -64,7 +64,7 @@ WAVE('\n')
 	ISB
 #endif
 	DELAY(printloops, 1)
-WAVE('P')
+PUTC('P')
 	/*
 	 * disable the MMU & caches
 	 */
@@ -80,10 +80,10 @@ WAVE('P')
 	MCR	CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
 	ISB
 
-WAVE('l')
+PUTC('l')
 	DELAY(printloop3, 1)
 
-WAVE('a')
+PUTC('a')
 	/* clear Mach */
 	MOVW	$PADDR(MACHADDR), R4		/* address of Mach */
 	MOVW	$0, R0
@@ -97,7 +97,7 @@ _machZ:
 	 * set up the MMU page table
 	 */
 
-WAVE('n')
+PUTC('n')
 	/* clear all PTEs first, to provide a default */
 //	MOVW	$PADDR(L1+L1X(0)), R4		/* address of PTE for 0 */
 _ptenv0:
@@ -106,7 +106,7 @@ _ptenv0:
 	BNE	_ptenv0
 
 	DELAY(printloop4, 2)
-WAVE(' ')
+PUTC(' ')
 	/*
 	 * set up double map of PHYSDRAM, KZERO to PHYSDRAM for first few MBs,
 	 * but only if KZERO and PHYSDRAM differ.
@@ -129,7 +129,7 @@ no2map:
 	 * igepv2 has 1 bank of 512MB at PHYSDRAM.
 	 * Map the maximum (512MB).
 	 */
-WAVE('9')
+PUTC('9')
 	MOVW	$PTEDRAM, R2			/* PTE bits */
 	MOVW	$PHYSDRAM, R3
 	MOVW	$PADDR(L1+L1X(KZERO)), R4	/* start with PTE for KZERO */
@@ -143,7 +143,7 @@ _ptekrw:					/* set PTEs */
 	 * back up and fill in PTEs for MMIO
 	 * stop somewhere after uarts
 	 */
-WAVE(' ')
+PUTC(' ')
 	MOVW	$PTEIO, R2			/* PTE bits */
 	MOVW	$PHYSIO, R3
 	MOVW	$PADDR(L1+L1X(VIRTIO)), R4	/* start with PTE for VIRTIO */
@@ -167,7 +167,7 @@ _ptenv2:
 	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEwait
 	BARRIERS
 
-WAVE('f')
+PUTC('f')
 	/*
 	 * turn caches on
 	 */
@@ -181,13 +181,13 @@ WAVE('f')
 	MCR	CpSC, 0, R1, C(CpCONTROL), C(0), CpMainctl
 	BARRIERS
 
-WAVE('r')
+PUTC('r')
 	/* set the domain access control */
 	MOVW	$Client, R0
 	BL	dacput(SB)
 
 	DELAY(printloop5, 2)
-WAVE('o')
+PUTC('o')
 	/* set the translation table base */
 	MOVW	$PADDR(L1), R0
 	BL	ttbput(SB)
@@ -195,7 +195,7 @@ WAVE('o')
 	MOVW	$0, R0
 	BL	pidput(SB)		/* paranoia */
 
-WAVE('m')
+PUTC('m')
 	/*
 	 * the little dance to turn the MMU on
 	 */
@@ -203,7 +203,7 @@ WAVE('m')
 	BL	mmuinvalidate(SB)
 	BL	mmuenable(SB)
 
-WAVE(' ')
+PUTC(' ')
 	/* warp the PC into the virtual map */
 	MOVW	$KZERO, R0
 	BL	_r15warp(SB)
@@ -224,7 +224,7 @@ WAVE(' ')
 
 	BL	cacheuwbinv(SB)
 
-WAVE('B')
+PUTC('B')
 	MOVW	$PHYSDRAM, R3			/* pa */
 	CMP	$KZERO, R3
 	BEQ	no2unmap
@@ -260,7 +260,7 @@ no2unmap:
 	ADD	$(MACHSIZE), R13		/* stack pointer */
 	SUB	$4, R13				/* space for link register */
 	MOVW	R0, R10				/* m = MACHADDR */
-WAVE('e')
+PUTC('e')
 	BL	main(SB)			/* void main(Mach*) */
 	/*FALLTHROUGH*/
 
@@ -274,15 +274,15 @@ TEXT _reset(SB), 1, $-4
 	BARRIERS
 
 	DELAY(printloopr, 2)
-WAVE('!')
-WAVE('r')
-WAVE('e')
-WAVE('s')
-WAVE('e')
-WAVE('t')
-WAVE('!')
-WAVE('\r')
-WAVE('\n')
+PUTC('!')
+PUTC('r')
+PUTC('e')
+PUTC('s')
+PUTC('e')
+PUTC('t')
+PUTC('!')
+PUTC('\r')
+PUTC('\n')
 
 	/* turn the caches off */
 	BL	cacheuwbinv(SB)

sys/src/9/omap/rebootcode.s

@@ -23,7 +23,7 @@ TEXT	main(SB), 1, $-4
 	MOVW	R0, CPSR		/* splhi */
 	BARRIERS
 
-WAVE('R')
+PUTC('R')
 	MRC	CpSC, 0, R1, C(CpCONTROL), C(0), CpAuxctl
 	BIC	$CpACasa, R1	/* no speculative I access forwarding to mem */
 	/* slow down */
@@ -39,7 +39,7 @@ WAVE('R')
 	 * turn the MMU off
 	 */
 
-WAVE('e')
+PUTC('e')
 	/* first switch to PHYSDRAM-based addresses */
 	DMB
 
@@ -55,7 +55,7 @@ WAVE('e')
 	 * now running in PHYSDRAM segment, not KZERO.
 	 */
 
-WAVE('b')
+PUTC('b')
 	SUB	$12, SP				/* paranoia */
 	BL	cacheuwbinv(SB)
 	ADD	$12, SP				/* paranoia */
@@ -65,13 +65,13 @@ WAVE('b')
 	MCR	CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinv
 	BARRIERS
 
-WAVE('o')
+PUTC('o')
 	MRC	CpSC, 0, R0, C(CpCONTROL), C(0)
 	BIC	$(CpCmmu|CpCdcache|CpCicache), R0
 	MCR     CpSC, 0, R0, C(CpCONTROL), C(0)	/* mmu off */
 	BARRIERS
 
-WAVE('o')
+PUTC('o')
 	/* copy in arguments from stack frame before moving stack */
 	MOVW	p2+4(FP), R4		/* phys source */
 	MOVW	n+8(FP), R5		/* byte count */
@@ -88,7 +88,7 @@ WAVE('o')
 	MOVW	R6, 44(SP)		/* save dest/entry */
 
 	DELAY(printloop2, 2)
-WAVE('t')
+PUTC('t')
 
 	MOVW	40(SP), R5		/* restore count */
 	MOVW	44(SP), R6		/* restore dest/entry */
@@ -99,17 +99,17 @@ WAVE('t')
 	MOVW	R5, 12(SP)		/* push size */
 	BL	memmove(SB)
 
-WAVE('-')
+PUTC('-')
 	/*
 	 * flush caches
 	 */
 	BL	cacheuwbinv(SB)
 
-WAVE('>')
+PUTC('>')
 	DELAY(printloopret, 1)
-WAVE('\r')
+PUTC('\r')
 	DELAY(printloopnl, 1)
-WAVE('\n')
+PUTC('\n')
 /*
  * jump to kernel entry point.  Note the true kernel entry point is
  * the virtual address KZERO|R6, but this must wait until
@@ -118,7 +118,7 @@ WAVE('\n')
 	MOVW	44(SP), R6		/* restore R6 (dest/entry) */
 	ORR	R6, R6			/* NOP: avoid link bug */
 	B	(R6)
-WAVE('?')
+PUTC('?')
 	B	0(PC)
 
 /*
@@ -201,7 +201,7 @@ TEXT _r15warp(SB), 1, $-4
 	RET
 
 TEXT panic(SB), 1, $-4		/* stub */
-WAVE('?')
+PUTC('?')
 	RET
 TEXT pczeroseg(SB), 1, $-4	/* stub */
 	RET

sys/src/cmd/ssh2/dial.c

@@ -284,13 +284,10 @@ pickuperr(char *besterr, char *err)
 		strcpy(besterr, err);
 }
 
-static void
+static int
 catcher(void *, char *s)
 {
-	if (strstr(s, "alarm") != nil)
-		noted(NCONT);
-	else
-		noted(NDFLT);
+	return strstr(s, "alarm") != nil;
 }
 
 /*
@@ -315,7 +312,7 @@ dialmulti(DS *ds, Dest *dp)
 			--dp->nkid;
 		else if (kid == 0) {
 			/* only in kid, to avoid atnotify callbacks in parent */
-			notify(catcher);
+			atnotify(catcher, 1);
 
 			*besterr = '\0';
 			rv = call(clone, dest, ds, dp, &dp->conn[kidme]);

sys/src/cmd/ssh2/ssh.c

@@ -63,11 +63,13 @@ bail(char *sts)
 }
 
 int
-handler(void *, char *)
+handler(void *, char *s)
 {
 	char *nf;
 	int fd;
 
+	if (strstr(s, "alarm") != nil)
+		return 0;
 	if (chpid) {
 		nf = esmprint("/proc/%d/note", chpid);
 		fd = open(nf, OWRITE);
@@ -113,13 +115,10 @@ parseargs(void)
 
 }
 
-static void
+static int
 catcher(void *, char *s)
 {
-	if (strstr(s, "alarm") != nil)
-		noted(NCONT);
-	else
-		noted(NDFLT);
+	return strstr(s, "alarm") != nil;
 }
 
 static int
@@ -127,10 +126,11 @@ timedmount(int fd, int afd, char *mntpt, int flag, char *aname)
 {
 	int oalarm, ret;
 
-	notify(catcher);
+	atnotify(catcher, 1);
 	oalarm = alarm(5*1000);		/* don't get stuck here */
 	ret = mount(fd, afd, mntpt, flag, aname);
 	alarm(oalarm);
+	atnotify(catcher, 0);
 	return ret;
 }
 

sys/src/libc/9sys/dial.c

@@ -283,13 +283,10 @@ pickuperr(char *besterr, char *err)
 		strcpy(besterr, err);
 }
 
-static void
+static int
 catcher(void *, char *s)
 {
-	if (strstr(s, "alarm") != nil)
-		noted(NCONT);
-	else
-		noted(NDFLT);
+	return strstr(s, "alarm") != nil;
 }
 
 /*
@@ -314,7 +311,7 @@ dialmulti(DS *ds, Dest *dp)
 			--dp->nkid;
 		else if (kid == 0) {
 			/* only in kid, to avoid atnotify callbacks in parent */
-			notify(catcher);
+			atnotify(catcher, 1);
 
 			*besterr = '\0';
 			rv = call(clone, dest, ds, dp, &dp->conn[kidme]);

sys/src/libc/arm/atom.s

@@ -2,8 +2,10 @@
  * int cas(ulong *p, ulong ov, ulong nv);
  */
 
+#define	CLREX		WORD	$0xf57ff01f
 #define	LDREX(a,r)	WORD	$(0xe<<28|0x01900f9f | (a)<<16 | (r)<<12)
-#define	STREX(a,v,r)	WORD	$(0xe<<28|0x01800f90 | (a)<<16 | (r)<<12 | (v)<<0)
+/* `The order of operands is from left to right in dataflow order' - asm man */
+#define	STREX(v,a,r)	WORD	$(0xe<<28|0x01800f90 | (a)<<16 | (r)<<12 | (v)<<0)
 
 TEXT	cas+0(SB),0,$12		/* r0 holds p */
 TEXT	casp+0(SB),0,$12	/* r0 holds p */
@@ -13,12 +15,13 @@ spincas:
 	LDREX(0,3)	/*	LDREX	0(R0),R3	*/
 	CMP.S	R3, R1
 	BNE	fail
-	STREX(0,2,4)	/*	STREX	0(R0),R2,R4	*/
+	STREX(2,0,4)	/*	STREX	0(R0),R2,R4	*/
 	CMP.S	$0, R4
 	BNE	spincas
 	MOVW	$1, R0
 	RET
 fail:
+//	CLREX		/* fpiarm in pre-v7 ports needs to emulate this */
 	MOVW	$0, R0
 	RET
 
@@ -27,7 +30,7 @@ TEXT ainc(SB), $0	/* long ainc(long *); */
 spinainc:
 	LDREX(0,3)	/*	LDREX	0(R0),R3	*/
 	ADD	$1,R3
-	STREX(0,3,4)	/*	STREX	0(R0),R2,R4	*/
+	STREX(3,0,4)	/*	STREX	0(R0),R3,R4	*/
 	CMP.S	$0, R4
 	BNE	spinainc
 	MOVW	R3, R0
@@ -38,7 +41,7 @@ TEXT adec(SB), $0	/* long adec(long *); */
 spinadec:
 	LDREX(0,3)	/*	LDREX	0(R0),R3	*/
 	SUB	$1,R3
-	STREX(0,3,4)	/*	STREX	0(R0),R3,R4	*/
+	STREX(3,0,4)	/*	STREX	0(R0),R3,R4	*/
 	CMP.S	$0, R4
 	BNE	spinadec
 	MOVW	R3, R0
@@ -50,6 +53,6 @@ TEXT loadlinked(SB), $0	/* long loadlinked(long *); */
 
 TEXT storecond(SB), $0	/* int storecond(long *, long); */
 	MOVW	ov+4(FP), R3
-	STREX(0,3,0)	/*	STREX	0(R0),R3,R0	*/
+	STREX(3,0,0)	/*	STREX	0(R0),R3,R0	*/
 	RSB	$1, R0
 	RET