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@@ -0,0 +1,676 @@
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+ /*
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+ Via Rhine driver, written for VT6102.
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+ Uses the ethermii to control PHY.
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+
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+ Currently always copies on both, tx and rx.
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+ rx side could be copy-free, and tx-side might be made
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+ (almost) copy-free by using (possibly) two descriptors (if it allows
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+ arbitrary tx lengths, which it should..): first for alignment and
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+ second for rest of the frame. Rx-part should be worth doing.
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+*/
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+#include "u.h"
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+#include "lib.h"
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+#include "mem.h"
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+#include "dat.h"
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+#include "fns.h"
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+#include "io.h"
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+
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+typedef struct QLock { int r; } QLock;
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+#define qlock(i) while(0)
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+#define qunlock(i) while(0)
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+#define coherence()
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+#define iprint print
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+
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+#include "etherif.h"
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+#include "ethermii.h"
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+
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+typedef struct Desc Desc;
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+typedef struct Ctlr Ctlr;
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+
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+enum {
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+ Ntxd = 4,
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+ Nrxd = 4,
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+ Nwait = 50,
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+ Ntxstats = 9,
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+ Nrxstats = 8,
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+ BIGSTR = 8192,
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+};
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+
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+struct Desc {
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+ ulong stat;
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+ ulong size;
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+ ulong addr;
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+ ulong next;
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+ char *buf;
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+ ulong pad[3];
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+};
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+
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+struct Ctlr {
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+ Pcidev *pci;
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+ int attached;
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+ int txused;
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+ int txhead;
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+ int txtail;
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+ int rxtail;
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+ ulong port;
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+
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+ Mii mii;
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+
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+ ulong txstats[Ntxstats];
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+ ulong rxstats[Nrxstats];
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+
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+ Desc *txd; /* wants to be aligned on 16-byte boundary */
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+ Desc *rxd;
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+
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+ QLock attachlck;
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+ Lock tlock;
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+};
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+
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+#define ior8(c, r) (inb((c)->port+(r)))
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+#define ior16(c, r) (ins((c)->port+(r)))
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+#define ior32(c, r) (inl((c)->port+(r)))
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+#define iow8(c, r, b) (outb((c)->port+(r), (int)(b)))
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+#define iow16(c, r, w) (outs((c)->port+(r), (ushort)(w)))
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+#define iow32(c, r, l) (outl((c)->port+(r), (ulong)(l)))
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+
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+enum Regs {
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+ Eaddr = 0x0,
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+ Rcr = 0x6,
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+ Tcr = 0x7,
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+ Cr = 0x8,
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+ Isr = 0xc,
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+ Imr = 0xe,
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+ McastAddr = 0x10,
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+ RxdAddr = 0x18,
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+ TxdAddr = 0x1C,
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+ Bcr = 0x6e,
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+ RhineMiiPhy = 0x6C,
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+ RhineMiiSr = 0x6D,
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+ RhineMiiCr = 0x70,
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+ RhineMiiAddr = 0x71,
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+ RhineMiiData = 0x72,
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+ Eecsr = 0x74,
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+ ConfigB = 0x79,
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+ ConfigD = 0x7B,
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+ MiscCr = 0x80,
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+ HwSticky = 0x83,
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+ MiscIsr = 0x84,
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+ MiscImr = 0x86,
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+ WolCrSet = 0xA0,
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+ WolCfgSet = 0xA1,
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+ WolCgSet = 0xA3,
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+ WolCrClr = 0xA4,
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+ PwrCfgClr = 0xA5,
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+ WolCgClr = 0xA7,
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+};
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+
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+enum Rcrbits {
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+ RxErrX = 1<<0,
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+ RxSmall = 1<<1,
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+ RxMcast = 1<<2,
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+ RxBcast = 1<<3,
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+ RxProm = 1<<4,
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+ RxFifo64 = 0<<5, RxFifo32 = 1<<5, RxFifo128 = 2<<5, RxFifo256 = 3<<5,
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+ RxFifo512 = 4<<5, RxFifo768 = 5<<5, RxFifo1024 = 6<<5,
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+ RxFifoStoreForward = 7<<5,
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+};
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+
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+enum Tcrbits {
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+ TxLoopback0 = 1<<1,
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+ TxLoopback1 = 1<<2,
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+ TxBackoff = 1<<3,
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+ TxFifo128 = 0<<5, TxFifo256 = 1<<5, TxFifo512 = 2<<5, TxFifo1024 = 3<<5,
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+ TxFifoStoreForward = 7<<5,
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+};
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+
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+enum Crbits {
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+ Init = 1<<0,
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+ Start = 1<<1,
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+ Stop = 1<<2,
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+ RxOn = 1<<3,
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+ TxOn = 1<<4,
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+ Tdmd = 1<<5,
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+ Rdmd = 1<<6,
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+ EarlyRx = 1<<8,
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+ Reserved0 = 1<<9,
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+ FullDuplex = 1<<10,
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+ NoAutoPoll = 1<<11,
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+ Reserved1 = 1<<12,
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+ Tdmd1 = 1<<13,
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+ Rdmd1 = 1<<14,
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+ Reset = 1<<15,
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+};
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+
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+enum Isrbits {
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+ RxOk = 1<<0,
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+ TxOk = 1<<1,
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+ RxErr = 1<<2,
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+ TxErr = 1<<3,
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+ TxBufUdf = 1<<4,
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+ RxBufLinkErr = 1<<5,
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+ BusErr = 1<<6,
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+ CrcOvf = 1<<7,
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+ EarlyRxInt = 1<<8,
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+ TxFifoUdf = 1<<9,
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+ RxFifoOvf = 1<<10,
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+ TxPktRace = 1<<11,
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+ NoRxbuf = 1<<12,
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+ TxCollision = 1<<13,
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+ PortCh = 1<<14,
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+ GPInt = 1<<15
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+};
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+
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+enum Bcrbits {
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+ Dma32 = 0<<0, Dma64 = 1<<0, Dma128 = 2<<0,
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+ Dma256 = 3<<0, Dma512 = 4<<0, Dma1024 = 5<<0,
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+ DmaStoreForward = 7<<0,
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+ DupRxFifo0 = 1<<3, DupRxFifo1 = 1<<4, DupRxFifo2 = 1<<5,
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+ ExtraLed = 1<<6,
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+ MediumSelect = 1<<7,
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+ PollTimer0 = 1<<8, PollTimer1 = 1<<9, PollTimer2 = 1<<10,
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+ DupTxFifo0 = 1<<11, DupTxFifo1 = 1<<12, DupTxFifo2 = 1<<13,
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+};
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+
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+enum Eecsrbits {
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+ EeAutoLoad = 1<<5,
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+};
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+
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+enum MiscCrbits {
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+ Timer0Enable= 1<<0,
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+ Timer0Suspend = 1<<1,
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+ HalfDuplexFlowControl = 1<<2,
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+ FullDuplexFlowControl = 1<<3,
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+ Timer1Enable = 1<<8,
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+ ForceSoftReset = 1<<14,
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+};
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+
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+enum HwStickybits {
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+ StickyDS0 = 1<<0,
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+ StickyDS1 = 1<<1,
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+ WOLEna = 1<<2,
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+ WOLStat = 1<<3,
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+};
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+
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+enum WolCgbits {
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+ PmeOvr = 1<<7,
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+};
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+
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+enum Descbits {
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+ OwnNic = 1<<31, /* stat */
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+ TxAbort = 1<<8, /* stat */
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+ TxError = 1<<15, /* stat */
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+ RxChainbuf = 1<<10, /* stat */
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+ RxChainStart = 1<<9, /* stat */
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+ RxChainEnd = 1<<8, /* stat */
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+ Chainbuf = 1<<15, /* size rx & tx*/
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+ TxDisableCrc = 1<<16, /* size */
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+ TxChainStart = 1<<21, /* size */
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+ TxChainEnd = 1<<22, /* size */
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+ TxInt = 1<<23, /* size */
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+};
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+
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+enum ConfigDbits {
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+ BackoffOptional = 1<<0,
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+ BackoffAMD = 1<<1,
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+ BackoffDEC = 1<<2,
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+ BackoffRandom = 1<<3,
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+ PmccTestMode = 1<<4,
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+ PciReadlineCap = 1<<5,
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+ DiagMode = 1<<6,
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+ MmioEnable = 1<<7,
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+};
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+
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+enum ConfigBbits {
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+ LatencyTimer = 1<<0,
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+ WriteWaitState = 1<<1,
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+ ReadWaitState = 1<<2,
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+ RxArbit = 1<<3,
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+ TxArbit = 1<<4,
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+ NoMemReadline = 1<<5,
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+ NoParity = 1<<6,
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+ NoTxQueuing = 1<<7,
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+};
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+
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+enum RhineMiiCrbits {
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+ Mdc = 1<<0,
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+ Mdi = 1<<1,
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+ Mdo = 1<<2,
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+ Mdout = 1<<3,
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+ Mdpm = 1<<4,
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+ Wcmd = 1<<5,
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+ Rcmd = 1<<6,
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+ Mauto = 1<<7,
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+};
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+
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+enum RhineMiiSrbits {
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+ Speed10M = 1<<0,
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+ LinkFail = 1<<1,
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+ PhyError = 1<<3,
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+ DefaultPhy = 1<<4,
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+ ResetPhy = 1<<7,
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+};
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+
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+enum RhineMiiAddrbits {
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+ Mdone = 1<<5,
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+ Msrcen = 1<<6,
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+ Midle = 1<<7,
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+};
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+
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+static char *
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+txstatnames[Ntxstats] = {
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+ "aborts (excess collisions)",
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+ "out of window collisions",
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+ "carrier sense losses",
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+ "fifo underflows",
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+ "invalid descriptor format or underflows",
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+ "system errors",
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+ "reserved",
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+ "transmit errors",
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+ "collisions",
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+};
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+
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+static char *
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+rxstatnames[Nrxstats] = {
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+ "receiver errors",
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+ "crc errors",
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+ "frame alignment errors",
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+ "fifo overflows",
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+ "long packets",
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+ "run packets",
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+ "system errors",
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+ "buffer underflows",
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+};
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+
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+static void
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+attach(Ether *edev)
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+{
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+ Ctlr *ctlr;
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+ Desc *txd, *rxd, *td, *rd;
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+ Mii *mi;
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+ MiiPhy *phy;
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+ int i, s;
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+
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+ ctlr = edev->ctlr;
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+ qlock(&ctlr->attachlck);
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+ if (ctlr->attached == 0) {
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+ txd = ctlr->txd;
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+ rxd = ctlr->rxd;
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+ for (i = 0; i < Ntxd; ++i) {
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+ td = &txd[i];
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+ td->next = PCIWADDR(&txd[(i+1) % Ntxd]);
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+ td->buf = xspanalloc(sizeof(Etherpkt)+4, 4, 0);
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+ td->addr = PCIWADDR(td->buf);
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+ td->size = 0;
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+ coherence();
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+ td->stat = 0;
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+ }
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+ for (i = 0; i < Nrxd; ++i) {
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+ rd = &rxd[i];
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+ rd->next = PCIWADDR(&rxd[(i+1) % Nrxd]);
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+ rd->buf = xspanalloc(sizeof(Etherpkt)+4, 4, 0);
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+ rd->addr = PCIWADDR(rd->buf);
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+ rd->size = sizeof(Etherpkt)+4;
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+ coherence();
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+ rd->stat = OwnNic;
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+ }
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+
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+ ctlr->txhead = ctlr->txtail = ctlr->rxtail = 0;
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+ mi = &ctlr->mii;
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+ miistatus(mi);
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+ phy = mi->curphy;
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+ s = splhi();
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+ iow32(ctlr, TxdAddr, PCIWADDR(&txd[0]));
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+ iow32(ctlr, RxdAddr, PCIWADDR(&rxd[0]));
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+ iow16(ctlr, Cr, (phy->fd ? FullDuplex : 0) | NoAutoPoll | TxOn | RxOn | Start | Rdmd);
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+ iow16(ctlr, Isr, 0xFFFF);
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+ iow16(ctlr, Imr, 0xFFFF);
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+ iow8(ctlr, MiscIsr, 0xFF);
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+ iow8(ctlr, MiscImr, ~(3<<5));
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+ splx(s);
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+ }
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+ ctlr->attached++;
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+ qunlock(&ctlr->attachlck);
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+}
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+
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+static void
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+txstart(Ether *edev)
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+{
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+ Ctlr *ctlr;
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+ Desc *txd, *td;
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+ int i, txused, n;
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+ RingBuf *tb;
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+
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+ ctlr = edev->ctlr;
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+
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+ txd = ctlr->txd;
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+ i = ctlr->txhead;
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+ txused = ctlr->txused;
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+ n = 0;
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+ while (txused < Ntxd) {
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+ tb = &edev->tb[edev->ti];
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+ if(tb->owner != Interface)
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+ break;
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+
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+ td = &txd[i];
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+ memmove(td->buf, tb->pkt, tb->len);
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+ td->size = tb->len | TxChainStart | TxChainEnd | TxInt; /* could reduce number of ints here */
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+ coherence();
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+ td->stat = OwnNic;
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+ i = (i + 1) % Ntxd;
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+ txused++;
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+ n++;
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+
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+ tb->owner = Host;
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+ edev->ti = NEXT(edev->ti, edev->ntb);
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+ }
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+ if (n)
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+ iow16(ctlr, Cr, ior16(ctlr, Cr) | Tdmd);
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+
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+ ctlr->txhead = i;
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+ ctlr->txused = txused;
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+}
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+
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+static void
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+transmit(Ether *edev)
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+{
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+ Ctlr *ctlr;
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+ ctlr = edev->ctlr;
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+ ilock(&ctlr->tlock);
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+ txstart(edev);
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+ iunlock(&ctlr->tlock);
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+}
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+
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+static void
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+txcomplete(Ether *edev)
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+{
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+ Ctlr *ctlr;
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+ Desc *txd, *td;
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+ int i, txused, j;
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+ ulong stat;
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+
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+ ctlr = edev->ctlr;
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+ txd = ctlr->txd;
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+ txused = ctlr->txused;
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+ i = ctlr->txtail;
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+ while (txused > 0) {
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+ td = &txd[i];
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+ stat = td->stat;
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+
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+ if (stat & OwnNic)
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+ break;
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+
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+ ctlr->txstats[Ntxstats-1] += stat & 0xF;
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+ for (j = 0; j < Ntxstats-1; ++j)
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+ if (stat & (1<<(j+8)))
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+ ctlr->txstats[j]++;
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+
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+ i = (i + 1) % Ntxd;
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+ txused--;
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+ }
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+ ctlr->txused = txused;
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+ ctlr->txtail = i;
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+
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+ if (txused <= Ntxd/2)
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+ txstart(edev);
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+}
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+
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+static void
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+interrupt(Ureg *, void *arg)
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+{
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+ Ether *edev;
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+ Ctlr *ctlr;
|
|
|
+ RingBuf *rb;
|
|
|
+ ushort isr, misr;
|
|
|
+ ulong stat;
|
|
|
+ Desc *rxd, *rd;
|
|
|
+ int i, n, j, size;
|
|
|
+
|
|
|
+ edev = (Ether*)arg;
|
|
|
+ ctlr = edev->ctlr;
|
|
|
+ iow16(ctlr, Imr, 0);
|
|
|
+ isr = ior16(ctlr, Isr);
|
|
|
+ iow16(ctlr, Isr, 0xFFFF);
|
|
|
+ misr = ior16(ctlr, MiscIsr) & ~(3<<5); /* don't care about used defined ints */
|
|
|
+
|
|
|
+ if (isr & RxOk) {
|
|
|
+ rxd = ctlr->rxd;
|
|
|
+ i = ctlr->rxtail;
|
|
|
+
|
|
|
+ n = 0;
|
|
|
+ while ((rxd[i].stat & OwnNic) == 0) {
|
|
|
+ rd = &rxd[i];
|
|
|
+ stat = rd->stat;
|
|
|
+ for (j = 0; j < Nrxstats; ++j)
|
|
|
+ if (stat & (1<<j))
|
|
|
+ ctlr->rxstats[j]++;
|
|
|
+
|
|
|
+ if (stat & 0xFF)
|
|
|
+ iprint("rx: %lux\n", stat & 0xFF);
|
|
|
+
|
|
|
+ size = ((rd->stat>>16) & 2047) - 4;
|
|
|
+
|
|
|
+ rb = &edev->rb[edev->ri];
|
|
|
+ if(rb->owner == Interface){
|
|
|
+ rb->owner = Host;
|
|
|
+ rb->len = size;
|
|
|
+ memmove(rb->pkt, rd->buf, size);
|
|
|
+ edev->ri = NEXT(edev->ri, edev->nrb);
|
|
|
+ }
|
|
|
+
|
|
|
+ rd->size = sizeof(Etherpkt)+4;
|
|
|
+ coherence();
|
|
|
+ rd->stat = OwnNic;
|
|
|
+ i = (i + 1) % Nrxd;
|
|
|
+ n++;
|
|
|
+ }
|
|
|
+ if (n)
|
|
|
+ iow16(ctlr, Cr, ior16(ctlr, Cr) | Rdmd);
|
|
|
+ ctlr->rxtail = i;
|
|
|
+ isr &= ~RxOk;
|
|
|
+ }
|
|
|
+ if (isr & TxOk) {
|
|
|
+ txcomplete(edev);
|
|
|
+ isr &= ~TxOk;
|
|
|
+ }
|
|
|
+ if (isr | misr)
|
|
|
+ iprint("etherrhine: unhandled irq(s). isr:%x misr:%x\n", isr, misr);
|
|
|
+
|
|
|
+ iow16(ctlr, Imr, 0xFFFF);
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+promiscuous(void *arg, int enable)
|
|
|
+{
|
|
|
+ Ether *edev;
|
|
|
+ Ctlr *ctlr;
|
|
|
+
|
|
|
+ edev = arg;
|
|
|
+ ctlr = edev->ctlr;
|
|
|
+ ilock(&ctlr->tlock);
|
|
|
+ iow8(ctlr, Rcr, ior8(ctlr, Rcr) | (enable ? RxProm : RxBcast));
|
|
|
+ iunlock(&ctlr->tlock);
|
|
|
+}
|
|
|
+
|
|
|
+static int
|
|
|
+miiread(Mii *mii, int phy, int reg)
|
|
|
+{
|
|
|
+ Ctlr *ctlr;
|
|
|
+ int n;
|
|
|
+
|
|
|
+ ctlr = mii->ctlr;
|
|
|
+
|
|
|
+ n = Nwait;
|
|
|
+ while (n-- && ior8(ctlr, RhineMiiCr) & (Rcmd | Wcmd))
|
|
|
+ microdelay(1);
|
|
|
+ if (n == Nwait)
|
|
|
+ iprint("etherrhine: miiread: timeout\n");
|
|
|
+
|
|
|
+ iow8(ctlr, RhineMiiCr, 0);
|
|
|
+ iow8(ctlr, RhineMiiPhy, phy);
|
|
|
+ iow8(ctlr, RhineMiiAddr, reg);
|
|
|
+ iow8(ctlr, RhineMiiCr, Rcmd);
|
|
|
+
|
|
|
+ n = Nwait;
|
|
|
+ while (n-- && ior8(ctlr, RhineMiiCr) & Rcmd)
|
|
|
+ microdelay(1);
|
|
|
+ if (n == Nwait)
|
|
|
+ iprint("etherrhine: miiread: timeout\n");
|
|
|
+
|
|
|
+ n = ior16(ctlr, RhineMiiData);
|
|
|
+
|
|
|
+ return n;
|
|
|
+}
|
|
|
+
|
|
|
+static int
|
|
|
+miiwrite(Mii *mii, int phy, int reg, int data)
|
|
|
+{
|
|
|
+ int n;
|
|
|
+ Ctlr *ctlr;
|
|
|
+
|
|
|
+ ctlr = mii->ctlr;
|
|
|
+
|
|
|
+ n = Nwait;
|
|
|
+ while (n-- && ior8(ctlr, RhineMiiCr) & (Rcmd | Wcmd))
|
|
|
+ microdelay(1);
|
|
|
+ if (n == Nwait)
|
|
|
+ iprint("etherrhine: miiwrite: timeout\n");
|
|
|
+
|
|
|
+ iow8(ctlr, RhineMiiCr, 0);
|
|
|
+ iow8(ctlr, RhineMiiPhy, phy);
|
|
|
+ iow8(ctlr, RhineMiiAddr, reg);
|
|
|
+ iow16(ctlr, RhineMiiData, data);
|
|
|
+ iow8(ctlr, RhineMiiCr, Wcmd);
|
|
|
+
|
|
|
+ n = Nwait;
|
|
|
+ while (n-- && ior8(ctlr, RhineMiiCr) & Wcmd)
|
|
|
+ microdelay(1);
|
|
|
+ if (n == Nwait)
|
|
|
+ iprint("etherrhine: miiwrite: timeout\n");
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+reset(Ctlr* ctlr)
|
|
|
+{
|
|
|
+ int i;
|
|
|
+
|
|
|
+ iow16(ctlr, Cr, ior16(ctlr, Cr) | Stop);
|
|
|
+ iow16(ctlr, Cr, ior16(ctlr, Cr) | Reset);
|
|
|
+
|
|
|
+ for (i = 0; i < Nwait; ++i) {
|
|
|
+ if ((ior16(ctlr, Cr) & Reset) == 0)
|
|
|
+ return;
|
|
|
+ delay(5);
|
|
|
+ }
|
|
|
+ iprint("etherrhine: reset timeout\n");
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+detach(Ether* edev)
|
|
|
+{
|
|
|
+ reset(edev->ctlr);
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+init(Ether *edev)
|
|
|
+{
|
|
|
+ Ctlr *ctlr;
|
|
|
+ int i;
|
|
|
+
|
|
|
+ ctlr = edev->ctlr;
|
|
|
+
|
|
|
+ ilock(&ctlr->tlock);
|
|
|
+
|
|
|
+ pcisetbme(ctlr->pci);
|
|
|
+
|
|
|
+ reset(ctlr);
|
|
|
+
|
|
|
+ iow8(ctlr, Eecsr, ior8(ctlr, Eecsr) | EeAutoLoad);
|
|
|
+ for (i = 0; i < Nwait; ++i) {
|
|
|
+ if ((ior8(ctlr, Eecsr) & EeAutoLoad) == 0)
|
|
|
+ break;
|
|
|
+ delay(5);
|
|
|
+ }
|
|
|
+ if (i == Nwait)
|
|
|
+ iprint("etherrhine: eeprom autoload timeout\n");
|
|
|
+
|
|
|
+ for (i = 0; i < Eaddrlen; ++i)
|
|
|
+ edev->ea[i] = ior8(ctlr, Eaddr + i);
|
|
|
+
|
|
|
+ ctlr->mii.mir = miiread;
|
|
|
+ ctlr->mii.miw = miiwrite;
|
|
|
+ ctlr->mii.ctlr = ctlr;
|
|
|
+
|
|
|
+ if(mii(&ctlr->mii, ~0) == 0 || ctlr->mii.curphy == nil){
|
|
|
+ iprint("etherrhine: init mii failure\n");
|
|
|
+ return;
|
|
|
+ }
|
|
|
+ for (i = 0; i < NMiiPhy; ++i)
|
|
|
+ if (ctlr->mii.phy[i])
|
|
|
+ if (ctlr->mii.phy[i]->oui != 0xFFFFF)
|
|
|
+ ctlr->mii.curphy = ctlr->mii.phy[i];
|
|
|
+
|
|
|
+ miistatus(&ctlr->mii);
|
|
|
+
|
|
|
+ iow16(ctlr, Imr, 0);
|
|
|
+ iow16(ctlr, Cr, ior16(ctlr, Cr) | Stop);
|
|
|
+
|
|
|
+ iunlock(&ctlr->tlock);
|
|
|
+}
|
|
|
+
|
|
|
+static Pcidev *
|
|
|
+rhinematch(ulong)
|
|
|
+{
|
|
|
+ static int nrhines = 0;
|
|
|
+ int nfound = 0;
|
|
|
+ Pcidev *p = nil;
|
|
|
+
|
|
|
+ while (p = pcimatch(p, 0x1106, 0))
|
|
|
+ if (p->did == 0x3065)
|
|
|
+ if (++nfound > nrhines) {
|
|
|
+ nrhines++;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ return p;
|
|
|
+}
|
|
|
+
|
|
|
+int
|
|
|
+rhinepnp(Ether *edev)
|
|
|
+{
|
|
|
+ Pcidev *p;
|
|
|
+ Ctlr *ctlr;
|
|
|
+ ulong port;
|
|
|
+
|
|
|
+ p = rhinematch(edev->port);
|
|
|
+ if (p == nil)
|
|
|
+ return -1;
|
|
|
+
|
|
|
+ port = p->mem[0].bar & ~1;
|
|
|
+
|
|
|
+ if ((ctlr = malloc(sizeof(Ctlr))) == nil) {
|
|
|
+ print("etherrhine: couldn't allocate memory for ctlr\n");
|
|
|
+ return -1;
|
|
|
+ }
|
|
|
+ memset(ctlr, 0, sizeof(Ctlr));
|
|
|
+ ctlr->txd = xspanalloc(sizeof(Desc) * Ntxd, 16, 0);
|
|
|
+ ctlr->rxd = xspanalloc(sizeof(Desc) * Nrxd, 16, 0);
|
|
|
+
|
|
|
+ ctlr->pci = p;
|
|
|
+ ctlr->port = port;
|
|
|
+
|
|
|
+ edev->ctlr = ctlr;
|
|
|
+ edev->port = ctlr->port;
|
|
|
+ edev->irq = p->intl;
|
|
|
+ edev->tbdf = p->tbdf;
|
|
|
+
|
|
|
+ init(edev);
|
|
|
+
|
|
|
+
|
|
|
+ edev->attach = attach;
|
|
|
+ edev->transmit = transmit;
|
|
|
+ edev->interrupt = interrupt;
|
|
|
+ edev->detach = detach;
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
David du Colombier