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+/* Portions of this file derived from work with the following copyright */
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+
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+ /***************************************************************************\
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+|* *|
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+|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
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+|* *|
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+|* NOTICE TO USER: The source code is copyrighted under U.S. and *|
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+|* international laws. Users and possessors of this source code are *|
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+|* hereby granted a nonexclusive, royalty-free copyright license to *|
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+|* use this code in individual and commercial software. *|
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+|* *|
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+|* Any use of this source code must include, in the user documenta- *|
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+|* tion and internal comments to the code, notices to the end user *|
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+|* as follows: *|
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+|* *|
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+|* Copyright 2003 NVIDIA, Corporation. All rights reserved. *|
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+|* *|
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+|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
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+|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
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+|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
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+|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
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+|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
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+|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
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+|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
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+|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
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+|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
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+|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
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+|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
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+|* *|
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+|* U.S. Government End Users. This source code is a "commercial *|
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+|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
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+|* consisting of "commercial computer software" and "commercial *|
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+|* computer software documentation," as such terms are used in *|
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+|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
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+|* ment only as a commercial end item. Consistent with 48 C.F.R. *|
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+|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
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+|* all U.S. Government End Users acquire the source code with only *|
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+|* those rights set forth herein. *|
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+|* *|
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+ \***************************************************************************/
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+
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+#include "u.h"
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+#include "../port/lib.h"
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+#include "mem.h"
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+#include "dat.h"
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+#include "fns.h"
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+#include "io.h"
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+#include "../port/error.h"
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+
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+#define Image IMAGE
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+#include <draw.h>
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+#include <memdraw.h>
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+#include <cursor.h>
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+#include "screen.h"
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+#include "nv_dma.h"
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+
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+enum {
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+ Pramin = 0x00710000,
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+ Pramdac = 0x00680000,
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+ Fifo = 0x00800000,
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+ Pgraph = 0x00400000,
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+ Pfb = 0x00100000
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+};
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+
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+enum {
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+ hwCurPos = Pramdac + 0x0300,
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+};
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+
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+#define SKIPS 8
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+
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+struct {
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+ ulong *dmabase;
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+ int dmacurrent;
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+ int dmaput;
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+ int dmafree;
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+ int dmamax;
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+} nv;
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+
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+static Pcidev*
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+nvidiapci(void)
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+{
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+ Pcidev *p;
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+
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+ p = nil;
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+ while((p = pcimatch(p, 0x10DE, 0)) != nil){
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+ if(p->did >= 0x20 && p->ccrb == 3) /* video card */
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+ return p;
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+ }
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+ return nil;
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+}
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+
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+static void
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+nvidialinear(VGAscr*, int, int)
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+{
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+}
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+
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+static void
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+nvidiaenable(VGAscr* scr)
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+{
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+ Pcidev *p;
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+ ulong *q;
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+ int tmp;
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+
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+ if(scr->mmio)
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+ return;
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+ p = nvidiapci();
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+ if(p == nil)
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+ return;
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+ scr->id = p->did;
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+ scr->pci = p;
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+
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+ scr->mmio = vmap(p->mem[0].bar & ~0x0F, p->mem[0].size);
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+ if(scr->mmio == nil)
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+ return;
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+ addvgaseg("nvidiammio", p->mem[0].bar&~0x0F, p->mem[0].size);
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+
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+ vgalinearpci(scr);
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+ if(scr->apsize)
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+ addvgaseg("nvidiascreen", scr->paddr, scr->apsize);
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+
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+ /* find video memory size */
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+ switch (scr->id & 0x0ff0) {
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+ case 0x0020:
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+ case 0x00A0:
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+ q = (void*)((uchar*)scr->mmio + Pfb);
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+ tmp = *q;
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+ if (tmp & 0x0100) {
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+ scr->storage = ((tmp >> 12) & 0x0F) * 1024 + 1024 * 2;
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+ } else {
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+ tmp &= 0x03;
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+ if (tmp)
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+ scr->storage = (1024*1024*2) << tmp;
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+ else
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+ scr->storage = 1024*1024*32;
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+ }
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+ break;
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+ case 0x01A0:
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+ p = pcimatchtbdf(MKBUS(BusPCI, 0, 0, 1));
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+ tmp = pcicfgr32(p, 0x7C);
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+ scr->storage = (((tmp >> 6) & 31) + 1) * 1024 * 1024;
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+ break;
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+ case 0x01F0:
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+ p = pcimatchtbdf(MKBUS(BusPCI, 0, 0, 1));
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+ tmp = pcicfgr32(p, 0x84);
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+ scr->storage = (((tmp >> 4) & 127) + 1) * 1024 * 1024;
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+ break;
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+ default:
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+ q = (void*)((uchar*)scr->mmio + Pfb + 0x020C);
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+ tmp = (*q >> 20) & 0xFFF;
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+ if (tmp == 0)
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+ tmp = 16;
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+ scr->storage = tmp*1024*1024;
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+ break;
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+ }
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+}
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+
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+static void
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+nvidiacurdisable(VGAscr* scr)
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+{
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+ if(scr->mmio == 0)
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+ return;
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+
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+ vgaxo(Crtx, 0x31, vgaxi(Crtx, 0x31) & ~0x01);
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+}
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+
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+
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+static void
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+nvidiacurload(VGAscr* scr, Cursor* curs)
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+{
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+ ulong* p;
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+ int i,j;
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+ ushort c,s;
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+ ulong tmp;
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+
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+ if(scr->mmio == 0)
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+ return;
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+
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+ vgaxo(Crtx, 0x31, vgaxi(Crtx, 0x31) & ~0x01);
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+
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+ switch (scr->id & 0x0ff0) {
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+ case 0x0020:
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+ case 0x00A0:
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+ p = (void*)((uchar*)scr->mmio + Pramin + 0x1E00 * 4);
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+ break;
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+ default:
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+ /*
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+ * Reset the cursor location, since the kernel may
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+ * have allocated less storage than aux/vga
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+ * expected.
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+ */
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+ tmp = scr->apsize - 96*1024;
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+ p = (void*)((uchar*)scr->vaddr + tmp);
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+ vgaxo(Crtx, 0x30, 0x80|(tmp>>17));
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+ vgaxo(Crtx, 0x31, (tmp>>11)<<2);
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+ vgaxo(Crtx, 0x2F, tmp>>24);
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+ break;
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+ }
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+
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+ for(i=0; i<16; i++) {
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+ c = (curs->clr[2 * i] << 8) | curs->clr[2 * i+1];
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+ s = (curs->set[2 * i] << 8) | curs->set[2 * i+1];
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+ tmp = 0;
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+ for (j=0; j<16; j++){
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+ if(s&0x8000)
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+ tmp |= 0x80000000;
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+ else if(c&0x8000)
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+ tmp |= 0xFFFF0000;
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+ if (j&0x1){
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+ *p++ = tmp;
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+ tmp = 0;
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+ } else {
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+ tmp>>=16;
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+ }
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+ c<<=1;
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+ s<<=1;
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+ }
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+ for (j=0; j<8; j++)
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+ *p++ = 0;
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+ }
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+ for (i=0; i<256; i++)
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+ *p++ = 0;
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+
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+ scr->offset = curs->offset;
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+ vgaxo(Crtx, 0x31, vgaxi(Crtx, 0x31) | 0x01);
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+
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+ return;
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+}
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+
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+static int
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+nvidiacurmove(VGAscr* scr, Point p)
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+{
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+ ulong* cursorpos;
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+
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+ if(scr->mmio == 0)
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+ return 1;
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+
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+ cursorpos = (void*)((uchar*)scr->mmio + hwCurPos);
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+ *cursorpos = ((p.y+scr->offset.y)<<16)|((p.x+scr->offset.x) & 0xFFFF);
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+
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+ return 0;
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+}
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+
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+static void
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+nvidiacurenable(VGAscr* scr)
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+{
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+ nvidiaenable(scr);
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+ if(scr->mmio == 0)
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+ return;
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+
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+ vgaxo(Crtx, 0x1F, 0x57);
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+
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+ nvidiacurload(scr, &arrow);
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+ nvidiacurmove(scr, ZP);
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+
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+ vgaxo(Crtx, 0x31, vgaxi(Crtx, 0x31) | 0x01);
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+}
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+
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+void
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+writeput(VGAscr *scr, int data)
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+{
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+ uchar *p, scratch;
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+ ulong *fifo;
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+
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+ outb(0x3D0,0);
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+ p = scr->vaddr;
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+ scratch = *p;
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+ fifo = (void*)((uchar*)scr->mmio + Fifo);
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+ fifo[0x10] = (data << 2);
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+ USED(scratch);
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+}
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+
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+ulong
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+readget(VGAscr *scr)
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+{
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+ ulong *fifo;
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+
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+ fifo = (void*)((uchar*)scr->mmio + Fifo);
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+ return (fifo[0x0011] >> 2);
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+}
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+
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+void
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+nvdmakickoff(VGAscr *scr)
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+{
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+ if(nv.dmacurrent != nv.dmaput) {
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+ nv.dmaput = nv.dmacurrent;
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+ writeput(scr, nv.dmaput);
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+ }
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+}
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+
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+static void
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+nvdmanext(ulong data)
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+{
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+ nv.dmabase[nv.dmacurrent++] = data;
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+}
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+
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+void
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+nvdmawait(VGAscr *scr, int size)
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+{
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+ int dmaget;
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+
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+ size++;
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+
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+ while(nv.dmafree < size) {
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+ dmaget = readget(scr);
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+
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+ if(nv.dmaput >= dmaget) {
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+ nv.dmafree = nv.dmamax - nv.dmacurrent;
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+ if(nv.dmafree < size) {
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+ nvdmanext(0x20000000);
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+ if(dmaget <= SKIPS) {
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+ if (nv.dmaput <= SKIPS) /* corner case - will be idle */
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+ writeput(scr, SKIPS + 1);
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+ do { dmaget = readget(scr); }
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+ while(dmaget <= SKIPS);
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+ }
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+ writeput(scr, SKIPS);
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+ nv.dmacurrent = nv.dmaput = SKIPS;
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+ nv.dmafree = dmaget - (SKIPS + 1);
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+ }
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+ } else
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+ nv.dmafree = dmaget - nv.dmacurrent - 1;
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+ }
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+}
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+
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+
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+static void
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+nvdmastart(VGAscr *scr, ulong tag, int size)
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+{
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+ if (nv.dmafree <= size)
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+ nvdmawait(scr, size);
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+ nvdmanext((size << 18) | tag);
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+ nv.dmafree -= (size + 1);
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+}
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+
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+static void
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+waitforidle(VGAscr *scr)
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+{
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+ ulong* pgraph;
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+ int x;
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+
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+ pgraph = (void*)((uchar*)scr->mmio + Pgraph);
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+
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+ x = 0;
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+ while((readget(scr) != nv.dmaput) && x++ < 1000000)
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+ ;
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+ if(x >= 1000000)
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+ iprint("idle stat %lud put %d scr %#p pc %#p\n", readget(scr), nv.dmaput, scr, getcallerpc(&scr));
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+
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+ x = 0;
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+ while(pgraph[0x00000700/4] & 0x01 && x++ < 1000000)
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+ ;
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+
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+ if(x >= 1000000)
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+ iprint("idle stat %lud scrio %#p scr %#p pc %#p\n", *pgraph, scr->mmio, scr, getcallerpc(&scr));
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+}
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+
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+static void
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+nvresetgraphics(VGAscr *scr)
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+{
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+ ulong surfaceFormat, patternFormat, rectFormat, lineFormat;
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+ int pitch, i;
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+
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+ pitch = scr->gscreen->width*BY2WD;
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+
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+ /*
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+ * DMA is at the end of the virtual window,
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+ * but we might have cut it short when mapping it.
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+ */
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+ if(nv.dmabase == nil){
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+ if(scr->storage <= scr->apsize)
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+ nv.dmabase = (ulong*)((uchar*)scr->vaddr + scr->storage - 128*1024);
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+ else{
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+ nv.dmabase = (void*)vmap(scr->paddr + scr->storage - 128*1024, 128*1024);
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+ if(nv.dmabase == 0){
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+ hwaccel = 0;
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+ hwblank = 0;
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+ print("vmap nvidia dma failed\n");
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+ return;
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+ }
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+ }
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+ }
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+
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+ for(i=0; i<SKIPS; i++)
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+ nv.dmabase[i] = 0x00000000;
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+
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+ nv.dmabase[0x0 + SKIPS] = 0x00040000;
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+ nv.dmabase[0x1 + SKIPS] = 0x80000010;
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+ nv.dmabase[0x2 + SKIPS] = 0x00042000;
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+ nv.dmabase[0x3 + SKIPS] = 0x80000011;
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+ nv.dmabase[0x4 + SKIPS] = 0x00044000;
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+ nv.dmabase[0x5 + SKIPS] = 0x80000012;
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+ nv.dmabase[0x6 + SKIPS] = 0x00046000;
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+ nv.dmabase[0x7 + SKIPS] = 0x80000013;
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+ nv.dmabase[0x8 + SKIPS] = 0x00048000;
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+ nv.dmabase[0x9 + SKIPS] = 0x80000014;
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+ nv.dmabase[0xA + SKIPS] = 0x0004A000;
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+ nv.dmabase[0xB + SKIPS] = 0x80000015;
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+ nv.dmabase[0xC + SKIPS] = 0x0004C000;
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+ nv.dmabase[0xD + SKIPS] = 0x80000016;
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+ nv.dmabase[0xE + SKIPS] = 0x0004E000;
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+ nv.dmabase[0xF + SKIPS] = 0x80000017;
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+
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+ nv.dmaput = 0;
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+ nv.dmacurrent = 16 + SKIPS;
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+ nv.dmamax = 8191;
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+ nv.dmafree = nv.dmamax - nv.dmacurrent;
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|
|
+
|
|
|
+ switch(scr->gscreen->depth) {
|
|
|
+ case 32:
|
|
|
+ case 24:
|
|
|
+ surfaceFormat = SURFACE_FORMAT_DEPTH24;
|
|
|
+ patternFormat = PATTERN_FORMAT_DEPTH24;
|
|
|
+ rectFormat = RECT_FORMAT_DEPTH24;
|
|
|
+ lineFormat = LINE_FORMAT_DEPTH24;
|
|
|
+ break;
|
|
|
+ case 16:
|
|
|
+ case 15:
|
|
|
+ surfaceFormat = SURFACE_FORMAT_DEPTH16;
|
|
|
+ patternFormat = PATTERN_FORMAT_DEPTH16;
|
|
|
+ rectFormat = RECT_FORMAT_DEPTH16;
|
|
|
+ lineFormat = LINE_FORMAT_DEPTH16;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ surfaceFormat = SURFACE_FORMAT_DEPTH8;
|
|
|
+ patternFormat = PATTERN_FORMAT_DEPTH8;
|
|
|
+ rectFormat = RECT_FORMAT_DEPTH8;
|
|
|
+ lineFormat = LINE_FORMAT_DEPTH8;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ nvdmastart(scr, SURFACE_FORMAT, 4);
|
|
|
+ nvdmanext(surfaceFormat);
|
|
|
+ nvdmanext(pitch | (pitch << 16));
|
|
|
+ nvdmanext(0);
|
|
|
+ nvdmanext(0);
|
|
|
+
|
|
|
+ nvdmastart(scr, PATTERN_FORMAT, 1);
|
|
|
+ nvdmanext(patternFormat);
|
|
|
+
|
|
|
+ nvdmastart(scr, RECT_FORMAT, 1);
|
|
|
+ nvdmanext(rectFormat);
|
|
|
+
|
|
|
+ nvdmastart(scr, LINE_FORMAT, 1);
|
|
|
+ nvdmanext(lineFormat);
|
|
|
+
|
|
|
+ nvdmastart(scr, PATTERN_COLOR_0, 4);
|
|
|
+ nvdmanext(~0);
|
|
|
+ nvdmanext(~0);
|
|
|
+ nvdmanext(~0);
|
|
|
+ nvdmanext(~0);
|
|
|
+
|
|
|
+ nvdmastart(scr, ROP_SET, 1);
|
|
|
+ nvdmanext(0xCC);
|
|
|
+
|
|
|
+ nvdmakickoff(scr);
|
|
|
+ waitforidle(scr);
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+static int
|
|
|
+nvidiahwfill(VGAscr *scr, Rectangle r, ulong sval)
|
|
|
+{
|
|
|
+ nvdmastart(scr, RECT_SOLID_COLOR, 1);
|
|
|
+ nvdmanext(sval);
|
|
|
+
|
|
|
+ nvdmastart(scr, RECT_SOLID_RECTS(0), 2);
|
|
|
+ nvdmanext((r.min.x << 16) | r.min.y);
|
|
|
+ nvdmanext((Dx(r) << 16) | Dy(r));
|
|
|
+
|
|
|
+ //if ( (Dy(r) * Dx(r)) >= 512)
|
|
|
+ nvdmakickoff(scr);
|
|
|
+
|
|
|
+ waitforidle(scr);
|
|
|
+
|
|
|
+ return 1;
|
|
|
+}
|
|
|
+
|
|
|
+static int
|
|
|
+nvidiahwscroll(VGAscr *scr, Rectangle r, Rectangle sr)
|
|
|
+{
|
|
|
+ nvdmastart(scr, BLIT_POINT_SRC, 3);
|
|
|
+ nvdmanext((sr.min.y << 16) | sr.min.x);
|
|
|
+ nvdmanext((r.min.y << 16) | r.min.x);
|
|
|
+ nvdmanext((Dy(r) << 16) | Dx(r));
|
|
|
+
|
|
|
+ //if ( (Dy(r) * Dx(r)) >= 512)
|
|
|
+ nvdmakickoff(scr);
|
|
|
+
|
|
|
+ waitforidle(scr);
|
|
|
+
|
|
|
+ return 1;
|
|
|
+}
|
|
|
+
|
|
|
+void
|
|
|
+nvidiablank(VGAscr*, int blank)
|
|
|
+{
|
|
|
+ uchar seq1, crtc1A;
|
|
|
+
|
|
|
+ seq1 = vgaxi(Seqx, 1) & ~0x20;
|
|
|
+ crtc1A = vgaxi(Crtx, 0x1A) & ~0xC0;
|
|
|
+
|
|
|
+ if(blank){
|
|
|
+ seq1 |= 0x20;
|
|
|
+// crtc1A |= 0xC0;
|
|
|
+ crtc1A |= 0x80;
|
|
|
+ }
|
|
|
+
|
|
|
+ vgaxo(Seqx, 1, seq1);
|
|
|
+ vgaxo(Crtx, 0x1A, crtc1A);
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+nvidiadrawinit(VGAscr *scr)
|
|
|
+{
|
|
|
+ nvresetgraphics(scr);
|
|
|
+ scr->blank = nvidiablank;
|
|
|
+ hwblank = 1;
|
|
|
+ scr->fill = nvidiahwfill;
|
|
|
+ scr->scroll = nvidiahwscroll;
|
|
|
+}
|
|
|
+
|
|
|
+VGAdev vganvidiadev = {
|
|
|
+ "nvidia",
|
|
|
+
|
|
|
+ nvidiaenable,
|
|
|
+ nil,
|
|
|
+ nil,
|
|
|
+ nvidialinear,
|
|
|
+ nvidiadrawinit,
|
|
|
+};
|
|
|
+
|
|
|
+VGAcur vganvidiacur = {
|
|
|
+ "nvidiahwgc",
|
|
|
+
|
|
|
+ nvidiacurenable,
|
|
|
+ nvidiacurdisable,
|
|
|
+ nvidiacurload,
|
|
|
+ nvidiacurmove,
|
|
|
+};
|