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riscv: gets to the first print and dies

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Ronald G. Minnich 7 years ago
parent
commit
a27bab1ab7

+ 1 - 0
sys/include/libc.h

@@ -385,6 +385,7 @@ struct Lock {
 } Lock;
 
 extern int	_tas(int*);
+extern int	_tas32(int*);
 
 extern	void	lock(Lock*);
 extern	void	unlock(Lock*);

+ 13 - 0
sys/src/9/riscv/asm.c

@@ -18,6 +18,9 @@
 #include "dat.h"
 #include "fns.h"
 
+#undef DBG
+void msg(char *);
+#define DBG(fmt, ...) msg(fmt)
 /*
  * Address Space Map.
  * Low duty cycle.
@@ -156,12 +159,16 @@ asmalloc(uintmem addr, uintmem size, int type, int align)
 
 	DBG("asmalloc: %#P@%#P, type %d\n", size, addr, type);
 	lock(&asmlock);
+//msg("after lock\n");
 	for(pp = nil, assem = asmlist; assem != nil; pp = assem, assem = assem->next){
+//msg("loop\n");
 		if(assem->type != type)
 			continue;
 		a = assem->addr;
+//msg("loop 2\n");
 
 		if(addr != 0){
+//msg("loop 3\n");
 			/*
 			 * A specific address range has been given:
 			 *   if the current map entry is greater then
@@ -184,11 +191,13 @@ asmalloc(uintmem addr, uintmem size, int type, int align)
 			a = addr;
 		}
 
+//msg("loop 4\n");
 		if(align > 0)
 			a = ((a+align-1)/align)*align;
 		if(assem->addr+assem->size-a < size)
 			continue;
 
+//msg("loop 5\n");
 		o = assem->addr;
 		assem->addr = a+size;
 		assem->size -= a-o+size;
@@ -199,12 +208,16 @@ asmalloc(uintmem addr, uintmem size, int type, int align)
 			asmfreelist = assem;
 		}
 
+//msg("loop 6\n");
 		unlock(&asmlock);
+//msg("loop 7\n");
 		if(o != a)
 			asmfree(o, a-o, type);
 		return a;
 	}
+//msg("loop 8\n");
 	unlock(&asmlock);
+//msg("loop 9\n");
 
 	return 0;
 }

+ 5 - 1
sys/src/9/riscv/assembly.S

@@ -33,4 +33,8 @@ slim_setlabel:
 	SD	x2,16(a0)
 	RET
 
-	
+
+.globl rdtsc
+rdtsc:
+	RDCYCLE a0
+	RET

+ 0 - 7
sys/src/9/riscv/devarch.c

@@ -562,13 +562,6 @@ timerset(uint64_t x)
 //	apictimerset(x);
 }
 
-void
-cycles(uint64_t* t)
-{
-	panic("cycles");
-	*t = 0;
-}
-
 void
 delay(int millisecs)
 {

+ 5 - 19
sys/src/9/riscv/main.c

@@ -102,8 +102,11 @@ void bsp(void)
 	// probably pull in the one from coreboot for riscv.
 
 	consuartputs = puts;
+	msg("call asminit\n");
 	asminit();
+	msg("call fmtinit\n");
 	fmtinit();
+	msg("done fmtinit\n");
 	print("\nHarvey\n");
 
 	die("Completed hart for bsp OK!\n");
@@ -169,17 +172,6 @@ userpc(Ureg*u)
 }
 
 
-int tas32(void *_)
-{
-	panic("tas32");
-	return -1;
-}
-int      cas32(void*_, uint32_t __, uint32_t ___)
-{
-	panic((char *)__func__);
-	return -1;
-}
-
 void    exit(int _)
 {
 	panic((char *)__func__);
@@ -239,10 +231,9 @@ setregisters(Ureg*u, char*f, char*t, int amt)
 	panic((char *)__func__);
 }
 
-uint64_t rdtsc(void)
+void cycles(uint64_t *p)
 {
-	panic((char *)__func__);
-	return 0;
+	*p = rdtsc();
 }
 
 int islo(void)
@@ -251,11 +242,6 @@ int islo(void)
 	return 0;
 }
 
-void mfence(void)
-{
-	panic((char *)__func__);
-}
-
 uintptr_t
 dbgpc(Proc*p)
 {

+ 1 - 1
sys/src/libc/9sys/qlock.c

@@ -46,7 +46,7 @@ getqlp(void)
 			p = ql.x;
 		if(p == op)
 			abort();
-		if(_tas(&(p->inuse)) == 0){
+		if(_tas32(&(p->inuse)) == 0){
 			ql.p = p;
 			p->next = nil;
 			break;

+ 24 - 0
sys/src/libc/riscv/atomic.S

@@ -10,6 +10,13 @@ adec:
 	li		a1, -1
 	amoadd.w.aq	a0, a1, 0(a0)
 	ret
+
+/* This works fine either way as we are little endian. */
+/* boy we have a lot of names for this. I don't know how *that* happened. */
+.globl _tas32				/* int _tas32(int *); */
+_tas32:
+.globl tas32				/* int _tas32(int *); */
+tas32:
 .globl _tas				/* int _tas(int *); */
 _tas:
 	li           a1, 1
@@ -21,3 +28,20 @@ aswap:
 	amoswap.w.aq a0, a1, 0(a0)
 	ret
 
+.globl cas32
+// int	cas32(void* %rdi, uint32_t %esi, uint32_t %edx);
+// a0 holds address of memory location
+// a1 holds expected value
+// a2 holds desired value
+// v0 return value, 0 if successful, !0 otherwise
+cas32:
+	lr.w x16, (a0)  // Load original value
+	li x16, 1 # Preset return to fail
+	bne x17, a1, return # Doesn’t match, so fail
+	sc.w x16, a2, (a0) # Try to update
+return: jr ra
+
+.globl mfence
+mfence:
+	fence
+	ret