Plan 9 from Bell Labs 2010-09-01

sys/src/9/kw/l.s

@@ -738,12 +738,8 @@ TEXT splfhi(SB), $-4
 
 TEXT	_tas(SB), $-4
 	MOVW	R0,R1
-	BARRIERS
 	MOVW	$1,R0
 	SWPW	R0,(R1)			/* fix: deprecated in armv7 */
-	MOVW	R0, R3
-	BARRIERS
-	MOVW	R3, R0
 	RET
 
 //TEXT tas32(SB), 1, $-4

sys/src/9/kw/plug.words

@@ -18,7 +18,7 @@ page table entries need to be flushed or invalidated in l2.
 we arrange that device registers are uncached.
 
 be aware that cache operations act on cache lines (of CACHELINESZ
-bytes) as atomic units, so if you invalidate 4 caches of a cache line,
+bytes) as atomic units, so if you invalidate one word of a cache line,
 you invalidate the entire cache line, whether it's been written back
 (is clean) or not (is dirty).  mixed data structures with parts
 maintained by hardware and other parts by software are especially

sys/src/9/omap/archomap.c

@@ -16,6 +16,7 @@
 
 #include "../port/netif.h"
 #include "etherif.h"
+#include "../port/flashif.h"
 #include "usbehci.h"
 
 typedef struct L3agent L3agent;
@@ -245,7 +246,7 @@ log2(ulong n)
 	int i;
 
 	i = 31 - clz(n);
-	if (!ispow2(n) || n == 0)
+	if (n == 0 || !ispow2(n))
 		i++;
 	return i;
 }
@@ -1285,7 +1286,6 @@ chkmissing(void)
 	delay(20);
 }
 
-#ifdef USE_FLASH
 void
 archflashwp(Flash*, int)
 {
@@ -1301,11 +1301,14 @@ archflashreset(int bank, Flash *f)
 {
 	if(bank != 0)
 		return -1;
-	f->type = "nand";
+	/*
+	 * this is set up for the igepv2 board.
+	 * if the beagleboard ever works, we'll have to sort this out.
+	 */
+	f->type = "onenand";
 	f->addr = (void*)PHYSNAND;		/* mapped here by archreset */
 	f->size = 0;				/* done by probe */
 	f->width = 1;
 	f->interleave = 0;
 	return 0;
 }
-#endif

sys/src/9/omap/cache.v7.s

@@ -3,74 +3,77 @@
  * shared by l.s and rebootcode.s
  */
 
-TEXT cacheiinv(SB), 1, $-4			/* I invalidate */
+TEXT cacheiinv(SB), $-4				/* I invalidate */
 	MOVW	$0, R0
 	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvi), CpCACHEall /* ok on cortex */
 	BARRIERS
 	RET
 
 /*
- * set/way operators
+ * set/way operators, passed a suitable set/way value in R0.
  */
-
-TEXT cachedwb_sw(SB), 1, $-4
+TEXT cachedwb_sw(SB), $-4
 	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEsi
 	RET
 
-TEXT cachedwbinv_sw(SB), 1, $-4
+TEXT cachedwbinv_sw(SB), $-4
 	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEwbi), CpCACHEsi
 	RET
 
-TEXT cachedinv_sw(SB), 1, $-4
+TEXT cachedinv_sw(SB), $-4
 	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEinvd), CpCACHEsi
 	RET
 
 	/* set cache size select */
-TEXT setcachelvl(SB), 1, $-4
+TEXT setcachelvl(SB), $-4
 	MCR	CpSC, CpIDcssel, R0, C(CpID), C(CpIDid), 0
 	BARRIERS
 	RET
 
 	/* return cache sizes */
-TEXT getwayssets(SB), 1, $-4
+TEXT getwayssets(SB), $-4
 	MRC	CpSC, CpIDcsize, R0, C(CpID), C(CpIDid), 0
 	RET
 
 /*
- * l1 cache operations
+ * l1 cache operations.
+ * l1 and l2 ops are intended to be called from C, thus need save no
+ * caller's regs, only those we need to preserve across calls.
  */
 
-TEXT cachedwb(SB), 1, $-4
+TEXT cachedwb(SB), $-4
 	MOVW.W	R14, -8(R13)
 	MOVW	$cachedwb_sw(SB), R0
 	MOVW	$1, R8
 	BL	cacheall(SB)
 	MOVW.P	8(R13), R15
 
-TEXT cachedwbinv(SB), 1, $-4
+TEXT cachedwbinv(SB), $-4
 	MOVW.W	R14, -8(R13)
 	MOVW	$cachedwbinv_sw(SB), R0
 	MOVW	$1, R8
 	BL	cacheall(SB)
 	MOVW.P	8(R13), R15
 
-TEXT cachedinv(SB), 1, $-4
+TEXT cachedinv(SB), $-4
 	MOVW.W	R14, -8(R13)
 	MOVW	$cachedinv_sw(SB), R0
 	MOVW	$1, R8
 	BL	cacheall(SB)
 	MOVW.P	8(R13), R15
 
-TEXT cacheuwbinv(SB), 1, $-4
+TEXT cacheuwbinv(SB), $-4
 	MOVM.DB.W [R14], (R13)	/* save lr on stack */
 	MOVW	CPSR, R1
 	ORR	$(PsrDirq|PsrDfiq), R1, R0
 	MOVW	R0, CPSR	/* splhi */
 	BARRIERS
+	MOVM.DB.W [R1], (R13)	/* save R1 on stack */
 
 	BL	cachedwbinv(SB)
 	BL	cacheiinv(SB)
 
+	MOVM.IA.W (R13), [R1]	/* restore R1 */
 	MOVW	R1, CPSR
 	BARRIERS
 	MOVM.IA.W (R13), [R14]	/* restore lr */
@@ -80,40 +83,38 @@ TEXT cacheuwbinv(SB), 1, $-4
  * l2 cache operations
  */
 
-TEXT l2cacheuwb(SB), 1, $-4
+TEXT l2cacheuwb(SB), $-4
 	MOVW.W	R14, -8(R13)
 	MOVW	$cachedwb_sw(SB), R0
 	MOVW	$2, R8
 	BL	cacheall(SB)
 	MOVW.P	8(R13), R15
 
-TEXT l2cacheuwbinv(SB), 1, $-4
+TEXT l2cacheuwbinv(SB), $-4
 	MOVW.W	R14, -8(R13)
 	MOVW	CPSR, R1
 	ORR	$(PsrDirq|PsrDfiq), R1, R0
 	MOVW	R0, CPSR	/* splhi */
 	BARRIERS
+	MOVM.DB.W [R1], (R13)	/* save R1 on stack */
 
 	MOVW	$cachedwbinv_sw(SB), R0
 	MOVW	$2, R8
 	BL	cacheall(SB)
 	BL	l2cacheuinv(SB)
 
+	MOVM.IA.W (R13), [R1]	/* restore R1 */
 	MOVW	R1, CPSR
 	BARRIERS
 	MOVW.P	8(R13), R15
 
-TEXT l2cacheuinv(SB), 1, $-4
+TEXT l2cacheuinv(SB), $-4
 	MOVW.W	R14, -8(R13)
 	MOVW	$cachedinv_sw(SB), R0
 	MOVW	$2, R8
 	BL	cacheall(SB)
 	MOVW.P	8(R13), R15
 
-/*
- * initial translation by 5c, then massaged by hand.
- */
-
 /*
  * these shift values are for the Cortex-A8 L1 cache (A=2, L=6) and
  * the Cortex-A8 L2 cache (A=3, L=6).
@@ -125,21 +126,16 @@ TEXT l2cacheuinv(SB), 1, $-4
 #define L2WAYSH 29
 #define L2SETSH 6
 
-#define VARSTACK (8*4)		/* generous stack space for local variables */
-
-/* first argument (in R0) is the function to call in the innermost loop */
-/* second argument (in R8 when called from assembler) is cache level */
-TEXT cacheall+0(SB), 1, $-4
-//	MOVW	lvl+4(FP), R8	/* cache level */
-	MOVM.DB.W [R14,R1-R8], (R13) /* save regs on stack */
+/*
+ * callers are assumed to be the above l1 and l2 ops.
+ * R0 is the function to call in the innermost loop.
+ * R8 is the cache level (one-origin: 1 or 2).
+ *
+ * initial translation by 5c, then massaged by hand.
+ */
+TEXT cacheall+0(SB), $-4
 	MOVW	R0, R1		/* save argument for inner loop in R1 */
-
-	MOVW	CPSR, R0
-	MOVM.DB.W [R0], (R13)	/* push CPSR */
-
-	ORR	$(PsrDirq|PsrDfiq), R0
-	MOVW	R0, CPSR	/* splhi */
-	BARRIERS
+	SUB	$1, R8		/* convert cache level to zero origin */
 
 	/* we may not have the MMU on yet, so map R1 to PC's space */
 	BIC	$KSEGM,	R1	/* strip segment from address */
@@ -154,89 +150,61 @@ TEXT cacheall+0(SB), 1, $-4
 	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEwait
 	BARRIERS
 
-	SUB	$1, R8, R0	/* R0 = cache - 1 */
-	SLL	$1, R0		/* R0 = (cache - 1) << 1 */
-
-	/* set cache size select */
-	MCR	CpSC, CpIDcssel, R0, C(CpID), C(CpIDid), 0
+	MOVW	CPSR, R2
+	MOVM.DB.W [R2,R14], (SP) /* save regs on stack */
+	ORR	$(PsrDirq|PsrDfiq), R2
+	MOVW	R2, CPSR	/* splhi to make entire op atomic */
 	BARRIERS
 
+	/* get cache sizes */
+	SLL	$1, R8, R0	/* R0 = (cache - 1) << 1 */
+	MCR	CpSC, CpIDcssel, R0, C(CpID), C(CpIDid), 0 /* set cache size select */
+	BARRIERS
 	MRC	CpSC, CpIDcsize, R0, C(CpID), C(CpIDid), 0 /* get cache sizes */
 
 	/* compute # of ways and sets for this cache level */
 	SRA	$3, R0, R5	/* R5 (ways) = R0 >> 3 */
 	AND	$1023, R5	/* R5 = (R0 >> 3) & MASK(10) */
-	ADD	$1, R5		/* R5 = ((R0 >> 3) & MASK(10)) + 1 */
-	MOVW	R5, ways-20(SP)	/* ways = ((R0 >> 3) & MASK(10)) + 1 */
+	ADD	$1, R5		/* R5 (ways) = ((R0 >> 3) & MASK(10)) + 1 */
 
-	SRA	$13, R0, R3	/* R3 (sets) = R0 >> 13 */
-	AND	$32767, R3	/* R3 = (R0 >> 13) & MASK(15) */
-	ADD	$1, R3		/* R3 = ((R0 >> 13) & MASK(15)) + 1 */
-	MOVW	R3, sets-12(SP)	/* sets = ((R0 >> 13) & MASK(15)) + 1 */
+	SRA	$13, R0, R2	/* R2 = R0 >> 13 */
+	AND	$32767, R2	/* R2 = (R0 >> 13) & MASK(15) */
+	ADD	$1, R2		/* R2 (sets) = ((R0 >> 13) & MASK(15)) + 1 */
 
-	/* force writes to stack out to dram */
-	BARRIERS
-	MOVW	R13, R0
-	SUB	$VARSTACK, R0	/* move down past local variables (ways) */
-	BIC	$(CACHELINESZ-1), R0
-	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEse
-	ADD	$CACHELINESZ, R0
-	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEse
-	ADD	$CACHELINESZ, R0
-	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEse
-	ADD	$CACHELINESZ, R0
-	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEse
-	BARRIERS
-	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEwait
-	BARRIERS
+	/* precompute set/way shifts for inner loop */
+	CMP	$0, R8		/* cache == 1? */
+	MOVW.EQ	$L1WAYSH, R3 	/* yes */
+	MOVW.EQ	$L1SETSH, R4
+	MOVW.NE	$L2WAYSH, R3	/* no */
+	MOVW.NE	$L2SETSH, R4
 
 	/* iterate over ways */
 	MOVW	$0, R7		/* R7: way */
-	B	midtest
-middle:
-	ADD	$1, R7		/* way++ */
-midtest:
-	MOVW	ways-20(SP), R2	/* R2: ways */
-	CMP	R2, R7		/* way >= ways? */
-	BGE	ret		/* then done */
-
+outer:
 	/* iterate over sets */
 	MOVW	$0, R6		/* R6: set */
-	B	intest
 inner:
+	/* compute set/way register contents */
+	SLL	R3, R7, R0 	/* R0 = way << R3 (L?WAYSH) */
+	ORR	R8<<1, R0	/* R0 = way << L?WAYSH | (cache - 1) << 1 */
+	ORR	R6<<R4, R0 	/* R0 = way<<L?WAYSH | (cache-1)<<1 |set<<R4 */
+
+	BL	(R1)		/* call set/way operation with R0 */
+
 	ADD	$1, R6		/* set++ */
-intest:
-	MOVW	sets-12(SP), R5	/* R5: sets */
-	CMP	R5, R6		/* set >= sets? */
-	BGE	middle		/* then back to reinit of previous loop */
+	CMP	R2, R6		/* set >= sets? */
+	BLT	inner		/* no, do next set */
 
-	/* compute set/way register contents */
-	SUB	$1, R8, R4	/* R4 = cache - 1 */
-	CMP	$1, R8		/* cache == 1? */
-	SLL.EQ	$L1WAYSH, R7, R2 /* yes: R2 = way << L1WAYSH */
-	SLL.NE	$L2WAYSH, R7, R2 /* no:  R2 = way << L2WAYSH */
-	ORR	R4<<1, R2, R4	/* R4 = way << L?WAYSH | (cache - 1) << 1 */
-	ORR.EQ	R6<<L1SETSH, R4, R0 /* R0=way<<L1WAYSH|(cache-1)<<1|set<<L1SETSH */
-	ORR.NE	R6<<L2SETSH, R4, R0 /* R0=way<<L2WAYSH|(cache-1)<<1|set<<L2SETSH */
-
-	SUB	$VARSTACK, R13	/* move sp down past local variables (ways) */
-	/* must not use addresses relative to (SP) from here */
-	BL	(R1)		/* call asm to do something with R0 */
-	BARRIERS		/* make sure it has executed */
-	ADD	$VARSTACK, R13	/* restore sp */
-	/* may again use addresses relative to (SP) from here */
-
-	B	inner
-
-ret:
-	/* drain write buffers */
-	BARRIERS
-	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEwait
+	ADD	$1, R7		/* way++ */
+	CMP	R5, R7		/* way >= ways? */
+	BLT	outer		/* no, do next way */
+
+	MOVM.IA.W (SP), [R2,R14] /* restore regs */
+	MOVW	R2, CPSR	/* splx */
 	BARRIERS
 
-	MOVM.IA.W (R13), [R0]	/* pop CPSR */
-	MOVM.IA.W (R13), [R14,R1-R8] /* restore regs */
-	MOVW	R0, CPSR
+	/* drain write buffers */
+	MCR	CpSC, 0, R0, C(CpCACHE), C(CpCACHEwb), CpCACHEwait
 	BARRIERS
 	RET
 

sys/src/9/omap/coproc.c

@@ -22,12 +22,10 @@ enum {
 void
 cpwr(int cp, int op1, int crn, int crm, int op2, ulong val)
 {
-	int s;
 	volatile ulong instr[2];
 	void *pcaddr;
 	void (*fp)(ulong);
 
-	s = splhi();
 	op1 &= 7;
 	op2 &= 7;
 	crn &= 017;
@@ -37,7 +35,6 @@ cpwr(int cp, int op1, int crn, int crm, int op2, ulong val)
 	instr[0] = 0xee000010 |
 		op1 << 21 | crn << 16 | cp << 8 | op2 << 5 | crm;
 	instr[1] = Retinst;
-	coherence();
 
 	pcaddr = (void *)MAP2PCSPACE(instr, getcallerpc(&cp));
 	cachedwbse(pcaddr, sizeof instr);
@@ -46,7 +43,6 @@ cpwr(int cp, int op1, int crn, int crm, int op2, ulong val)
 	fp = (void (*)(ulong))pcaddr;
 	(*fp)(val);
 	coherence();
-	splx(s);
 }
 
 void
@@ -58,13 +54,10 @@ cpwrsc(int op1, int crn, int crm, int op2, ulong val)
 ulong
 cprd(int cp, int op1, int crn, int crm, int op2)
 {
-	int s;
-	ulong res;
 	volatile ulong instr[2];
 	void *pcaddr;
 	ulong (*fp)(void);
 
-	s = splhi();
 	op1 &= 7;
 	op2 &= 7;
 	crn &= 017;
@@ -76,16 +69,13 @@ cprd(int cp, int op1, int crn, int crm, int op2)
 	instr[0] = 0xee100010 |
 		op1 << 21 | crn << 16 | cp << 8 | op2 << 5 | crm;
 	instr[1] = Retinst;
-	coherence();
 
 	pcaddr = (void *)MAP2PCSPACE(instr, getcallerpc(&cp));
 	cachedwbse(pcaddr, sizeof instr);
 	cacheiinv();
 
 	fp = (ulong (*)(void))pcaddr;
-	res = (*fp)();
-	splx(s);
-	return res;
+	return (*fp)();
 }
 
 ulong
@@ -99,13 +89,10 @@ cprdsc(int op1, int crn, int crm, int op2)
 ulong
 fprd(int fpreg)
 {
-	int s;
-	ulong res;
 	volatile ulong instr[2];
 	void *pcaddr;
 	ulong (*fp)(void);
 
-	s = splhi();
 	fpreg &= 017;
 	/*
 	 * VMRS.  return value will be in R0, which is convenient.
@@ -120,20 +107,16 @@ fprd(int fpreg)
 	cacheiinv();
 
 	fp = (ulong (*)(void))pcaddr;
-	res = (*fp)();
-	splx(s);
-	return res;
+	return (*fp)();
 }
 
 void
 fpwr(int fpreg, ulong val)
 {
-	int s;
 	volatile ulong instr[2];
 	void *pcaddr;
 	void (*fp)(ulong);
 
-	s = splhi();
 	fpreg &= 017;
 	/* VMSR.  Rt will be R0. */
 	instr[0] = 0xeee00a10 | fpreg << 16 | 0 << 12;
@@ -147,5 +130,4 @@ fpwr(int fpreg, ulong val)
 	fp = (void (*)(ulong))pcaddr;
 	(*fp)(val);
 	coherence();
-	splx(s);
 }

sys/src/9/omap/dat.h

@@ -1,5 +1,5 @@
-#define LASTRESORT lastresortprint	/* for ../port/devcons.c */
-#define CRUDEPRINT serialputs		/* for ../port/devcons.c */
+#define LASTRESORT lastresortprint	/* for ./devcons.c */
+#define CRUDEPRINT serialputs		/* for ./devcons.c */
 
 /*
  * Time.

sys/src/9/omap/l.s

@@ -322,7 +322,7 @@ _ptrdbl:
 	/* ...and jump to it */
 //	MOVW	R2, R15				/* software reboot */
 _limbo:						/* should not get here... */
-	BL	_idlehands(SB)
+	BL	idlehands(SB)
 	B	_limbo				/* ... and can't get out */
 	BL	_div(SB)			/* hack to load _div, etc. */
 
@@ -339,7 +339,7 @@ TEXT _r15warp(SB), 1, $-4
  * l2 functions are unnecessary.
  */
 
-TEXT cachedwbse(SB), 1, $-4			/* D writeback SE */
+TEXT cachedwbse(SB), $-4			/* D writeback SE */
 	MOVW	R0, R2
 
 	MOVW	CPSR, R3			/* splhi */
@@ -359,7 +359,7 @@ _dwbse:
 	BGT	_dwbse
 	B	_wait
 
-TEXT cachedwbinvse(SB), 1, $-4			/* D writeback+invalidate SE */
+TEXT cachedwbinvse(SB), $-4			/* D writeback+invalidate SE */
 	MOVW	R0, R2
 
 	MOVW	CPSR, R3			/* splhi */
@@ -387,7 +387,7 @@ _wait:						/* drain write buffer */
 	BARRIERS
 	RET
 
-TEXT cachedinvse(SB), 1, $-4			/* D invalidate SE */
+TEXT cachedinvse(SB), $-4			/* D invalidate SE */
 	MOVW	R0, R2
 
 	MOVW	CPSR, R3			/* splhi */
@@ -428,7 +428,7 @@ TEXT mmudisable(SB), 1, $-4
  * If one of these MCR instructions crashes or hangs the machine,
  * check your Level 1 page table (at TTB) closely.
  */
-TEXT mmuinvalidate(SB), 1, $-4			/* invalidate all */
+TEXT mmuinvalidate(SB), $-4			/* invalidate all */
 	BARRIERS
 	MOVW	CPSR, R2
 	ORR	$(PsrDirq|PsrDfiq), R2, R3	/* interrupts off */
@@ -442,7 +442,7 @@ TEXT mmuinvalidate(SB), 1, $-4			/* invalidate all */
 	BARRIERS
 	RET
 
-TEXT mmuinvalidateaddr(SB), 1, $-4		/* invalidate single entry */
+TEXT mmuinvalidateaddr(SB), $-4			/* invalidate single entry */
 	MCR	CpSC, 0, R0, C(CpTLB), C(CpTLBinvu), CpTLBinvse
 	BARRIERS
 	RET
@@ -515,7 +515,7 @@ TEXT splhi(SB), 1, $-4
 	MOVW	R3, R0				/* must return old CPSR */
 	RET
 
-TEXT spllo(SB), 1, $-4
+TEXT spllo(SB), 1, $-4			/* start marker for devkprof.c */
 	MOVW	CPSR, R3
 	BIC	$PsrDirq, R3, R1
 	MOVW	R1, CPSR
@@ -535,7 +535,7 @@ TEXT splx(SB), 1, $-4
 	MOVW	R3, R0				/* must return old CPSR */
 	RET
 
-TEXT spldone(SB), 1, $0				/* marker for devkprof.c */
+TEXT spldone(SB), 1, $0				/* end marker for devkprof.c */
 	RET
 
 TEXT islo(SB), 1, $-4
@@ -546,15 +546,11 @@ TEXT islo(SB), 1, $-4
 
 TEXT	_tas(SB), $-4
 	MOVW	R0,R1
-	BARRIERS
 	MOVW	$1,R0
 	SWPW	R0,(R1)			/* fix: deprecated in armv7 */
-	MOVW	R0, R3
-	BARRIERS
-	MOVW	R3, R0
 	RET
 
-TEXT clz(SB), 1, $-4
+TEXT clz(SB), $-4
 	CLZ(0, 0)			/* 0 is R0 */
 	RET
 
@@ -574,12 +570,12 @@ TEXT getcallerpc(SB), 1, $-4
 	MOVW	0(R13), R0
 	RET
 
-TEXT _idlehands(SB), 1, $-4
+TEXT idlehands(SB), $-4
 	BARRIERS
 	WFI
 	RET
 
-TEXT coherence(SB), 1, $-4
+TEXT coherence(SB), $-4
 	BARRIERS
 	RET
 

sys/src/9/omap/trap.c

@@ -726,14 +726,6 @@ dumpregs(Ureg* ureg)
 	dumpscr();
 }
 
-void
-idlehands(void)
-{
-	extern void _idlehands(void);
-
-	_idlehands();
-}
-
 vlong
 probeaddr(uintptr addr)
 {