Browse Source

Plan 9 from Bell Labs 2010-02-05

David du Colombier 9 years ago
parent
commit
cbd541c823

+ 9 - 4
sys/lib/scsicodes

@@ -1,7 +1,12 @@
-# hget http://www.t10.org/lists/asc-num.htm |
-#   grep '^[0-9]' |tr -d '
' |tr A-Z a-z |
-#   sed 's/(..)\/(..)  ..............  (.*)/\1\2 \3/' > scsicodes
-# (and then put this header back)
+#!/bin/rc
+{
+	sed '/^$/q' scsicodes
+	hget http://www.t10.org/lists/asc-num.htm |
+		grep '^[0-9]' |tr -d '
' |tr A-Z a-z |
+		sed 's/(..)\/(..)  ..............  (.*)/\1\2 \3/'
+} > nscsicodes && mv nscsicodes scsicodes
+exit
+
 0000 no additional sense information
 0001 filemark detected
 0002 end-of-partition/medium detected

+ 14 - 14
sys/src/9/kw/etherkw.c

@@ -362,29 +362,29 @@ struct Gbereg {
 	ulong	smi;			/* serial mgmt. interface */
 	ulong	euda;			/* ether default address */
 	ulong	eudid;			/* ether default id */
-	ulong	_pad0[PAD(0x80, 0xc)];
+	uchar	_pad0[0x80-0x10];
 
 	ulong	euirq;			/* interrupt cause */
 	ulong	euirqmask;		/* interrupt mask */
-	ulong	_pad1[PAD(0x94, 0x84)];
+	uchar	_pad1[0x94-0x88];
 
 	ulong	euea;			/* error address */
 	ulong	euiae;			/* internal error address */
-	ulong	_pad2[PAD(0xb0, 0x98)];
+	uchar	_pad2[0xb0-0x9c];
 
 	ulong	euc;			/* control */
-	ulong	_pad3[PAD(0x200, 0xb0)];
+	uchar	_pad3[0x200-0xb4];
 
 	struct {
 		ulong	base;		/* window base */
 		ulong	size;		/* window size */
 	} base[6];
-	ulong	_pad4[PAD(0x280, 0x22c)];
+	uchar	_pad4[0x280-0x230];
 
 	ulong	harr[4];		/* high address remap */
 	ulong	bare;			/* base address enable */
 	ulong	epap;			/* port access protect */
-	ulong	_pad5[PAD(0x400, 0x294)];
+	uchar	_pad5[0x400-0x298];
 
 	ulong	portcfg;		/* port configuration */
 	ulong	portcfgx;		/* port config. extend */
@@ -424,15 +424,15 @@ struct Gbereg {
 	ulong	pxofc;			/* port overrun frame counter */
 	ulong	_pad12[2];
 	ulong	piae;			/* port internal address error */
-	ulong	_pad13[PAD(0x4bc, 0x494)];
+	uchar	_pad13[0x4bc-0x498];
 	ulong	etherprio;		/* ether type priority */
-	ulong	_pad14[PAD(0x4dc, 0x4bc)];
+	uchar	_pad14[0x4dc-0x4c0];
 	ulong	tqfpc;			/* tx queue fixed priority config. */
 	ulong	pttbrc;			/* port tx token-bucket rate config. */
 	ulong	tqc1;			/* tx queue command 1 */
 	ulong	pmtu;			/* port maximum transmit unit */
 	ulong	pmtbs;			/* port maximum token bucket size */
-	ulong	_pad15[PAD(0x600, 0x4ec)];
+	uchar	_pad15[0x600-0x4f0];
 
 	struct {
 		ulong	_pad[3];
@@ -440,10 +440,10 @@ struct Gbereg {
 	} crdp[8];
 	ulong	rqc;			/* rx queue command */
 	ulong	tcsdp;			/* phys. addr.: cur. tx desc. ptr */
-	ulong	_pad16[PAD(0x6c0, 0x684)];
+	uchar	_pad16[0x6c0-0x688];
 
 	ulong	tcqdp[8];		/* phys. addr.: cur. tx q. desc. ptr */
-	ulong	_pad17[PAD(0x700, 0x6dc)];
+	uchar	_pad17[0x700-0x6e0];
 
 	struct {
 		ulong	tbctr;		/* queue tx token-bucket counter */
@@ -452,7 +452,7 @@ struct Gbereg {
 		ulong	_pad;
 	} tq[8];
 	ulong	pttbc;			/* port tx token-bucket counter */
-	ulong	_pad18[PAD(0x7a8, 0x780)];
+	uchar	_pad18[0x7a8-0x784];
 
 	ulong	ipg2;			/* tx queue ipg */
 	ulong	_pad19[3];
@@ -463,11 +463,11 @@ struct Gbereg {
 	ulong	ltap;			/* low token in async packet */
 	ulong	_pad21;
 	ulong	ts;			/* tx speed */
-	ulong	_pad22[PAD(0x1000, 0x7d0)];
+	uchar	_pad22[0x1000-0x7d4];
 
 	/* mac mib counters: statistics */
 	Mibstats;
-	ulong	_pad23[PAD(0x1400, 0x107c)];
+	uchar	_pad23[0x1400-0x1080];
 
 	/* multicast filtering; each byte: Qno<<1 | Pass */
 	ulong	dfsmt[64];	/* dest addr filter special m'cast table */

+ 1 - 1
sys/src/9/kw/ethermii.c

@@ -44,7 +44,7 @@ mii(Mii* mii, int mask)
 		/*
 		 * for some reason, phyno 18 (ether1's) doesn't report an
 		 * oui of 0x005043 (Marvell), but rather 0xFFFFF.
-		 * for now, workaround it by knowing that 18 is a valid PHY.
+		 * for now, work around it by knowing that 18 is a valid PHY.
 		 */
 		if(oui == 0xFFFFF || oui == 0)
 			if (phyno != 18)

+ 0 - 3
sys/src/9/kw/io.h

@@ -198,9 +198,6 @@ struct Pcidev
  * Kirkwood stuff
  */
 
-/* weird padding macro */
-#define PAD(next, last)	(((next) - sizeof(ulong) - (last)) / sizeof(ulong))
-
 enum {
 	Regbase		= 0xf1000000,	/* PHYSIO in mem.h */
 	AddrSDramc	= Regbase+0x01400,

+ 142 - 51
sys/src/9/kw/usbehci.c

@@ -383,6 +383,40 @@ union Ed
 	uchar	align[Align];
 };
 
+typedef struct Kwusb Kwusb;
+typedef struct Usbwin Usbwin;
+struct Kwusb {			/* at offset 0x300 from Addrusb */
+	ulong	bcs;		/* bridge ctl & sts */
+	uchar	_pad0[0x310-0x304];
+
+	ulong	bic;		/* bridge intr. cause */
+	ulong	bim;		/* bridge intr. mask */
+	ulong	_pad1;
+	ulong	bea;		/* bridge error addr. */
+	struct Usbwin {
+		ulong	ctl;
+		ulong	base;
+		ulong	_pad2[2];
+	} win[4];
+	ulong	phycfg;		/* phy config. */
+	uchar	_pad3[0x400-0x364];
+
+	ulong	pwrctl;		/* power control */
+	uchar	_pad4[0x410-0x404];
+	ulong	phypll;		/* phy pll control */
+	uchar	_pad5[0x420-0x414];
+	ulong	phytxctl;	/* phy transmit control */
+	uchar	_pad6[0x430-0x424];
+	ulong	phyrxctl;	/* phy receive control */
+	uchar	_pad7[0x440-0x434];
+	ulong	phyivref;	/* phy ivref control */
+};
+
+enum {
+	/* Kwusb->win[i].ctl bits */
+	Winenable	= 1<<0,
+};
+
 #define diprint		if(debug || iso->debug)print
 #define ddiprint	if(debug>1 || iso->debug>1)print
 #define dqprint		if(debug || (qh->io && qh->io->debug))print
@@ -3176,23 +3210,82 @@ init(Hci *hp)
 
 }
 
+#define WINTARG(ctl)	(((ctl) >> 4) & 017)
+#define WINATTR(ctl)	(((ctl) >> 8) & 0377)
+#define WIN64KSIZE(ctl)	(((ctl) >> 16) + 1)
+
+#define SIZETO64KSIZE(size) ((size) / (64*1024) - 1)
+
 static void
-ehcireset(Ctlr *ctlr)
+addrmapdump(void)
 {
+	int i;
+	ulong ctl, targ, attr, size64k;
+	Kwusb *map;
+	Usbwin *win;
+
+	map = (Kwusb *)(Addrusb + 0x300);
+	for (i = 0; i < nelem(map->win); i++) {
+		win = &map->win[i];
+		ctl = win->ctl;
+		if (ctl & Winenable) {
+			targ = WINTARG(ctl);
+			attr = WINATTR(ctl);
+			size64k = WIN64KSIZE(ctl);
+			print("usb address map window %d: "
+				"targ %ld attr %#lux size %,ld addr %#lux\n",
+				i, targ, attr, size64k * 64*1024, win->base);
+		}
+	}
+}
+
+/* assumes ctlr is ilocked */
+static void
+ctlrreset(Ctlr *ctlr)
+{
+	int i;
 	Eopio *opio;
+
+	opio = ctlr->opio;
+	opio->cmd |= Chcreset;
+	/* wait for it to come out of reset */
+	for(i = 0; i < 100 && opio->cmd & Chcreset; i++)
+		delay(1);
+	if(i >= 100)
+		print("ehci %#p controller reset timed out\n", ctlr->capio);
+	/*
+	 * Marvell errata FE-USB-340 workaround: 1 << 4 magic:
+	 * disable streaming.  Magic 3 (usb host mode) from the linux driver
+	 * makes it work.  Ick.
+	 */
+	opio->usbmode |= 1 << 4 | 3;
+	coherence();
+}
+
+static void
+setaddrwin(Kwusb *kw, int win, int attr, ulong base)
+{
+	/* target 0, size 256MB */
+	kw->win[win].ctl = Winenable | 0 << 4 | attr << 8 |
+		SIZETO64KSIZE(256*MB) << 16;
+	kw->win[win].base = base;
+}
+
+static void
+ehcireset(Ctlr *ctlr)
+{
 	int i;
-	ulong val;
-	ulong *reg;
+	ulong v;
+	Eopio *opio;
+	Kwusb *kw;
 
 	ilock(ctlr);
 	dprint("ehci %#p reset\n", ctlr->capio);
 	opio = ctlr->opio;
 
-	/*
-	 * Turn off legacy mode. Some controllers won't
-	 * interrupt us as expected otherwise.
-	 */
-	ehcirun(ctlr, 0);
+	kw = (Kwusb *)(Addrusb + 0x300);
+	kw->bic = kw->bim = 0;
+	ctlrreset(ctlr);
 
 	/*
 	 * clear high 32 bits of address signals if it's 64 bits capable.
@@ -3203,15 +3296,6 @@ ehcireset(Ctlr *ctlr)
 		opio->seg = 0;
 	}
 
-	opio->cmd |= Chcreset;	/* controller reset */
-	for(i = 0; i < 100; i++){
-		if((opio->cmd & Chcreset) == 0)
-			break;
-		delay(1);
-	}
-	if(i == 100)
-		print("ehci %#p controller reset timed out\n", ctlr->capio);
-
 	/* requesting more interrupts per µframe may miss interrupts */
 	opio->cmd |= Citc8;		/* 1 intr. per ms */
 	switch(opio->cmd & Cflsmask){
@@ -3230,45 +3314,60 @@ ehcireset(Ctlr *ctlr)
 	dprint("ehci: %d frames\n", ctlr->nframes);
 
 	/*
-	 * Marvell errata FE-USB-340 workaround: 1 << 4 magic.
-	 * Magic 3 from the linux driver makes it work.  Ick.
+	 * set up the USB address map (bridge address decoding)
 	 */
-	opio->usbmode |= 1 << 4 | 3;
+	for (i = 0; i < nelem(kw->win); i++)
+		kw->win[i].ctl = kw->win[i].base = 0;
+	coherence();
+
+	setaddrwin(kw, 0, 0xe, 0);		/* attr 0xe: sdram cs 0 */
+	setaddrwin(kw, 1, 0xd, 256*MB);		/* attr 0xd: sdram cs 1 */
+	setaddrwin(kw, 2, 0xe, (ulong)KADDR(0));      /* attr 0xe: sdram cs 0 */
+	setaddrwin(kw, 3, 0xd, (ulong)KADDR(256*MB)); /* attr 0xd: sdram cs 1 */
+	coherence();
+
+	if (kw->bcs & (1 << 4))
+		print("usb BS bit is one, thus no byte swapping\n");
+	else
+		print("usb BS bit is zero, thus byte swapping\n");
+	addrmapdump();				/* verify sanity */
+
+	kw->pwrctl |= 1 << 0 | 1 << 1;		/* Pu | PuPll */
 	coherence();
 
 	/*
 	 * Marvell guideline GL-USB-160.
-	 * uses publically-undocumented registers.
 	 */
-	reg = (ulong *)(Regbase + 0x50410);
-	*reg |= 1 << 21;
+	kw->phypll |= 1 << 21;		/* VCOCAL_START: PLL calibration */
 	coherence();
 	microdelay(100);
-	*reg &= ~(1 << 21);
+	kw->phypll &= ~(1 << 21);
 
-	reg = (ulong *)(Regbase + 0x50420);
-	val = *reg;
-	val &= ~(017 << 27 | 7);
-	val |= 1 << 26 | 1 << 12 | 4;	/* 4 for 6281-A0 (3 for A1) */
-	*reg = val;
+	v = kw->phytxctl & ~(017 << 27 | 7);	/* REG_EXT_FS_RCALL & AMP_2_0 */
+	/*
+	 * AMP_2_0 = 4 for 6281-A0 (but 3 for A1).
+	 * also set REG_EXT_FS_RCALL_EN | REG_RCAL_START.
+	 */
+	kw->phytxctl = v | 1 << 26 | 1 << 12 | 4;
 	coherence();
 	microdelay(100);
-	val &= ~(1 << 12);
-	*reg = val;
+	kw->phytxctl &= ~(1 << 12);
 
-	reg = (ulong *)(Regbase + 0x50430);
-	val = *reg;
-	val &= ~(3 << 2 | 017 << 4);
-	val |= 1 << 2 | 8 << 4;
-	*reg = val;
+	v = kw->phyrxctl & ~(3 << 2 | 017 << 4); /* LPF_COEF_1_0 & SQ_THRESH_3_0 */
+	kw->phyrxctl = v | 1 << 2 | 8 << 4;
 
-	reg = (ulong *)(Regbase + 0x50440);
-	val = *reg;
-	val &= ~(3 << 8);
-	val |= 1 << 8;			/* 1 for 6281-A0; 3 for A1 */
-	*reg = val;
+	v = kw->phyivref & ~(3 << 8);		/* TXVDD12 */
+	kw->phyivref = v | 1 << 8;		/* 1 for 6281-A0; 3 for A1 */
 
 	coherence();
+
+	/*
+	 * Turn off legacy mode.  Some controllers won't
+	 * interrupt us as expected otherwise.
+	 */
+	ehcirun(ctlr, 0);
+	ctlrreset(ctlr);
+
 	iunlock(ctlr);
 }
 
@@ -3281,23 +3380,15 @@ setdebug(Hci*, int d)
 static void
 shutdown(Hci *hp)
 {
-	int i;
 	Ctlr *ctlr;
 	Eopio *opio;
 
 	ctlr = hp->aux;
 	ilock(ctlr);
-	opio = ctlr->opio;
-	opio->cmd |= Chcreset;		/* controller reset */
-	for(i = 0; i < 100; i++){
-		if((opio->cmd & Chcreset) == 0)
-			break;
-		delay(1);
-	}
-	if(i >= 100)
-		print("ehci %#p controller reset timed out\n", ctlr->capio);
+	ctlrreset(ctlr);
 	delay(100);
 	ehcirun(ctlr, 0);
+	opio = ctlr->opio;
 	opio->frbase = 0;
 	iunlock(ctlr);
 }

+ 1 - 0
sys/src/cmd/usb/serial/ftdi.c

@@ -15,6 +15,7 @@
 Cinfo ftinfo[] = {
 	{ FTVid, FTACTZWAVEDid },
 	{ FTSheevaVid, FTSheevaDid },
+	{ FTVid, FTOpenrdDid },
 	{ FTVid, FTIRTRANSDid },
 	{ FTVid, FTIPLUSDid },
 	{ FTVid, FTSIODid },

+ 4 - 3
sys/src/cmd/usb/serial/ftdi.h

@@ -1,9 +1,10 @@
 enum {
 	/* used by devices which don't provide their own Vid */
-	FTVid = 0x0403,
+	FTVid		= 0x0403,
+	FTOpenrdDid	= 0x9E90,
 
-	FTSheevaVid = 0x9E88,
-	FTSheevaDid = 0x9E8F,
+	FTSheevaVid	= 0x9E88,
+	FTSheevaDid	= 0x9E8F,
 
 	FTSIODid	= 0x8372,	/* Product Id SIO appl'n of 8U100AX */
 	FT8U232AMDid	= 0x6001, 	/* Similar device to SIO above */