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@@ -0,0 +1,1623 @@
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+/*
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+ * bootstrap driver for
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+ * Intel RS-82543GC Gigabit Ethernet Controller
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+ * as found on the Intel PRO/1000[FT] Server Adapter.
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+ * The older non-[FT] cards use the 82542 (LSI L2A1157) chip; no attempt
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+ * is made to handle the older chip although it should be possible.
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+ *
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+ * updated just enough to cope with the
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+ * Intel 8254[340]NN Gigabit Ethernet Controller
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+ * as found on the Intel PRO/1000 series of adapters:
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+ * 82543GC Intel PRO/1000 T
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+ * 82544EI Intel PRO/1000 XT
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+ * 82540EM Intel PRO/1000 MT
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+ *
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+ * The datasheet is not very clear about running on a big-endian system
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+ * and this driver assumes little-endian throughout.
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+ * To do:
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+ * GMII/MII
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+ * check recovery from receive no buffers condition
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+ * automatic ett adjustment
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+ */
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+#include "u.h"
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+#include "lib.h"
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+#include "mem.h"
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+#include "dat.h"
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+#include "fns.h"
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+#include "io.h"
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+
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+#include "etherif.h"
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+#include "ethermii.h"
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+
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+/* compatibility with cpu kernels */
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+#define iallocb allocb
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+#ifndef CACHELINESZ
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+#define CACHELINESZ 32 /* pentium & later */
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+#endif
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+
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+/* from pci.c */
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+enum
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+{ /* command register (pcidev->pcr) */
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+ IOen = (1<<0),
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+ MEMen = (1<<1),
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+ MASen = (1<<2),
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+ MemWrInv = (1<<4),
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+ PErrEn = (1<<6),
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+ SErrEn = (1<<8),
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+};
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+enum {
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+ Ctrl = 0x00000000, /* Device Control */
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+ Status = 0x00000008, /* Device Status */
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+ Eecd = 0x00000010, /* EEPROM/Flash Control/Data */
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+ Ctrlext = 0x00000018, /* Extended Device Control */
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+ Mdic = 0x00000020, /* MDI Control */
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+ Fcal = 0x00000028, /* Flow Control Address Low */
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+ Fcah = 0x0000002C, /* Flow Control Address High */
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+ Fct = 0x00000030, /* Flow Control Type */
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+ Icr = 0x000000C0, /* Interrupt Cause Read */
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+ Ics = 0x000000C8, /* Interrupt Cause Set */
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+ Ims = 0x000000D0, /* Interrupt Mask Set/Read */
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+ Imc = 0x000000D8, /* Interrupt mask Clear */
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+ Rctl = 0x00000100, /* Receive Control */
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+ Fcttv = 0x00000170, /* Flow Control Transmit Timer Value */
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+ Txcw = 0x00000178, /* Transmit Configuration Word */
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+ Tctl = 0x00000400, /* Transmit Control */
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+ Tipg = 0x00000410, /* Transmit IPG */
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+ Tbt = 0x00000448, /* Transmit Burst Timer */
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+ Ait = 0x00000458, /* Adaptive IFS Throttle */
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+ Fcrtl = 0x00002160, /* Flow Control RX Threshold Low */
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+ Fcrth = 0x00002168, /* Flow Control Rx Threshold High */
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+ Rdbal = 0x00002800, /* Rdesc Base Address Low */
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+ Rdbah = 0x00002804, /* Rdesc Base Address High */
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+ Rdlen = 0x00002808, /* Receive Descriptor Length */
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+ Rdh = 0x00002810, /* Receive Descriptor Head */
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+ Rdt = 0x00002818, /* Receive Descriptor Tail */
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+ Rdtr = 0x00002820, /* Receive Descriptor Timer Ring */
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+ Rxdctl = 0x00002828, /* Receive Descriptor Control */
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+ Radv = 0x0000282C, /* Receive Interrupt Absolute Delay Timer */
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+ Txdmac = 0x00003000, /* Transfer DMA Control */
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+ Ett = 0x00003008, /* Early Transmit Control */
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+ Tdbal = 0x00003800, /* Tdesc Base Address Low */
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+ Tdbah = 0x00003804, /* Tdesc Base Address High */
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+ Tdlen = 0x00003808, /* Transmit Descriptor Length */
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+ Tdh = 0x00003810, /* Transmit Descriptor Head */
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+ Tdt = 0x00003818, /* Transmit Descriptor Tail */
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+ Tidv = 0x00003820, /* Transmit Interrupt Delay Value */
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+ Txdctl = 0x00003828, /* Transmit Descriptor Control */
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+ Tadv = 0x0000382C, /* Transmit Interrupt Absolute Delay Timer */
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+
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+ Statistics = 0x00004000, /* Start of Statistics Area */
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+ Gorcl = 0x88/4, /* Good Octets Received Count */
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+ Gotcl = 0x90/4, /* Good Octets Transmitted Count */
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+ Torl = 0xC0/4, /* Total Octets Received */
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+ Totl = 0xC8/4, /* Total Octets Transmitted */
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+ Nstatistics = 64,
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+
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+ Rxcsum = 0x00005000, /* Receive Checksum Control */
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+ Mta = 0x00005200, /* Multicast Table Array */
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+ Ral = 0x00005400, /* Receive Address Low */
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+ Rah = 0x00005404, /* Receive Address High */
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+ Manc = 0x00005820, /* Management Control */
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+};
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+
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+enum { /* Ctrl */
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+ Bem = 0x00000002, /* Big Endian Mode */
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+ Prior = 0x00000004, /* Priority on the PCI bus */
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+ Lrst = 0x00000008, /* Link Reset */
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+ Asde = 0x00000020, /* Auto-Speed Detection Enable */
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+ Slu = 0x00000040, /* Set Link Up */
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+ Ilos = 0x00000080, /* Invert Loss of Signal (LOS) */
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+ SspeedMASK = 0x00000300, /* Speed Selection */
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+ SspeedSHIFT = 8,
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+ Sspeed10 = 0x00000000, /* 10Mb/s */
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+ Sspeed100 = 0x00000100, /* 100Mb/s */
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+ Sspeed1000 = 0x00000200, /* 1000Mb/s */
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+ Frcspd = 0x00000800, /* Force Speed */
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+ Frcdplx = 0x00001000, /* Force Duplex */
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+ SwdpinsloMASK = 0x003C0000, /* Software Defined Pins - lo nibble */
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+ SwdpinsloSHIFT = 18,
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+ SwdpioloMASK = 0x03C00000, /* Software Defined Pins - I or O */
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+ SwdpioloSHIFT = 22,
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+ Devrst = 0x04000000, /* Device Reset */
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+ Rfce = 0x08000000, /* Receive Flow Control Enable */
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+ Tfce = 0x10000000, /* Transmit Flow Control Enable */
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+ Vme = 0x40000000, /* VLAN Mode Enable */
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+};
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+
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+enum { /* Status */
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+ Lu = 0x00000002, /* Link Up */
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+ Tckok = 0x00000004, /* Transmit clock is running */
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+ Rbcok = 0x00000008, /* Receive clock is running */
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+ Txoff = 0x00000010, /* Transmission Paused */
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+ Tbimode = 0x00000020, /* TBI Mode Indication */
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+ SpeedMASK = 0x000000C0,
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+ Speed10 = 0x00000000, /* 10Mb/s */
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+ Speed100 = 0x00000040, /* 100Mb/s */
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+ Speed1000 = 0x00000080, /* 1000Mb/s */
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+ Mtxckok = 0x00000400, /* MTX clock is running */
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+ Pci66 = 0x00000800, /* PCI Bus speed indication */
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+ Bus64 = 0x00001000, /* PCI Bus width indication */
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+};
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+
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+enum { /* Ctrl and Status */
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+ Fd = 0x00000001, /* Full-Duplex */
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+ AsdvMASK = 0x00000300,
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+ Asdv10 = 0x00000000, /* 10Mb/s */
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+ Asdv100 = 0x00000100, /* 100Mb/s */
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+ Asdv1000 = 0x00000200, /* 1000Mb/s */
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+};
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+
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+enum { /* Eecd */
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+ Sk = 0x00000001, /* Clock input to the EEPROM */
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+ Cs = 0x00000002, /* Chip Select */
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+ Di = 0x00000004, /* Data Input to the EEPROM */
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+ Do = 0x00000008, /* Data Output from the EEPROM */
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+ Areq = 0x00000040, /* EEPROM Access Request */
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+ Agnt = 0x00000080, /* EEPROM Access Grant */
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+ Eesz256 = 0x00000200, /* EEPROM is 256 words not 64 */
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+ Spi = 0x00002000, /* EEPROM is SPI not Microwire */
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+};
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+
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+enum { /* Ctrlext */
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+ Gpien = 0x0000000F, /* General Purpose Interrupt Enables */
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+ SwdpinshiMASK = 0x000000F0, /* Software Defined Pins - hi nibble */
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+ SwdpinshiSHIFT = 4,
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+ SwdpiohiMASK = 0x00000F00, /* Software Defined Pins - I or O */
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+ SwdpiohiSHIFT = 8,
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+ Asdchk = 0x00001000, /* ASD Check */
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+ Eerst = 0x00002000, /* EEPROM Reset */
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+ Ips = 0x00004000, /* Invert Power State */
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+ Spdbyps = 0x00008000, /* Speed Select Bypass */
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+};
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+
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+enum { /* EEPROM content offsets */
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+ Ea = 0x00, /* Ethernet Address */
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+ Cf = 0x03, /* Compatibility Field */
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+ Pba = 0x08, /* Printed Board Assembly number */
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+ Icw1 = 0x0A, /* Initialization Control Word 1 */
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+ Sid = 0x0B, /* Subsystem ID */
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+ Svid = 0x0C, /* Subsystem Vendor ID */
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+ Did = 0x0D, /* Device ID */
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+ Vid = 0x0E, /* Vendor ID */
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+ Icw2 = 0x0F, /* Initialization Control Word 2 */
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+};
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+
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+enum { /* Mdic */
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+ MDIdMASK = 0x0000FFFF, /* Data */
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+ MDIdSHIFT = 0,
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+ MDIrMASK = 0x001F0000, /* PHY Register Address */
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+ MDIrSHIFT = 16,
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+ MDIpMASK = 0x03E00000, /* PHY Address */
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+ MDIpSHIFT = 21,
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+ MDIwop = 0x04000000, /* Write Operation */
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+ MDIrop = 0x08000000, /* Read Operation */
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+ MDIready = 0x10000000, /* End of Transaction */
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+ MDIie = 0x20000000, /* Interrupt Enable */
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+ MDIe = 0x40000000, /* Error */
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+};
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+
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+enum { /* Icr, Ics, Ims, Imc */
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+ Txdw = 0x00000001, /* Transmit Descriptor Written Back */
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+ Txqe = 0x00000002, /* Transmit Queue Empty */
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+ Lsc = 0x00000004, /* Link Status Change */
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+ Rxseq = 0x00000008, /* Receive Sequence Error */
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+ Rxdmt0 = 0x00000010, /* Rdesc Minimum Threshold Reached */
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+ Rxo = 0x00000040, /* Receiver Overrun */
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+ Rxt0 = 0x00000080, /* Receiver Timer Interrupt */
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+ Mdac = 0x00000200, /* MDIO Access Completed */
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+ Rxcfg = 0x00000400, /* Receiving /C/ ordered sets */
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+ Gpi0 = 0x00000800, /* General Purpose Interrupts */
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+ Gpi1 = 0x00001000,
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+ Gpi2 = 0x00002000,
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+ Gpi3 = 0x00004000,
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+};
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+
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+/*
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+ * The Mdic register isn't implemented on the 82543GC,
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+ * the software defined pins are used instead.
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+ * These definitions work for the Intel PRO/1000 T Server Adapter.
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+ * The direction pin bits are read from the EEPROM.
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+ */
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+enum {
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+ Mdd = ((1<<2)<<SwdpinsloSHIFT), /* data */
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+ Mddo = ((1<<2)<<SwdpioloSHIFT), /* pin direction */
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+ Mdc = ((1<<3)<<SwdpinsloSHIFT), /* clock */
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+ Mdco = ((1<<3)<<SwdpioloSHIFT), /* pin direction */
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+ Mdr = ((1<<0)<<SwdpinshiSHIFT), /* reset */
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+ Mdro = ((1<<0)<<SwdpiohiSHIFT), /* pin direction */
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+};
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+
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+enum { /* Txcw */
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+ TxcwFd = 0x00000020, /* Full Duplex */
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+ TxcwHd = 0x00000040, /* Half Duplex */
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+ TxcwPauseMASK = 0x00000180, /* Pause */
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+ TxcwPauseSHIFT = 7,
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+ TxcwPs = (1<<TxcwPauseSHIFT), /* Pause Supported */
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+ TxcwAs = (2<<TxcwPauseSHIFT), /* Asymmetric FC desired */
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+ TxcwRfiMASK = 0x00003000, /* Remote Fault Indication */
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+ TxcwRfiSHIFT = 12,
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+ TxcwNpr = 0x00008000, /* Next Page Request */
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+ TxcwConfig = 0x40000000, /* Transmit COnfig Control */
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+ TxcwAne = 0x80000000, /* Auto-Negotiation Enable */
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+};
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+
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+enum { /* Rctl */
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+ Rrst = 0x00000001, /* Receiver Software Reset */
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+ Ren = 0x00000002, /* Receiver Enable */
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+ Sbp = 0x00000004, /* Store Bad Packets */
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+ Upe = 0x00000008, /* Unicast Promiscuous Enable */
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+ Mpe = 0x00000010, /* Multicast Promiscuous Enable */
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+ Lpe = 0x00000020, /* Long Packet Reception Enable */
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+ LbmMASK = 0x000000C0, /* Loopback Mode */
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+ LbmOFF = 0x00000000, /* No Loopback */
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+ LbmTBI = 0x00000040, /* TBI Loopback */
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+ LbmMII = 0x00000080, /* GMII/MII Loopback */
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+ LbmXCVR = 0x000000C0, /* Transceiver Loopback */
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+ RdtmsMASK = 0x00000300, /* Rdesc Minimum Threshold Size */
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+ RdtmsHALF = 0x00000000, /* Threshold is 1/2 Rdlen */
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+ RdtmsQUARTER = 0x00000100, /* Threshold is 1/4 Rdlen */
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+ RdtmsEIGHTH = 0x00000200, /* Threshold is 1/8 Rdlen */
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+ MoMASK = 0x00003000, /* Multicast Offset */
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+ Bam = 0x00008000, /* Broadcast Accept Mode */
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+ BsizeMASK = 0x00030000, /* Receive Buffer Size */
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+ Bsize2048 = 0x00000000,
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+ Bsize1024 = 0x00010000,
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+ Bsize512 = 0x00020000,
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+ Bsize256 = 0x00030000,
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+ Vfe = 0x00040000, /* VLAN Filter Enable */
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+ Cfien = 0x00080000, /* Canonical Form Indicator Enable */
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+ Cfi = 0x00100000, /* Canonical Form Indicator value */
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+ Dpf = 0x00400000, /* Discard Pause Frames */
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+ Pmcf = 0x00800000, /* Pass MAC Control Frames */
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+ Bsex = 0x02000000, /* Buffer Size Extension */
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+ Secrc = 0x04000000, /* Strip CRC from incoming packet */
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+};
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+
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+enum { /* Tctl */
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+ Trst = 0x00000001, /* Transmitter Software Reset */
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+ Ten = 0x00000002, /* Transmit Enable */
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+ Psp = 0x00000008, /* Pad Short Packets */
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+ CtMASK = 0x00000FF0, /* Collision Threshold */
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+ CtSHIFT = 4,
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+ ColdMASK = 0x003FF000, /* Collision Distance */
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+ ColdSHIFT = 12,
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+ Swxoff = 0x00400000, /* Sofware XOFF Transmission */
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+ Pbe = 0x00800000, /* Packet Burst Enable */
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+ Rtlc = 0x01000000, /* Re-transmit on Late Collision */
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+ Nrtu = 0x02000000, /* No Re-transmit on Underrrun */
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+};
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+
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+enum { /* [RT]xdctl */
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+ PthreshMASK = 0x0000003F, /* Prefetch Threshold */
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+ PthreshSHIFT = 0,
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+ HthreshMASK = 0x00003F00, /* Host Threshold */
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+ HthreshSHIFT = 8,
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+ WthreshMASK = 0x003F0000, /* Writebacj Threshold */
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+ WthreshSHIFT = 16,
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+ Gran = 0x01000000, /* Granularity */
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+};
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+
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+enum { /* Rxcsum */
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+ PcssMASK = 0x000000FF, /* Packet Checksum Start */
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+ PcssSHIFT = 0,
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+ Ipofl = 0x00000100, /* IP Checksum Off-load Enable */
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+ Tuofl = 0x00000200, /* TCP/UDP Checksum Off-load Enable */
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+};
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+
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+enum { /* Manc */
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+ Arpen = 0x00002000, /* Enable ARP Request Filtering */
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+};
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+
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+typedef struct Rdesc { /* Receive Descriptor */
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+ uint addr[2];
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+ ushort length;
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+ ushort checksum;
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+ uchar status;
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+ uchar errors;
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+ ushort special;
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+} Rdesc;
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+
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+enum { /* Rdesc status */
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+ Rdd = 0x01, /* Descriptor Done */
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+ Reop = 0x02, /* End of Packet */
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+ Ixsm = 0x04, /* Ignore Checksum Indication */
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+ Vp = 0x08, /* Packet is 802.1Q (matched VET) */
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+ Tcpcs = 0x20, /* TCP Checksum Calculated on Packet */
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+ Ipcs = 0x40, /* IP Checksum Calculated on Packet */
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+ Pif = 0x80, /* Passed in-exact filter */
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+};
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+
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+enum { /* Rdesc errors */
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+ Ce = 0x01, /* CRC Error or Alignment Error */
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+ Se = 0x02, /* Symbol Error */
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+ Seq = 0x04, /* Sequence Error */
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+ Cxe = 0x10, /* Carrier Extension Error */
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+ Tcpe = 0x20, /* TCP/UDP Checksum Error */
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+ Ipe = 0x40, /* IP Checksum Error */
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+ Rxe = 0x80, /* RX Data Error */
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+};
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+
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+typedef struct Tdesc { /* Legacy+Normal Transmit Descriptor */
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+ uint addr[2];
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+ uint control; /* varies with descriptor type */
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+ uint status; /* varies with descriptor type */
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+} Tdesc;
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+
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+enum { /* Tdesc control */
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+ LenMASK = 0x000FFFFF, /* Data/Packet Length Field */
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+ LenSHIFT = 0,
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+ DtypeCD = 0x00000000, /* Data Type 'Context Descriptor' */
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+ DtypeDD = 0x00100000, /* Data Type 'Data Descriptor' */
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+ PtypeTCP = 0x01000000, /* TCP/UDP Packet Type (CD) */
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+ Teop = 0x01000000, /* End of Packet (DD) */
|
|
|
+ PtypeIP = 0x02000000, /* IP Packet Type (CD) */
|
|
|
+ Ifcs = 0x02000000, /* Insert FCS (DD) */
|
|
|
+ Tse = 0x04000000, /* TCP Segmentation Enable */
|
|
|
+ Rs = 0x08000000, /* Report Status */
|
|
|
+ Rps = 0x10000000, /* Report Status Sent */
|
|
|
+ Dext = 0x20000000, /* Descriptor Extension */
|
|
|
+ Vle = 0x40000000, /* VLAN Packet Enable */
|
|
|
+ Ide = 0x80000000, /* Interrupt Delay Enable */
|
|
|
+};
|
|
|
+
|
|
|
+enum { /* Tdesc status */
|
|
|
+ Tdd = 0x00000001, /* Descriptor Done */
|
|
|
+ Ec = 0x00000002, /* Excess Collisions */
|
|
|
+ Lc = 0x00000004, /* Late Collision */
|
|
|
+ Tu = 0x00000008, /* Transmit Underrun */
|
|
|
+ CssMASK = 0x0000FF00, /* Checksum Start Field */
|
|
|
+ CssSHIFT = 8,
|
|
|
+};
|
|
|
+
|
|
|
+enum {
|
|
|
+ Nrdesc = 128, /* multiple of 8 */
|
|
|
+ Ntdesc = 128, /* multiple of 8 */
|
|
|
+};
|
|
|
+
|
|
|
+typedef struct Ctlr Ctlr;
|
|
|
+typedef struct Ctlr {
|
|
|
+ int port;
|
|
|
+ Pcidev* pcidev;
|
|
|
+ Ctlr* next;
|
|
|
+ int active;
|
|
|
+ int id;
|
|
|
+ int cls;
|
|
|
+ ushort eeprom[0x40];
|
|
|
+
|
|
|
+ int* nic;
|
|
|
+ Lock imlock;
|
|
|
+ int im; /* interrupt mask */
|
|
|
+
|
|
|
+ Mii* mii;
|
|
|
+
|
|
|
+ Lock slock;
|
|
|
+ uint statistics[Nstatistics];
|
|
|
+
|
|
|
+ uchar ra[Eaddrlen]; /* receive address */
|
|
|
+ ulong mta[128]; /* multicast table array */
|
|
|
+
|
|
|
+ Rdesc* rdba; /* receive descriptor base address */
|
|
|
+ Block** rb; /* receive buffers */
|
|
|
+ int rdh; /* receive descriptor head */
|
|
|
+ int rdt; /* receive descriptor tail */
|
|
|
+
|
|
|
+ Tdesc* tdba; /* transmit descriptor base address */
|
|
|
+ Lock tdlock;
|
|
|
+ Block** tb; /* transmit buffers */
|
|
|
+ int tdh; /* transmit descriptor head */
|
|
|
+ int tdt; /* transmit descriptor tail */
|
|
|
+ int ett; /* early transmit threshold */
|
|
|
+
|
|
|
+ int txcw;
|
|
|
+ int fcrtl;
|
|
|
+ int fcrth;
|
|
|
+
|
|
|
+ /* bootstrap goo */
|
|
|
+ Block* bqhead; /* transmission queue */
|
|
|
+ Block* bqtail;
|
|
|
+} Ctlr;
|
|
|
+
|
|
|
+static Ctlr* ctlrhead;
|
|
|
+static Ctlr* ctlrtail;
|
|
|
+
|
|
|
+#define csr32r(c, r) (*((c)->nic+((r)/4)))
|
|
|
+#define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v))
|
|
|
+
|
|
|
+static void
|
|
|
+igbeim(Ctlr* ctlr, int im)
|
|
|
+{
|
|
|
+ ilock(&ctlr->imlock);
|
|
|
+ ctlr->im |= im;
|
|
|
+ csr32w(ctlr, Ims, ctlr->im);
|
|
|
+ iunlock(&ctlr->imlock);
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+igbeattach(Ether* edev)
|
|
|
+{
|
|
|
+ int ctl;
|
|
|
+ Ctlr *ctlr;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * To do here:
|
|
|
+ * one-time stuff;
|
|
|
+ * start off a kproc for link status change:
|
|
|
+ * adjust queue length depending on speed;
|
|
|
+ * flow control.
|
|
|
+ * more needed here...
|
|
|
+ */
|
|
|
+ ctlr = edev->ctlr;
|
|
|
+ igbeim(ctlr, 0);
|
|
|
+ ctl = csr32r(ctlr, Rctl)|Ren;
|
|
|
+ csr32w(ctlr, Rctl, ctl);
|
|
|
+ ctl = csr32r(ctlr, Tctl)|Ten;
|
|
|
+ csr32w(ctlr, Tctl, ctl);
|
|
|
+}
|
|
|
+
|
|
|
+static char* statistics[Nstatistics] = {
|
|
|
+ "CRC Error",
|
|
|
+ "Alignment Error",
|
|
|
+ "Symbol Error",
|
|
|
+ "RX Error",
|
|
|
+ "Missed Packets",
|
|
|
+ "Single Collision",
|
|
|
+ "Excessive Collisions",
|
|
|
+ "Multiple Collision",
|
|
|
+ "Late Collisions",
|
|
|
+ nil,
|
|
|
+ "Collision",
|
|
|
+ "Transmit Underrun",
|
|
|
+ "Defer",
|
|
|
+ "Transmit - No CRS",
|
|
|
+ "Sequence Error",
|
|
|
+ "Carrier Extension Error",
|
|
|
+ "Receive Error Length",
|
|
|
+ nil,
|
|
|
+ "XON Received",
|
|
|
+ "XON Transmitted",
|
|
|
+ "XOFF Received",
|
|
|
+ "XOFF Transmitted",
|
|
|
+ "FC Received Unsupported",
|
|
|
+ "Packets Received (64 Bytes)",
|
|
|
+ "Packets Received (65-127 Bytes)",
|
|
|
+ "Packets Received (128-255 Bytes)",
|
|
|
+ "Packets Received (256-511 Bytes)",
|
|
|
+ "Packets Received (512-1023 Bytes)",
|
|
|
+ "Packets Received (1024-1522 Bytes)",
|
|
|
+ "Good Packets Received",
|
|
|
+ "Broadcast Packets Received",
|
|
|
+ "Multicast Packets Received",
|
|
|
+ "Good Packets Transmitted",
|
|
|
+ nil,
|
|
|
+ "Good Octets Received",
|
|
|
+ nil,
|
|
|
+ "Good Octets Transmitted",
|
|
|
+ nil,
|
|
|
+ nil,
|
|
|
+ nil,
|
|
|
+ "Receive No Buffers",
|
|
|
+ "Receive Undersize",
|
|
|
+ "Receive Fragment",
|
|
|
+ "Receive Oversize",
|
|
|
+ "Receive Jabber",
|
|
|
+ nil,
|
|
|
+ nil,
|
|
|
+ nil,
|
|
|
+ "Total Octets Received",
|
|
|
+ nil,
|
|
|
+ "Total Octets Transmitted",
|
|
|
+ nil,
|
|
|
+ "Total Packets Received",
|
|
|
+ "Total Packets Transmitted",
|
|
|
+ "Packets Transmitted (64 Bytes)",
|
|
|
+ "Packets Transmitted (65-127 Bytes)",
|
|
|
+ "Packets Transmitted (128-255 Bytes)",
|
|
|
+ "Packets Transmitted (256-511 Bytes)",
|
|
|
+ "Packets Transmitted (512-1023 Bytes)",
|
|
|
+ "Packets Transmitted (1024-1522 Bytes)",
|
|
|
+ "Multicast Packets Transmitted",
|
|
|
+ "Broadcast Packets Transmitted",
|
|
|
+ "TCP Segmentation Context Transmitted",
|
|
|
+ "TCP Segmentation Context Fail",
|
|
|
+};
|
|
|
+
|
|
|
+static void
|
|
|
+txstart(Ether *edev)
|
|
|
+{
|
|
|
+ int tdh, tdt, len, olen;
|
|
|
+ Ctlr *ctlr = edev->ctlr;
|
|
|
+ Block *bp;
|
|
|
+ Tdesc *tdesc;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Try to fill the ring back up, moving buffers from the transmit q.
|
|
|
+ */
|
|
|
+ tdh = PREV(ctlr->tdh, Ntdesc);
|
|
|
+ for(tdt = ctlr->tdt; tdt != tdh; tdt = NEXT(tdt, Ntdesc)){
|
|
|
+ /* pull off the head of the transmission queue */
|
|
|
+ if((bp = ctlr->bqhead) == nil) /* was qget(edev->oq) */
|
|
|
+ break;
|
|
|
+ ctlr->bqhead = bp->next;
|
|
|
+ if (ctlr->bqtail == bp)
|
|
|
+ ctlr->bqtail = nil;
|
|
|
+ len = olen = BLEN(bp);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * if packet is too short, make it longer rather than relying
|
|
|
+ * on ethernet interface to pad it and complain so the caller
|
|
|
+ * will get fixed. I don't think Psp is working right, or it's
|
|
|
+ * getting cleared.
|
|
|
+ */
|
|
|
+ if (len < ETHERMINTU) {
|
|
|
+ if (bp->rp + ETHERMINTU <= bp->lim)
|
|
|
+ bp->wp = bp->rp + ETHERMINTU;
|
|
|
+ else
|
|
|
+ bp->wp = bp->lim;
|
|
|
+ len = BLEN(bp);
|
|
|
+ print("txstart: extended short pkt %d -> %d bytes\n",
|
|
|
+ olen, len);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* set up a descriptor for it */
|
|
|
+ tdesc = &ctlr->tdba[tdt];
|
|
|
+ tdesc->addr[0] = PCIWADDR(bp->rp);
|
|
|
+ tdesc->addr[1] = 0;
|
|
|
+ tdesc->control = /* Ide| */ Rs|Dext|Ifcs|Teop|DtypeDD|len;
|
|
|
+ tdesc->status = 0;
|
|
|
+
|
|
|
+ ctlr->tb[tdt] = bp;
|
|
|
+ }
|
|
|
+ ctlr->tdt = tdt;
|
|
|
+ csr32w(ctlr, Tdt, tdt);
|
|
|
+ igbeim(ctlr, Txdw);
|
|
|
+}
|
|
|
+
|
|
|
+static Block *
|
|
|
+fromringbuf(Ether *ether)
|
|
|
+{
|
|
|
+ RingBuf *tb = ðer->tb[ether->ti];
|
|
|
+ Block *bp = allocb(tb->len);
|
|
|
+
|
|
|
+ memmove(bp->wp, tb->pkt, tb->len);
|
|
|
+ memmove(bp->wp+Eaddrlen, ether->ea, Eaddrlen);
|
|
|
+ bp->wp += tb->len;
|
|
|
+ return bp;
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+igbetransmit(Ether* edev)
|
|
|
+{
|
|
|
+ Block *bp;
|
|
|
+ Ctlr *ctlr;
|
|
|
+ Tdesc *tdesc;
|
|
|
+ RingBuf *tb;
|
|
|
+ int tdh;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * For now there are no smarts here. Tuning comes later.
|
|
|
+ */
|
|
|
+ ctlr = edev->ctlr;
|
|
|
+ ilock(&ctlr->tdlock);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Free any completed packets
|
|
|
+ * - try to get the soft tdh to catch the tdt;
|
|
|
+ * - if the packet had an underrun bump the threshold
|
|
|
+ * - the Tu bit doesn't seem to ever be set, perhaps
|
|
|
+ * because Rs mode is used?
|
|
|
+ */
|
|
|
+ tdh = ctlr->tdh;
|
|
|
+ for(;;){
|
|
|
+ tdesc = &ctlr->tdba[tdh];
|
|
|
+ if(!(tdesc->status & Tdd))
|
|
|
+ break;
|
|
|
+ if(tdesc->status & Tu){
|
|
|
+ ctlr->ett++;
|
|
|
+ csr32w(ctlr, Ett, ctlr->ett);
|
|
|
+ }
|
|
|
+ tdesc->status = 0;
|
|
|
+ if(ctlr->tb[tdh] != nil){
|
|
|
+ freeb(ctlr->tb[tdh]);
|
|
|
+ ctlr->tb[tdh] = nil;
|
|
|
+ }
|
|
|
+ tdh = NEXT(tdh, Ntdesc);
|
|
|
+ }
|
|
|
+ ctlr->tdh = tdh;
|
|
|
+
|
|
|
+ /* copy packets from the software RingBuf to the transmission q */
|
|
|
+ /* from boot ether83815.c */
|
|
|
+ while((tb = &edev->tb[edev->ti])->owner == Interface){
|
|
|
+ bp = fromringbuf(edev);
|
|
|
+
|
|
|
+ /* put the buffer on the transmit queue */
|
|
|
+ if(ctlr->bqhead)
|
|
|
+ ctlr->bqtail->next = bp;
|
|
|
+ else
|
|
|
+ ctlr->bqhead = bp;
|
|
|
+ ctlr->bqtail = bp;
|
|
|
+
|
|
|
+ txstart(edev); /* kick transmitter */
|
|
|
+ tb->owner = Host; /* give descriptor back */
|
|
|
+
|
|
|
+ edev->ti = NEXT(edev->ti, edev->ntb);
|
|
|
+ }
|
|
|
+
|
|
|
+ iunlock(&ctlr->tdlock);
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+igbereplenish(Ctlr* ctlr)
|
|
|
+{
|
|
|
+ int rdt;
|
|
|
+ Block *bp;
|
|
|
+ Rdesc *rdesc;
|
|
|
+
|
|
|
+ rdt = ctlr->rdt;
|
|
|
+ while(NEXT(rdt, Nrdesc) != ctlr->rdh){
|
|
|
+ rdesc = &ctlr->rdba[rdt];
|
|
|
+ if(ctlr->rb[rdt] != nil){
|
|
|
+ /* nothing to do */
|
|
|
+ }
|
|
|
+ else if((bp = iallocb(2048)) != nil){
|
|
|
+ ctlr->rb[rdt] = bp;
|
|
|
+ rdesc->addr[0] = PCIWADDR(bp->rp);
|
|
|
+ rdesc->addr[1] = 0;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ break;
|
|
|
+ rdesc->status = 0;
|
|
|
+
|
|
|
+ rdt = NEXT(rdt, Nrdesc);
|
|
|
+ }
|
|
|
+ ctlr->rdt = rdt;
|
|
|
+ csr32w(ctlr, Rdt, rdt);
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+toringbuf(Ether *ether, Block *bp)
|
|
|
+{
|
|
|
+ RingBuf *rb = ðer->rb[ether->ri];
|
|
|
+
|
|
|
+ if (rb->owner == Interface) {
|
|
|
+ rb->len = BLEN(bp);
|
|
|
+ memmove(rb->pkt, bp->rp, rb->len);
|
|
|
+ rb->owner = Host;
|
|
|
+ ether->ri = NEXT(ether->ri, ether->nrb);
|
|
|
+ }
|
|
|
+ /* else no one is expecting packets from the network */
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+igbeinterrupt(Ureg*, void* arg)
|
|
|
+{
|
|
|
+ Block *bp;
|
|
|
+ Ctlr *ctlr;
|
|
|
+ Ether *edev;
|
|
|
+ Rdesc *rdesc;
|
|
|
+ int icr, im, rdh, txdw = 0;
|
|
|
+
|
|
|
+ edev = arg;
|
|
|
+ ctlr = edev->ctlr;
|
|
|
+
|
|
|
+ ilock(&ctlr->imlock);
|
|
|
+ csr32w(ctlr, Imc, ~0);
|
|
|
+ im = ctlr->im;
|
|
|
+
|
|
|
+ for(icr = csr32r(ctlr, Icr); icr & ctlr->im; icr = csr32r(ctlr, Icr)){
|
|
|
+ /*
|
|
|
+ * Link status changed.
|
|
|
+ */
|
|
|
+ if(icr & (Rxseq|Lsc)){
|
|
|
+ /*
|
|
|
+ * More here...
|
|
|
+ */
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Process any received packets.
|
|
|
+ */
|
|
|
+ rdh = ctlr->rdh;
|
|
|
+ for(;;){
|
|
|
+ rdesc = &ctlr->rdba[rdh];
|
|
|
+ if(!(rdesc->status & Rdd))
|
|
|
+ break;
|
|
|
+ if ((rdesc->status & Reop) && rdesc->errors == 0) {
|
|
|
+ bp = ctlr->rb[rdh];
|
|
|
+ ctlr->rb[rdh] = nil;
|
|
|
+ /*
|
|
|
+ * it appears that the original 82543 needed
|
|
|
+ * to have the Ethernet CRC excluded, but that
|
|
|
+ * the newer chips do not?
|
|
|
+ */
|
|
|
+ bp->wp += rdesc->length /* -4 */;
|
|
|
+ toringbuf(edev, bp);
|
|
|
+ freeb(bp);
|
|
|
+ } else if ((rdesc->status & Reop) && rdesc->errors)
|
|
|
+ print("igbe: input packet error 0x%ux\n",
|
|
|
+ rdesc->errors);
|
|
|
+ rdesc->status = 0;
|
|
|
+ rdh = NEXT(rdh, Nrdesc);
|
|
|
+ }
|
|
|
+ ctlr->rdh = rdh;
|
|
|
+
|
|
|
+ if(icr & Rxdmt0)
|
|
|
+ igbereplenish(ctlr);
|
|
|
+ if(icr & Txdw){
|
|
|
+ im &= ~Txdw;
|
|
|
+ txdw++;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ ctlr->im = im;
|
|
|
+ csr32w(ctlr, Ims, im);
|
|
|
+ iunlock(&ctlr->imlock);
|
|
|
+
|
|
|
+ if(txdw)
|
|
|
+ igbetransmit(edev);
|
|
|
+}
|
|
|
+
|
|
|
+static int
|
|
|
+igbeinit(Ether* edev)
|
|
|
+{
|
|
|
+ int csr, i, r, ctrl;
|
|
|
+ MiiPhy *phy;
|
|
|
+ Ctlr *ctlr;
|
|
|
+
|
|
|
+ ctlr = edev->ctlr;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Set up the receive addresses.
|
|
|
+ * There are 16 addresses. The first should be the MAC address.
|
|
|
+ * The others are cleared and not marked valid (MS bit of Rah).
|
|
|
+ */
|
|
|
+ csr = (edev->ea[3]<<24)|(edev->ea[2]<<16)|(edev->ea[1]<<8)|edev->ea[0];
|
|
|
+ csr32w(ctlr, Ral, csr);
|
|
|
+ csr = 0x80000000|(edev->ea[5]<<8)|edev->ea[4];
|
|
|
+ csr32w(ctlr, Rah, csr);
|
|
|
+ for(i = 1; i < 16; i++){
|
|
|
+ csr32w(ctlr, Ral+i*8, 0);
|
|
|
+ csr32w(ctlr, Rah+i*8, 0);
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Clear the Multicast Table Array.
|
|
|
+ * It's a 4096 bit vector accessed as 128 32-bit registers.
|
|
|
+ */
|
|
|
+ for(i = 0; i < 128; i++)
|
|
|
+ csr32w(ctlr, Mta+i*4, 0);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Receive initialisation.
|
|
|
+ * Mostly defaults from the datasheet, will
|
|
|
+ * need some tuning for performance:
|
|
|
+ * Rctl descriptor mimimum threshold size
|
|
|
+ * discard pause frames
|
|
|
+ * strip CRC
|
|
|
+ * Rdtr interrupt delay
|
|
|
+ * Rxdctl all the thresholds
|
|
|
+ */
|
|
|
+ csr32w(ctlr, Rctl, 0);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Allocate the descriptor ring and load its
|
|
|
+ * address and length into the NIC.
|
|
|
+ */
|
|
|
+ ctlr->rdba = xspanalloc(Nrdesc*sizeof(Rdesc), 128 /* was 16 */, 0);
|
|
|
+ csr32w(ctlr, Rdbal, PCIWADDR(ctlr->rdba));
|
|
|
+ csr32w(ctlr, Rdbah, 0);
|
|
|
+ csr32w(ctlr, Rdlen, Nrdesc*sizeof(Rdesc));
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Initialise the ring head and tail pointers and
|
|
|
+ * populate the ring with Blocks.
|
|
|
+ * The datasheet says the tail pointer is set to beyond the last
|
|
|
+ * descriptor hardware can process, which implies the initial
|
|
|
+ * condition is Rdh == Rdt. However, experience shows Rdt must
|
|
|
+ * always be 'behind' Rdh; the replenish routine ensures this.
|
|
|
+ */
|
|
|
+ ctlr->rdh = 0;
|
|
|
+ csr32w(ctlr, Rdh, ctlr->rdh);
|
|
|
+ ctlr->rdt = 0;
|
|
|
+ csr32w(ctlr, Rdt, ctlr->rdt);
|
|
|
+ ctlr->rb = malloc(sizeof(Block*)*Nrdesc);
|
|
|
+ igbereplenish(ctlr);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Set up Rctl but don't enable receiver (yet).
|
|
|
+ */
|
|
|
+ csr32w(ctlr, Rdtr, 0);
|
|
|
+ switch(ctlr->id){
|
|
|
+ case (0x100E<<16)|0x8086: /* 82540EM */
|
|
|
+ case (0x101E<<16)|0x8086: /* 82540EPLP */
|
|
|
+ csr32w(ctlr, Radv, 64);
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ csr32w(ctlr, Rxdctl, (8<<WthreshSHIFT)|(8<<HthreshSHIFT)|4);
|
|
|
+ /*
|
|
|
+ * Enable checksum offload.
|
|
|
+ */
|
|
|
+ csr32w(ctlr, Rxcsum, Tuofl|Ipofl|(ETHERHDRSIZE<<PcssSHIFT));
|
|
|
+
|
|
|
+ csr32w(ctlr, Rctl, Dpf|Bsize2048|Bam|RdtmsHALF);
|
|
|
+ igbeim(ctlr, Rxt0|Rxo|Rxdmt0|Rxseq);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Transmit initialisation.
|
|
|
+ * Mostly defaults from the datasheet, will
|
|
|
+ * need some tuning for performance. The normal mode will
|
|
|
+ * be full-duplex and things to tune for half-duplex are
|
|
|
+ * Tctl re-transmit on late collision
|
|
|
+ * Tipg all IPG times
|
|
|
+ * Tbt burst timer
|
|
|
+ * Ait adaptive IFS throttle
|
|
|
+ * and in general
|
|
|
+ * Txdmac packet prefetching
|
|
|
+ * Ett transmit early threshold
|
|
|
+ * Tidv interrupt delay value
|
|
|
+ * Txdctl all the thresholds
|
|
|
+ */
|
|
|
+ csr32w(ctlr, Tctl, (0x0F<<CtSHIFT)|Psp|(66<<ColdSHIFT)); /* Fd */
|
|
|
+ switch(ctlr->id){
|
|
|
+ default:
|
|
|
+ r = 6;
|
|
|
+ break;
|
|
|
+ case (0x1004<<16)|0x8086: /* 82543GC */
|
|
|
+ case (0x1008<<16)|0x8086: /* 82544EI */
|
|
|
+ case (0x100E<<16)|0x8086: /* 82440EM */
|
|
|
+ case (0x101E<<16)|0x8086: /* 82540EPLP */
|
|
|
+ r = 8;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ csr32w(ctlr, Tipg, (6<<20)|(8<<10)|r);
|
|
|
+ csr32w(ctlr, Ait, 0);
|
|
|
+ csr32w(ctlr, Txdmac, 0);
|
|
|
+ csr32w(ctlr, Tidv, 128);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Allocate the descriptor ring and load its
|
|
|
+ * address and length into the NIC.
|
|
|
+ */
|
|
|
+ ctlr->tdba = xspanalloc(Ntdesc*sizeof(Tdesc), 128 /* was 16 */, 0);
|
|
|
+ csr32w(ctlr, Tdbal, PCIWADDR(ctlr->tdba));
|
|
|
+ csr32w(ctlr, Tdbah, 0);
|
|
|
+ csr32w(ctlr, Tdlen, Ntdesc*sizeof(Tdesc));
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Initialise the ring head and tail pointers.
|
|
|
+ */
|
|
|
+ ctlr->tdh = 0;
|
|
|
+ csr32w(ctlr, Tdh, ctlr->tdh);
|
|
|
+ ctlr->tdt = 0;
|
|
|
+ csr32w(ctlr, Tdt, ctlr->tdt);
|
|
|
+ ctlr->tb = malloc(sizeof(Block*)*Ntdesc);
|
|
|
+// ctlr->im |= Txqe|Txdw;
|
|
|
+
|
|
|
+ r = (4<<WthreshSHIFT)|(4<<HthreshSHIFT)|(8<<PthreshSHIFT);
|
|
|
+ switch(ctlr->id){
|
|
|
+ default:
|
|
|
+ break;
|
|
|
+ case (0x100E<<16)|0x8086: /* 82540EM */
|
|
|
+ case (0x101E<<16)|0x8086: /* 82540EPLP */
|
|
|
+ r = csr32r(ctlr, Txdctl);
|
|
|
+ r &= ~WthreshMASK;
|
|
|
+ r |= Gran|(4<<WthreshSHIFT);
|
|
|
+
|
|
|
+ csr32w(ctlr, Tadv, 64);
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ csr32w(ctlr, Txdctl, r);
|
|
|
+
|
|
|
+ r = csr32r(ctlr, Tctl);
|
|
|
+ r |= Ten;
|
|
|
+ csr32w(ctlr, Tctl, r);
|
|
|
+
|
|
|
+ if(ctlr->mii == nil || ctlr->mii->curphy == nil) {
|
|
|
+ print("igbe: no mii (yet)\n");
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
+ /* wait for the link to come up */
|
|
|
+ if (miistatus(ctlr->mii) < 0)
|
|
|
+ return -1;
|
|
|
+ print("igbe: phy: ");
|
|
|
+ phy = ctlr->mii->curphy;
|
|
|
+ if (phy->fd)
|
|
|
+ print("full duplex");
|
|
|
+ else
|
|
|
+ print("half duplex");
|
|
|
+ print(", %d Mb/s\n", phy->speed);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Flow control.
|
|
|
+ */
|
|
|
+ ctrl = csr32r(ctlr, Ctrl);
|
|
|
+ if(phy->rfc)
|
|
|
+ ctrl |= Rfce;
|
|
|
+ if(phy->tfc)
|
|
|
+ ctrl |= Tfce;
|
|
|
+ csr32w(ctlr, Ctrl, ctrl);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int
|
|
|
+i82543mdior(Ctlr* ctlr, int n)
|
|
|
+{
|
|
|
+ int ctrl, data, i, r;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Read n bits from the Management Data I/O Interface.
|
|
|
+ */
|
|
|
+ ctrl = csr32r(ctlr, Ctrl);
|
|
|
+ r = (ctrl & ~Mddo)|Mdco;
|
|
|
+ data = 0;
|
|
|
+ for(i = n-1; i >= 0; i--){
|
|
|
+ if(csr32r(ctlr, Ctrl) & Mdd)
|
|
|
+ data |= (1<<i);
|
|
|
+ csr32w(ctlr, Ctrl, Mdc|r);
|
|
|
+ csr32w(ctlr, Ctrl, r);
|
|
|
+ }
|
|
|
+ csr32w(ctlr, Ctrl, ctrl);
|
|
|
+
|
|
|
+ return data;
|
|
|
+}
|
|
|
+
|
|
|
+static int
|
|
|
+i82543mdiow(Ctlr* ctlr, int bits, int n)
|
|
|
+{
|
|
|
+ int ctrl, i, r;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Write n bits to the Management Data I/O Interface.
|
|
|
+ */
|
|
|
+ ctrl = csr32r(ctlr, Ctrl);
|
|
|
+ r = Mdco|Mddo|ctrl;
|
|
|
+ for(i = n-1; i >= 0; i--){
|
|
|
+ if(bits & (1<<i))
|
|
|
+ r |= Mdd;
|
|
|
+ else
|
|
|
+ r &= ~Mdd;
|
|
|
+ csr32w(ctlr, Ctrl, Mdc|r);
|
|
|
+ csr32w(ctlr, Ctrl, r);
|
|
|
+ }
|
|
|
+ csr32w(ctlr, Ctrl, ctrl);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int
|
|
|
+i82543miimir(Mii* mii, int pa, int ra)
|
|
|
+{
|
|
|
+ int data;
|
|
|
+ Ctlr *ctlr;
|
|
|
+
|
|
|
+ ctlr = mii->ctlr;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * MII Management Interface Read.
|
|
|
+ *
|
|
|
+ * Preamble;
|
|
|
+ * ST+OP+PHYAD+REGAD;
|
|
|
+ * TA + 16 data bits.
|
|
|
+ */
|
|
|
+ i82543mdiow(ctlr, 0xFFFFFFFF, 32);
|
|
|
+ i82543mdiow(ctlr, 0x1800|(pa<<5)|ra, 14);
|
|
|
+ data = i82543mdior(ctlr, 18);
|
|
|
+
|
|
|
+ if(data & 0x10000)
|
|
|
+ return -1;
|
|
|
+
|
|
|
+ return data & 0xFFFF;
|
|
|
+}
|
|
|
+
|
|
|
+static int
|
|
|
+i82543miimiw(Mii* mii, int pa, int ra, int data)
|
|
|
+{
|
|
|
+ Ctlr *ctlr;
|
|
|
+
|
|
|
+ ctlr = mii->ctlr;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * MII Management Interface Write.
|
|
|
+ *
|
|
|
+ * Preamble;
|
|
|
+ * ST+OP+PHYAD+REGAD+TA + 16 data bits;
|
|
|
+ * Z.
|
|
|
+ */
|
|
|
+ i82543mdiow(ctlr, 0xFFFFFFFF, 32);
|
|
|
+ data &= 0xFFFF;
|
|
|
+ data |= (0x05<<(5+5+2+16))|(pa<<(5+2+16))|(ra<<(2+16))|(0x02<<16);
|
|
|
+ i82543mdiow(ctlr, data, 32);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int
|
|
|
+igbemiimir(Mii* mii, int pa, int ra)
|
|
|
+{
|
|
|
+ Ctlr *ctlr;
|
|
|
+ int mdic, timo;
|
|
|
+
|
|
|
+ ctlr = mii->ctlr;
|
|
|
+
|
|
|
+ csr32w(ctlr, Mdic, MDIrop|(pa<<MDIpSHIFT)|(ra<<MDIrSHIFT));
|
|
|
+ mdic = 0;
|
|
|
+ for(timo = 64; timo; timo--){
|
|
|
+ mdic = csr32r(ctlr, Mdic);
|
|
|
+ if(mdic & (MDIe|MDIready))
|
|
|
+ break;
|
|
|
+ microdelay(1);
|
|
|
+ }
|
|
|
+
|
|
|
+ if((mdic & (MDIe|MDIready)) == MDIready)
|
|
|
+ return mdic & 0xFFFF;
|
|
|
+ return -1;
|
|
|
+}
|
|
|
+
|
|
|
+static int
|
|
|
+igbemiimiw(Mii* mii, int pa, int ra, int data)
|
|
|
+{
|
|
|
+ Ctlr *ctlr;
|
|
|
+ int mdic, timo;
|
|
|
+
|
|
|
+ ctlr = mii->ctlr;
|
|
|
+
|
|
|
+ data &= MDIdMASK;
|
|
|
+ csr32w(ctlr, Mdic, MDIwop|(pa<<MDIpSHIFT)|(ra<<MDIrSHIFT)|data);
|
|
|
+ mdic = 0;
|
|
|
+ for(timo = 64; timo; timo--){
|
|
|
+ mdic = csr32r(ctlr, Mdic);
|
|
|
+ if(mdic & (MDIe|MDIready))
|
|
|
+ break;
|
|
|
+ microdelay(1);
|
|
|
+ }
|
|
|
+ if((mdic & (MDIe|MDIready)) == MDIready)
|
|
|
+ return 0;
|
|
|
+ return -1;
|
|
|
+}
|
|
|
+
|
|
|
+static int
|
|
|
+igbemii(Ctlr* ctlr)
|
|
|
+{
|
|
|
+ MiiPhy *phy;
|
|
|
+ int ctrl, p, r;
|
|
|
+
|
|
|
+ r = csr32r(ctlr, Status);
|
|
|
+ if(r & Tbimode)
|
|
|
+ return -1;
|
|
|
+ if((ctlr->mii = malloc(sizeof(Mii))) == nil)
|
|
|
+ return -1;
|
|
|
+ ctlr->mii->ctlr = ctlr;
|
|
|
+
|
|
|
+ ctrl = csr32r(ctlr, Ctrl);
|
|
|
+ ctrl |= Slu;
|
|
|
+
|
|
|
+ switch(ctlr->id){
|
|
|
+ case (0x1004<<16)|0x8086: /* 82543GC */
|
|
|
+ ctrl |= Frcdplx|Frcspd;
|
|
|
+ csr32w(ctlr, Ctrl, ctrl);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * The reset pin direction (Mdro) should already
|
|
|
+ * be set from the EEPROM load.
|
|
|
+ * If it's not set this configuration is unexpected
|
|
|
+ * so bail.
|
|
|
+ */
|
|
|
+ r = csr32r(ctlr, Ctrlext);
|
|
|
+ if(!(r & Mdro))
|
|
|
+ return -1;
|
|
|
+ csr32w(ctlr, Ctrlext, r);
|
|
|
+ delay(20);
|
|
|
+ r = csr32r(ctlr, Ctrlext);
|
|
|
+ r &= ~Mdr;
|
|
|
+ csr32w(ctlr, Ctrlext, r);
|
|
|
+ delay(20);
|
|
|
+ r = csr32r(ctlr, Ctrlext);
|
|
|
+ r |= Mdr;
|
|
|
+ csr32w(ctlr, Ctrlext, r);
|
|
|
+ delay(20);
|
|
|
+
|
|
|
+ ctlr->mii->mir = i82543miimir;
|
|
|
+ ctlr->mii->miw = i82543miimiw;
|
|
|
+ break;
|
|
|
+ case (0x1008<<16)|0x8086: /* 82544EI*/
|
|
|
+ case (0x100E<<16)|0x8086: /* 82540EM */
|
|
|
+ case (0x101E<<16)|0x8086: /* 82540EPLP */
|
|
|
+ ctrl &= ~(Frcdplx|Frcspd);
|
|
|
+ csr32w(ctlr, Ctrl, ctrl);
|
|
|
+ ctlr->mii->mir = igbemiimir;
|
|
|
+ ctlr->mii->miw = igbemiimiw;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ free(ctlr->mii);
|
|
|
+ ctlr->mii = nil;
|
|
|
+ return -1;
|
|
|
+ }
|
|
|
+
|
|
|
+ if(mii(ctlr->mii, ~0) == 0 || (phy = ctlr->mii->curphy) == nil){
|
|
|
+ free(ctlr->mii);
|
|
|
+ ctlr->mii = nil;
|
|
|
+ return -1;
|
|
|
+ }
|
|
|
+ print("oui %X phyno %d\n", phy->oui, phy->phyno);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * 8254X-specific PHY registers not in 802.3:
|
|
|
+ * 0x10 PHY specific control
|
|
|
+ * 0x14 extended PHY specific control
|
|
|
+ * Set appropriate values then reset the PHY to have
|
|
|
+ * changes noted.
|
|
|
+ */
|
|
|
+ r = miimir(ctlr->mii, 0x10);
|
|
|
+ r |= 0x0800; /* assert CRS on Tx */
|
|
|
+ r |= 0x0060; /* auto-crossover all speeds */
|
|
|
+ r |= 0x0002; /* polarity reversal enabled */
|
|
|
+ miimiw(ctlr->mii, 0x10, r);
|
|
|
+
|
|
|
+ r = miimir(ctlr->mii, 0x14);
|
|
|
+ r |= 0x0070; /* +25MHz clock */
|
|
|
+ r &= ~0x0F00;
|
|
|
+ r |= 0x0100; /* 1x downshift */
|
|
|
+ miimiw(ctlr->mii, 0x14, r);
|
|
|
+
|
|
|
+ miireset(ctlr->mii);
|
|
|
+
|
|
|
+ p = 0;
|
|
|
+ if(ctlr->txcw & TxcwPs)
|
|
|
+ p |= AnaP;
|
|
|
+ if(ctlr->txcw & TxcwAs)
|
|
|
+ p |= AnaAP;
|
|
|
+ miiane(ctlr->mii, ~0, p, ~0);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int
|
|
|
+at93c46io(Ctlr* ctlr, char* op, int data)
|
|
|
+{
|
|
|
+ char *lp, *p;
|
|
|
+ int i, loop, eecd, r;
|
|
|
+
|
|
|
+ eecd = csr32r(ctlr, Eecd);
|
|
|
+
|
|
|
+ r = 0;
|
|
|
+ loop = -1;
|
|
|
+ lp = nil;
|
|
|
+ for(p = op; *p != '\0'; p++){
|
|
|
+ switch(*p){
|
|
|
+ default:
|
|
|
+ return -1;
|
|
|
+ case ' ':
|
|
|
+ continue;
|
|
|
+ case ':': /* start of loop */
|
|
|
+ loop = strtol(p+1, &lp, 0)-1;
|
|
|
+ lp--;
|
|
|
+ if(p == lp)
|
|
|
+ loop = 7;
|
|
|
+ p = lp;
|
|
|
+ continue;
|
|
|
+ case ';': /* end of loop */
|
|
|
+ if(lp == nil)
|
|
|
+ return -1;
|
|
|
+ loop--;
|
|
|
+ if(loop >= 0)
|
|
|
+ p = lp;
|
|
|
+ else
|
|
|
+ lp = nil;
|
|
|
+ continue;
|
|
|
+ case 'C': /* assert clock */
|
|
|
+ eecd |= Sk;
|
|
|
+ break;
|
|
|
+ case 'c': /* deassert clock */
|
|
|
+ eecd &= ~Sk;
|
|
|
+ break;
|
|
|
+ case 'D': /* next bit in 'data' byte */
|
|
|
+ if(loop < 0)
|
|
|
+ return -1;
|
|
|
+ if(data & (1<<loop))
|
|
|
+ eecd |= Di;
|
|
|
+ else
|
|
|
+ eecd &= ~Di;
|
|
|
+ break;
|
|
|
+ case 'O': /* collect data output */
|
|
|
+ i = (csr32r(ctlr, Eecd) & Do) != 0;
|
|
|
+ if(loop >= 0)
|
|
|
+ r |= (i<<loop);
|
|
|
+ else
|
|
|
+ r = i;
|
|
|
+ continue;
|
|
|
+ case 'I': /* assert data input */
|
|
|
+ eecd |= Di;
|
|
|
+ break;
|
|
|
+ case 'i': /* deassert data input */
|
|
|
+ eecd &= ~Di;
|
|
|
+ break;
|
|
|
+ case 'S': /* enable chip select */
|
|
|
+ eecd |= Cs;
|
|
|
+ break;
|
|
|
+ case 's': /* disable chip select */
|
|
|
+ eecd &= ~Cs;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ csr32w(ctlr, Eecd, eecd);
|
|
|
+ microdelay(1);
|
|
|
+ }
|
|
|
+ if(loop >= 0)
|
|
|
+ return -1;
|
|
|
+ return r;
|
|
|
+}
|
|
|
+
|
|
|
+static int
|
|
|
+at93c46r(Ctlr* ctlr)
|
|
|
+{
|
|
|
+ ushort sum;
|
|
|
+ char rop[20];
|
|
|
+ int addr, areq, bits, data, eecd, i;
|
|
|
+
|
|
|
+ eecd = csr32r(ctlr, Eecd);
|
|
|
+ if(eecd & Spi){
|
|
|
+ print("igbe: SPI EEPROM access not implemented\n");
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
+ if(eecd & Eesz256)
|
|
|
+ bits = 8;
|
|
|
+ else
|
|
|
+ bits = 6;
|
|
|
+ snprint(rop, sizeof(rop), "S :%dDCc;", bits+3);
|
|
|
+
|
|
|
+ sum = 0;
|
|
|
+
|
|
|
+ switch(ctlr->id){
|
|
|
+ default:
|
|
|
+ areq = 0;
|
|
|
+ break;
|
|
|
+ case (0x100E<<16)|0x8086: /* 82540EM */
|
|
|
+ case (0x101E<<16)|0x8086: /* 82540EPLP */
|
|
|
+ areq = 1;
|
|
|
+ csr32w(ctlr, Eecd, eecd|Areq);
|
|
|
+ for(i = 0; i < 1000; i++){
|
|
|
+ if((eecd = csr32r(ctlr, Eecd)) & Agnt)
|
|
|
+ break;
|
|
|
+ microdelay(5);
|
|
|
+ }
|
|
|
+ if(!(eecd & Agnt)){
|
|
|
+ print("igbe: not granted EEPROM access\n");
|
|
|
+ goto release;
|
|
|
+ }
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ for(addr = 0; addr < 0x40; addr++){
|
|
|
+ /*
|
|
|
+ * Read a word at address 'addr' from the Atmel AT93C46
|
|
|
+ * 3-Wire Serial EEPROM or compatible. The EEPROM access is
|
|
|
+ * controlled by 4 bits in Eecd. See the AT93C46 datasheet
|
|
|
+ * for protocol details.
|
|
|
+ */
|
|
|
+ if(at93c46io(ctlr, rop, (0x06<<bits)|addr) != 0){
|
|
|
+ print("igbe: can't set EEPROM address 0x%2.2X\n", addr);
|
|
|
+ goto release;
|
|
|
+ }
|
|
|
+ data = at93c46io(ctlr, ":16COc;", 0);
|
|
|
+ at93c46io(ctlr, "sic", 0);
|
|
|
+ ctlr->eeprom[addr] = data;
|
|
|
+ sum += data;
|
|
|
+ }
|
|
|
+
|
|
|
+release:
|
|
|
+ if(areq)
|
|
|
+ csr32w(ctlr, Eecd, eecd & ~Areq);
|
|
|
+ return sum;
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+detach(Ctlr *ctlr)
|
|
|
+{
|
|
|
+ int r;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Perform a device reset to get the chip back to the
|
|
|
+ * power-on state, followed by an EEPROM reset to read
|
|
|
+ * the defaults for some internal registers.
|
|
|
+ */
|
|
|
+ csr32w(ctlr, Imc, ~0);
|
|
|
+ csr32w(ctlr, Rctl, 0);
|
|
|
+ csr32w(ctlr, Tctl, 0);
|
|
|
+
|
|
|
+ delay(10);
|
|
|
+
|
|
|
+ csr32w(ctlr, Ctrl, Devrst);
|
|
|
+ while(csr32r(ctlr, Ctrl) & Devrst)
|
|
|
+ ;
|
|
|
+
|
|
|
+ csr32w(ctlr, Ctrlext, Eerst);
|
|
|
+ while(csr32r(ctlr, Ctrlext) & Eerst)
|
|
|
+ ;
|
|
|
+
|
|
|
+ switch(ctlr->id){
|
|
|
+ default:
|
|
|
+ break;
|
|
|
+ case (0x100E<<16)|0x8086: /* 82540EM */
|
|
|
+ case (0x101E<<16)|0x8086: /* 82540EPLP */
|
|
|
+ r = csr32r(ctlr, Manc);
|
|
|
+ r &= ~Arpen;
|
|
|
+ csr32w(ctlr, Manc, r);
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ csr32w(ctlr, Imc, ~0);
|
|
|
+ while(csr32r(ctlr, Icr))
|
|
|
+ ;
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+igbedetach(Ether *edev)
|
|
|
+{
|
|
|
+ detach(edev->ctlr);
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+igbeshutdown(Ether* ether)
|
|
|
+{
|
|
|
+print("igbeshutdown\n");
|
|
|
+ igbedetach(ether);
|
|
|
+}
|
|
|
+
|
|
|
+static int
|
|
|
+igbereset(Ctlr* ctlr)
|
|
|
+{
|
|
|
+ int ctrl, i, pause, r, swdpio, txcw;
|
|
|
+
|
|
|
+ detach(ctlr);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Read the EEPROM, validate the checksum
|
|
|
+ * then get the device back to a power-on state.
|
|
|
+ */
|
|
|
+ if((r = at93c46r(ctlr)) != 0xBABA){
|
|
|
+ print("igbe: bad EEPROM checksum - 0x%4.4uX\n", r);
|
|
|
+ return -1;
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Snarf and set up the receive addresses.
|
|
|
+ * There are 16 addresses. The first should be the MAC address.
|
|
|
+ * The others are cleared and not marked valid (MS bit of Rah).
|
|
|
+ */
|
|
|
+ for(i = Ea; i < Eaddrlen/2; i++){
|
|
|
+ ctlr->ra[2*i] = ctlr->eeprom[i];
|
|
|
+ ctlr->ra[2*i+1] = ctlr->eeprom[i]>>8;
|
|
|
+ }
|
|
|
+ r = (ctlr->ra[3]<<24)|(ctlr->ra[2]<<16)|(ctlr->ra[1]<<8)|ctlr->ra[0];
|
|
|
+ csr32w(ctlr, Ral, r);
|
|
|
+ r = 0x80000000|(ctlr->ra[5]<<8)|ctlr->ra[4];
|
|
|
+ csr32w(ctlr, Rah, r);
|
|
|
+ for(i = 1; i < 16; i++){
|
|
|
+ csr32w(ctlr, Ral+i*8, 0);
|
|
|
+ csr32w(ctlr, Rah+i*8, 0);
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Clear the Multicast Table Array.
|
|
|
+ * It's a 4096 bit vector accessed as 128 32-bit registers.
|
|
|
+ */
|
|
|
+ memset(ctlr->mta, 0, sizeof(ctlr->mta));
|
|
|
+ for(i = 0; i < 128; i++)
|
|
|
+ csr32w(ctlr, Mta+i*4, 0);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Just in case the Eerst didn't load the defaults
|
|
|
+ * (doesn't appear to fully on the 8243GC), do it manually.
|
|
|
+ */
|
|
|
+ txcw = csr32r(ctlr, Txcw);
|
|
|
+ txcw &= ~(TxcwAne|TxcwPauseMASK|TxcwFd);
|
|
|
+ ctrl = csr32r(ctlr, Ctrl);
|
|
|
+ ctrl &= ~(SwdpioloMASK|Frcspd|Ilos|Lrst|Fd);
|
|
|
+
|
|
|
+ if(ctlr->eeprom[Icw1] & 0x0400){
|
|
|
+ ctrl |= Fd;
|
|
|
+ txcw |= TxcwFd;
|
|
|
+ }
|
|
|
+ if(ctlr->eeprom[Icw1] & 0x0200)
|
|
|
+ ctrl |= Lrst;
|
|
|
+ if(ctlr->eeprom[Icw1] & 0x0010)
|
|
|
+ ctrl |= Ilos;
|
|
|
+ if(ctlr->eeprom[Icw1] & 0x0800)
|
|
|
+ ctrl |= Frcspd;
|
|
|
+ swdpio = (ctlr->eeprom[Icw1] & 0x01E0)>>5;
|
|
|
+ ctrl |= swdpio<<SwdpioloSHIFT;
|
|
|
+ csr32w(ctlr, Ctrl, ctrl);
|
|
|
+
|
|
|
+ ctrl = csr32r(ctlr, Ctrlext);
|
|
|
+ ctrl &= ~(Ips|SwdpiohiMASK);
|
|
|
+ swdpio = (ctlr->eeprom[Icw2] & 0x00F0)>>4;
|
|
|
+ if(ctlr->eeprom[Icw1] & 0x1000)
|
|
|
+ ctrl |= Ips;
|
|
|
+ ctrl |= swdpio<<SwdpiohiSHIFT;
|
|
|
+ csr32w(ctlr, Ctrlext, ctrl);
|
|
|
+
|
|
|
+ if(ctlr->eeprom[Icw2] & 0x0800)
|
|
|
+ txcw |= TxcwAne;
|
|
|
+ pause = (ctlr->eeprom[Icw2] & 0x3000)>>12;
|
|
|
+ txcw |= pause<<TxcwPauseSHIFT;
|
|
|
+ switch(pause){
|
|
|
+ default:
|
|
|
+ ctlr->fcrtl = 0x00002000;
|
|
|
+ ctlr->fcrth = 0x00004000;
|
|
|
+ txcw |= TxcwAs|TxcwPs;
|
|
|
+ break;
|
|
|
+ case 0:
|
|
|
+ ctlr->fcrtl = 0x00002000;
|
|
|
+ ctlr->fcrth = 0x00004000;
|
|
|
+ break;
|
|
|
+ case 2:
|
|
|
+ ctlr->fcrtl = 0;
|
|
|
+ ctlr->fcrth = 0;
|
|
|
+ txcw |= TxcwAs;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ ctlr->txcw = txcw;
|
|
|
+ csr32w(ctlr, Txcw, txcw);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Flow control - values from the datasheet.
|
|
|
+ */
|
|
|
+ csr32w(ctlr, Fcal, 0x00C28001);
|
|
|
+ csr32w(ctlr, Fcah, 0x00000100);
|
|
|
+ csr32w(ctlr, Fct, 0x00008808);
|
|
|
+ csr32w(ctlr, Fcttv, 0x00000100);
|
|
|
+
|
|
|
+ csr32w(ctlr, Fcrtl, ctlr->fcrtl);
|
|
|
+ csr32w(ctlr, Fcrth, ctlr->fcrth);
|
|
|
+
|
|
|
+ ilock(&ctlr->imlock);
|
|
|
+ csr32w(ctlr, Imc, ~0);
|
|
|
+ ctlr->im = Lsc;
|
|
|
+ csr32w(ctlr, Ims, ctlr->im);
|
|
|
+ iunlock(&ctlr->imlock);
|
|
|
+
|
|
|
+ if(!(csr32r(ctlr, Status) & Tbimode) && igbemii(ctlr) < 0) {
|
|
|
+ print("igbe: igbemii failed\n");
|
|
|
+ return -1;
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void
|
|
|
+igbepci(void)
|
|
|
+{
|
|
|
+ int port, cls;
|
|
|
+ Pcidev *p;
|
|
|
+ Ctlr *ctlr;
|
|
|
+
|
|
|
+ p = nil;
|
|
|
+ while(p = pcimatch(p, 0, 0)){
|
|
|
+ if(p->ccrb != 0x02 || p->ccru != 0)
|
|
|
+ continue;
|
|
|
+
|
|
|
+ switch((p->did<<16)|p->vid){
|
|
|
+ case (0x1000<<16)|0x8086: /* LSI L2A1157 (82542) */
|
|
|
+ default:
|
|
|
+ continue;
|
|
|
+ case (0x1001<<16)|0x8086: /* Intel PRO/1000 F */
|
|
|
+ break;
|
|
|
+ case (0x1004<<16)|0x8086: /* 82543GC - copper (PRO/1000 T) */
|
|
|
+ case (0x1008<<16)|0x8086: /* 82544EI - copper */
|
|
|
+ case (0x100E<<16)|0x8086: /* 82540EM - copper */
|
|
|
+ case (0x101E<<16)|0x8086: /* 82540EPLP - copper */
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ port = upamalloc(p->mem[0].bar & ~0x0F, p->mem[0].size, 0);
|
|
|
+ if(port == 0){
|
|
|
+ print("igbe: can't map %8.8luX\n", p->mem[0].bar);
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * from etherga620.c:
|
|
|
+ * If PCI Write-and-Invalidate is enabled set the max write DMA
|
|
|
+ * value to the host cache-line size (32 on Pentium or later).
|
|
|
+ */
|
|
|
+ if(p->pcr & MemWrInv){
|
|
|
+ cls = pcicfgr8(p, PciCLS) * 4;
|
|
|
+ if(cls != CACHELINESZ)
|
|
|
+ pcicfgw8(p, PciCLS, CACHELINESZ/4);
|
|
|
+ }
|
|
|
+
|
|
|
+ cls = pcicfgr8(p, PciCLS);
|
|
|
+ switch(cls){
|
|
|
+ default:
|
|
|
+ print("igbe: unexpected CLS - %d bytes\n",
|
|
|
+ cls*sizeof(long));
|
|
|
+ break;
|
|
|
+ case 0x00:
|
|
|
+ case 0xFF:
|
|
|
+ /* alphapc 164lx returns 0 */
|
|
|
+ print("igbe: unusable PciCLS: %d, using %d longs\n",
|
|
|
+ cls, CACHELINESZ/sizeof(long));
|
|
|
+ cls = CACHELINESZ/sizeof(long);
|
|
|
+ pcicfgw8(p, PciCLS, cls);
|
|
|
+ break;
|
|
|
+ case 0x08:
|
|
|
+ case 0x10:
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ ctlr = malloc(sizeof(Ctlr));
|
|
|
+ ctlr->port = port;
|
|
|
+ ctlr->pcidev = p;
|
|
|
+ ctlr->id = (p->did<<16)|p->vid;
|
|
|
+ ctlr->cls = cls*4;
|
|
|
+ ctlr->nic = KADDR(ctlr->port);
|
|
|
+print("status0 %8.8uX\n", csr32r(ctlr, Status));
|
|
|
+ if(igbereset(ctlr)){
|
|
|
+ free(ctlr);
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+print("status1 %8.8uX\n", csr32r(ctlr, Status));
|
|
|
+ pcisetbme(p);
|
|
|
+
|
|
|
+ if(ctlrhead != nil)
|
|
|
+ ctlrtail->next = ctlr;
|
|
|
+ else
|
|
|
+ ctlrhead = ctlr;
|
|
|
+ ctlrtail = ctlr;
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+int
|
|
|
+igbepnp(Ether* edev)
|
|
|
+{
|
|
|
+ int i;
|
|
|
+ Ctlr *ctlr;
|
|
|
+ uchar ea[Eaddrlen];
|
|
|
+
|
|
|
+ if(ctlrhead == nil)
|
|
|
+ igbepci();
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Any adapter matches if no edev->port is supplied,
|
|
|
+ * otherwise the ports must match.
|
|
|
+ */
|
|
|
+ for(ctlr = ctlrhead; ctlr != nil; ctlr = ctlr->next){
|
|
|
+ if(ctlr->active)
|
|
|
+ continue;
|
|
|
+ if(edev->port == 0 || edev->port == ctlr->port){
|
|
|
+ ctlr->active = 1;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ if(ctlr == nil)
|
|
|
+ return -1;
|
|
|
+
|
|
|
+ edev->ctlr = ctlr;
|
|
|
+ edev->port = ctlr->port;
|
|
|
+ edev->irq = ctlr->pcidev->intl;
|
|
|
+ edev->tbdf = ctlr->pcidev->tbdf;
|
|
|
+// edev->mbps = 1000;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Check if the adapter's station address is to be overridden.
|
|
|
+ * If not, read it from the EEPROM and set in ether->ea prior to
|
|
|
+ * loading the station address in the hardware.
|
|
|
+ */
|
|
|
+ memset(ea, 0, Eaddrlen);
|
|
|
+ if(memcmp(ea, edev->ea, Eaddrlen) == 0){
|
|
|
+ for(i = 0; i < Eaddrlen/2; i++){
|
|
|
+ edev->ea[2*i] = ctlr->eeprom[i];
|
|
|
+ edev->ea[2*i+1] = ctlr->eeprom[i]>>8;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ igbeinit(edev);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Linkage to the generic ethernet driver.
|
|
|
+ */
|
|
|
+ edev->attach = igbeattach;
|
|
|
+ edev->transmit = igbetransmit;
|
|
|
+ edev->interrupt = igbeinterrupt;
|
|
|
+ edev->detach = igbedetach;
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
David du Colombier