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@@ -27,6 +27,7 @@ i & d L1 caches, 16K each, 4 ways, 64 sets, 64-byte lines
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can invalidate entire i-cache only
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can clean or invalidate by set and way data/unified cache
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unified L2 PIPT cache, 256K, 8 ways, 512 sets, 64-byte lines
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+no hardware cache coherence
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l3 interconnect firewalls are all off at boot time, except for a bit of
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secure ram
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@@ -81,6 +82,16 @@ Video
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The video controller may be documented and source is available for a
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Linux driver.
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+___
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+
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+The code is fairly heavy-handed with the use of barrier instructions
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+(BARRIERS in assembler, coherence in C), partly in reaction to bad
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+experience doing Power PC ports, but also just as precautions against
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+modern processors, which may feel free to execute instructions out of
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+order or some time later, store to memory out of order or some time
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+later, otherwise break the model of traditional sequential processors,
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+or any combination of the above.
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+___
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There are a few rough edges:
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