riscv: check the bits 7-8 for page size, not 9-10

I uncovered this bug when porting to lowrisc.

Once the toolchain settles down we can turn this into something
more symbolic.

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>

sys/src/9/riscv/mmu.c

@@ -763,8 +763,8 @@ mmuinit(void)
 	if((l = mmuwalk(root, KSEG0, 2, &KzeroPTE, nil)) < 0) {
 		panic("Can't walk to PtePML2");
 	}
-	print("KzeroPTE is 0x%llx\n", KzeroPTE);
-	int PTLevels = (*KzeroPTE>>9)&3;
+	print("KzeroPTE is 0x%llx, *KzeroPTE is 0x%llx\n", KzeroPTE, *KzeroPTE);
+	int PTLevels = (*KzeroPTE>>7)&3;
 	switch(PTLevels) {
 	default:
 		panic("unsupported number of page table levels: %d", PTLevels);