arch 3.0 KB

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  1. .TH ARCH 3
  2. .SH NAME
  3. arch \- architecture-specific information and control
  4. .SH SYNOPSIS
  5. .nf
  6. .B bind -a #P /dev
  7. .sp 0.3v
  8. .B /dev/archctl
  9. .B /dev/cputype
  10. .B /dev/ioalloc
  11. .B /dev/iob
  12. .B /dev/iol
  13. .B /dev/iow
  14. .B /dev/irqalloc
  15. .SH DESCRIPTION
  16. This device presents textual information about PC hardware and allows
  17. user-level control of the I/O ports on x86-class and DEC Alpha machines.
  18. .PP
  19. Reads from
  20. .I cputype
  21. recover the processor type and clock rate in MHz.
  22. Reads from
  23. .I archctl
  24. yield at least data of this form:
  25. .IP
  26. .EX
  27. cpu AMD64 2201 pge
  28. pge on
  29. coherence mfence
  30. cmpswap cmpswap486
  31. i8253set on
  32. cache default uc
  33. cache 0x0 1073741824 wb
  34. cache 0x3ff00000 1048576 uc
  35. .EE
  36. .LP
  37. Where
  38. .L AMD64
  39. is the processor type,
  40. .L 2201
  41. is the processor speed in MHz,
  42. and
  43. .L pge
  44. is present only if the `page global extension' capability is present;
  45. the next line reflects its setting.
  46. .L coherence
  47. is followed by one of
  48. .LR mb386 ,
  49. .LR mb586 ,
  50. .L mfence
  51. or
  52. .LR nop ,
  53. showing the form of memory barrier used by the kernel.
  54. .L cmpswap
  55. is followed by
  56. .L cmpswap386
  57. or
  58. .LR cmpswap486 ,
  59. reflecting the form of `compare and swap' used by the kernel.
  60. .L i8253set
  61. is a flag, indicating the need to explicitly set
  62. the Intel 8253 or equivalent timer.
  63. There may be lines starting with
  64. .L cache
  65. that reflect the state of memory caching via MTRRs
  66. (memory-type region registers).
  67. The second word on the line is
  68. .L default
  69. or a C-style number which is the base physical address of the region;
  70. the third is a C-style length of the region;
  71. and the fourth is one of
  72. .LR uc
  73. (for uncachable),
  74. .LR wb
  75. (write-back),
  76. .LR wc
  77. (write-combining),
  78. .LR wp
  79. (write-protected),
  80. or
  81. .LR wt
  82. (write-through).
  83. A region may be a subset of another region, and the smaller region
  84. takes precedence.
  85. This may be used to make I/O registers uncachable
  86. in the midst of a write-combining region mostly used
  87. for a video framebuffer, for example.
  88. Control messages may be written to
  89. .I archctl
  90. and use the same syntax as the data read from
  91. .IR archctl .
  92. Known commands include
  93. .LR cache ,
  94. .LR coherence ,
  95. .LR i8253set ,
  96. and
  97. .LR pge .
  98. .
  99. .PP
  100. Reads from
  101. .I ioalloc
  102. return I/O ranges used by each device, one line
  103. per range.
  104. Each line contains three fields separated by white space: first address
  105. in hexadecimal,
  106. last address, name of device.
  107. .PP
  108. Reads from
  109. .I irqalloc
  110. return the enabled interrupts, one line per
  111. interrupt. Each line contains three fields separated by white space:
  112. the trap number, the IRQ it is assigned to, and the name of
  113. the device using it.
  114. .PP
  115. Reads and writes to
  116. .IR iob ,
  117. .IR iow ,
  118. and
  119. .I iol
  120. cause 8-bit wide, 16-bit wide, and 32-bit wide requests to
  121. I/O ports.
  122. The port accessed is determined by the byte offset of the
  123. file descriptor.
  124. .SH EXAMPLE
  125. The following code reads from an x86 byte I/O port.
  126. .IP
  127. .EX
  128. uchar
  129. inportb(unsigned port)
  130. {
  131. uchar data;
  132. if(iobfd == -1)
  133. iobfd = open("#P/iob", ORDWR);
  134. seek(iobfd, port, 0);
  135. if(read(iobfd, &data, sizeof(data)) != sizeof(data))
  136. sysfatal("inportb(0x%4.4ux): %r", port);
  137. return data;
  138. }
  139. .EE
  140. .SH SOURCE
  141. .B /sys/src/9/pc/devarch.c