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  1. <html>
  2. <title>
  3. data
  4. </title>
  5. <body BGCOLOR="#FFFFFF" TEXT="#000000" LINK="#0000FF" VLINK="#330088" ALINK="#FF0044">
  6. <H1>A Manual for the Plan 9 assembler
  7. </H1>
  8. <DL><DD><I>Rob Pike<br>
  9. rob@plan9.bell-labs.com<br>
  10. </I></DL>
  11. <H4>Machines
  12. </H4>
  13. <P>
  14. There is an assembler for each of the MIPS, SPARC, Intel 386,
  15. Intel 960, AMD 29000, Motorola 68020 and 68000, Motorola Power PC, DEC Alpha, and Acorn ARM.
  16. The 68020 assembler,
  17. <TT>2a</TT>,
  18. is the oldest and in many ways the prototype.
  19. The assemblers are really just variations of a single program:
  20. they share many properties such as left-to-right assignment order for
  21. instruction operands and the synthesis of macro instructions
  22. such as
  23. <TT>MOVE</TT>
  24. to hide the peculiarities of the load and store structure of the machines.
  25. To keep things concrete, the first part of this manual is
  26. specifically about the 68020.
  27. At the end is a description of the differences among
  28. the other assemblers.
  29. </P>
  30. <P>
  31. The document, ``How to Use the Plan 9 C Compiler'', by Rob Pike,
  32. is a prerequisite for this manual.
  33. </P>
  34. <H4>Registers
  35. </H4>
  36. <P>
  37. All pre-defined symbols in the assembler are upper-case.
  38. Data registers are
  39. <TT>R0</TT>
  40. through
  41. <TT>R7</TT>;
  42. address registers are
  43. <TT>A0</TT>
  44. through
  45. <TT>A7</TT>;
  46. floating-point registers are
  47. <TT>F0</TT>
  48. through
  49. <TT>F7</TT>.
  50. </P>
  51. <P>
  52. A pointer in
  53. <TT>A6</TT>
  54. is used by the C compiler to point to data, enabling short addresses to
  55. be used more often.
  56. The value of
  57. <TT>A6</TT>
  58. is constant and must be set during C program initialization
  59. to the address of the externally-defined symbol
  60. <TT>a6base</TT>.
  61. </P>
  62. <P>
  63. The following hardware registers are defined in the assembler; their
  64. meaning should be obvious given a 68020 manual:
  65. <TT>CAAR</TT>,
  66. <TT>CACR</TT>,
  67. <TT>CCR</TT>,
  68. <TT>DFC</TT>,
  69. <TT>ISP</TT>,
  70. <TT>MSP</TT>,
  71. <TT>SFC</TT>,
  72. <TT>SR</TT>,
  73. <TT>USP</TT>,
  74. and
  75. <TT>VBR</TT>.
  76. </P>
  77. <P>
  78. The assembler also defines several pseudo-registers that
  79. manipulate the stack:
  80. <TT>FP</TT>,
  81. <TT>SP</TT>,
  82. and
  83. <TT>TOS</TT>.
  84. <TT>FP</TT>
  85. is the frame pointer, so
  86. <TT>0(FP)</TT>
  87. is the first argument,
  88. <TT>4(FP)</TT>
  89. is the second, and so on.
  90. <TT>SP</TT>
  91. is the local stack pointer, where automatic variables are held
  92. (SP is a pseudo-register only on the 68020);
  93. <TT>0(SP)</TT>
  94. is the first automatic, and so on as with
  95. <TT>FP</TT>.
  96. Finally,
  97. <TT>TOS</TT>
  98. is the top-of-stack register, used for pushing parameters to procedures,
  99. saving temporary values, and so on.
  100. </P>
  101. <P>
  102. The assembler and loader track these pseudo-registers so
  103. the above statements are true regardless of what has been
  104. pushed on the hardware stack, pointed to by
  105. <TT>A7</TT>.
  106. The name
  107. <TT>A7</TT>
  108. refers to the hardware stack pointer, but beware of mixed use of
  109. <TT>A7</TT>
  110. and the above stack-related pseudo-registers, which will cause trouble.
  111. Note, too, that the
  112. <TT>PEA</TT>
  113. instruction is observed by the loader to
  114. alter SP and thus will insert a corresponding pop before all returns.
  115. The assembler accepts a label-like name to be attached to
  116. <TT>FP</TT>
  117. and
  118. <TT>SP</TT>
  119. uses, such as
  120. <TT>p+0(FP)</TT>,
  121. to help document that
  122. <TT>p</TT>
  123. is the first argument to a routine.
  124. The name goes in the symbol table but has no significance to the result
  125. of the program.
  126. </P>
  127. <H4>Referring to data
  128. </H4>
  129. <P>
  130. All external references must be made relative to some pseudo-register,
  131. either
  132. <TT>PC</TT>
  133. (the virtual program counter) or
  134. <TT>SB</TT>
  135. (the ``static base'' register).
  136. <TT>PC</TT>
  137. counts instructions, not bytes of data.
  138. For example, to branch to the second following instruction, that is,
  139. to skip one instruction, one may write
  140. <DL><DT><DD><TT><PRE>
  141. BRA 2(PC)
  142. </PRE></TT></DL>
  143. Labels are also allowed, as in
  144. <DL><DT><DD><TT><PRE>
  145. BRA return
  146. NOP
  147. return:
  148. RTS
  149. </PRE></TT></DL>
  150. When using labels, there is no
  151. <TT>(PC)</TT>
  152. annotation.
  153. </P>
  154. <P>
  155. The pseudo-register
  156. <TT>SB</TT>
  157. refers to the beginning of the address space of the program.
  158. Thus, references to global data and procedures are written as
  159. offsets to
  160. <TT>SB</TT>,
  161. as in
  162. <DL><DT><DD><TT><PRE>
  163. MOVL $array(SB), TOS
  164. </PRE></TT></DL>
  165. to push the address of a global array on the stack, or
  166. <DL><DT><DD><TT><PRE>
  167. MOVL array+4(SB), TOS
  168. </PRE></TT></DL>
  169. to push the second (4-byte) element of the array.
  170. Note the use of an offset; the complete list of addressing modes is given below.
  171. Similarly, subroutine calls must use
  172. <TT>SB</TT>:
  173. <DL><DT><DD><TT><PRE>
  174. BSR exit(SB)
  175. </PRE></TT></DL>
  176. File-static variables have syntax
  177. <DL><DT><DD><TT><PRE>
  178. local&#60;&#62;+4(SB)
  179. </PRE></TT></DL>
  180. The
  181. <TT><></TT>
  182. will be filled in at load time by a unique integer.
  183. </P>
  184. <P>
  185. When a program starts, it must execute
  186. <DL><DT><DD><TT><PRE>
  187. MOVL $a6base(SB), A6
  188. </PRE></TT></DL>
  189. before accessing any global data.
  190. (On machines such as the MIPS and SPARC that cannot load a register
  191. in a single instruction, constants are loaded through the static base
  192. register. The loader recognizes code that initializes the static
  193. base register and treats it specially. You must be careful, however,
  194. not to load large constants on such machines when the static base
  195. register is not set up, such as early in interrupt routines.)
  196. </P>
  197. <H4>Expressions
  198. </H4>
  199. <P>
  200. Expressions are mostly what one might expect.
  201. Where an offset or a constant is expected,
  202. a primary expression with unary operators is allowed.
  203. A general C constant expression is allowed in parentheses.
  204. </P>
  205. <P>
  206. Source files are preprocessed exactly as in the C compiler, so
  207. <TT>#define</TT>
  208. and
  209. <TT>#include</TT>
  210. work.
  211. </P>
  212. <H4>Addressing modes
  213. </H4>
  214. <P>
  215. The simple addressing modes are shared by all the assemblers.
  216. Here, for completeness, follows a table of all the 68020 addressing modes,
  217. since that machine has the richest set.
  218. In the table,
  219. <TT>o</TT>
  220. is an offset, which if zero may be elided, and
  221. <TT>d</TT>
  222. is a displacement, which is a constant between -128 and 127 inclusive.
  223. Many of the modes listed have the same name;
  224. scrutiny of the format will show what default is being applied.
  225. For instance, indexed mode with no address register supplied operates
  226. as though a zero-valued register were used.
  227. For "offset" read "displacement."
  228. For "<TT>.s</TT>" read one of
  229. <TT>.L</TT>,
  230. or
  231. <TT>.W</TT>
  232. followed by
  233. <TT>*1</TT>,
  234. <TT>*2</TT>,
  235. <TT>*4</TT>,
  236. or
  237. <TT>*8</TT>
  238. to indicate the size and scaling of the data.
  239. </P>
  240. <DL>
  241. <DT><DT>&#32;<DD>
  242. <br><img src="data.10610.gif"><br>
  243. </dl>
  244. <H4>Laying down data
  245. </H4>
  246. <P>
  247. Placing data in the instruction stream, say for interrupt vectors, is easy:
  248. the pseudo-instructions
  249. <TT>LONG</TT>
  250. and
  251. <TT>WORD</TT>
  252. (but not
  253. <TT>BYTE</TT>)
  254. lay down the value of their single argument, of the appropriate size,
  255. as if it were an instruction:
  256. <DL><DT><DD><TT><PRE>
  257. LONG $12345
  258. </PRE></TT></DL>
  259. places the long 12345 (base 10)
  260. in the instruction stream.
  261. (On most machines,
  262. the only such operator is
  263. <TT>WORD</TT>
  264. and it lays down 32-bit quantities.
  265. The 386 has all three:
  266. <TT>LONG</TT>,
  267. <TT>WORD</TT>,
  268. and
  269. <TT>BYTE</TT>.
  270. The 960 has only one,
  271. <TT>LONG</TT>.)
  272. </P>
  273. <P>
  274. Placing information in the data section is more painful.
  275. The pseudo-instruction
  276. <TT>DATA</TT>
  277. does the work, given two arguments: an address at which to place the item,
  278. including its size,
  279. and the value to place there. For example, to define a character array
  280. <TT>array</TT>
  281. containing the characters
  282. <TT>abc</TT>
  283. and a terminating null:
  284. <DL><DT><DD><TT><PRE>
  285. DATA array+0(SB)/1, $'a'
  286. DATA array+1(SB)/1, $'b'
  287. DATA array+2(SB)/1, $'c'
  288. GLOBL array(SB), $4
  289. </PRE></TT></DL>
  290. or
  291. <DL><DT><DD><TT><PRE>
  292. DATA array+0(SB)/4, $"abc\z"
  293. GLOBL array(SB), $4
  294. </PRE></TT></DL>
  295. The
  296. <TT>/1</TT>
  297. defines the number of bytes to define,
  298. <TT>GLOBL</TT>
  299. makes the symbol global, and the
  300. <TT>$4</TT>
  301. says how many bytes the symbol occupies.
  302. Uninitialized data is zeroed automatically.
  303. The character
  304. <TT>z</TT>
  305. is equivalent to the C
  306. <TT> .</TT>
  307. The string in a
  308. <TT>DATA</TT>
  309. statement may contain a maximum of eight bytes;
  310. build larger strings piecewise.
  311. Two pseudo-instructions,
  312. <TT>DYNT</TT>
  313. and
  314. <TT>INIT</TT>,
  315. allow the (obsolete) Alef compilers to build dynamic type information during the load
  316. phase.
  317. The
  318. <TT>DYNT</TT>
  319. pseudo-instruction has two forms:
  320. <DL><DT><DD><TT><PRE>
  321. DYNT , ALEF_SI_5+0(SB)
  322. DYNT ALEF_AS+0(SB), ALEF_SI_5+0(SB)
  323. </PRE></TT></DL>
  324. In the first form,
  325. <TT>DYNT</TT>
  326. defines the symbol to be a small unique integer constant, chosen by the loader,
  327. which is some multiple of the word size. In the second form,
  328. <TT>DYNT</TT>
  329. defines the second symbol in the same way,
  330. places the address of the most recently
  331. defined text symbol in the array specified by the first symbol at the
  332. index defined by the value of the second symbol,
  333. and then adjusts the size of the array accordingly.
  334. </P>
  335. <P>
  336. The
  337. <TT>INIT</TT>
  338. pseudo-instruction takes the same parameters as a
  339. <TT>DATA</TT>
  340. statement. Its symbol is used as the base of an array and the
  341. data item is installed in the array at the offset specified by the most recent
  342. <TT>DYNT</TT>
  343. pseudo-instruction.
  344. The size of the array is adjusted accordingly.
  345. The
  346. <TT>DYNT</TT>
  347. and
  348. <TT>INIT</TT>
  349. pseudo-instructions are not implemented on the 68020.
  350. </P>
  351. <H4>Defining a procedure
  352. </H4>
  353. <P>
  354. Entry points are defined by the pseudo-operation
  355. <TT>TEXT</TT>,
  356. which takes as arguments the name of the procedure (including the ubiquitous
  357. <TT>(SB)</TT>)
  358. and the number of bytes of automatic storage to pre-allocate on the stack,
  359. which will usually be zero when writing assembly language programs.
  360. On machines with a link register, such as the MIPS and SPARC,
  361. the special value -4 instructs the loader to generate no PC save
  362. and restore instructions, even if the function is not a leaf.
  363. Here is a complete procedure that returns the sum
  364. of its two arguments:
  365. <DL><DT><DD><TT><PRE>
  366. TEXT sum(SB), $0
  367. MOVL arg1+0(FP), R0
  368. ADDL arg2+4(FP), R0
  369. RTS
  370. </PRE></TT></DL>
  371. An optional middle argument
  372. to the
  373. <TT>TEXT</TT>
  374. pseudo-op is a bit field of options to the loader.
  375. Setting the 1 bit suspends profiling the function when profiling is enabled for the rest of
  376. the program.
  377. For example,
  378. <DL><DT><DD><TT><PRE>
  379. TEXT sum(SB), 1, $0
  380. MOVL arg1+0(FP), R0
  381. ADDL arg2+4(FP), R0
  382. RTS
  383. </PRE></TT></DL>
  384. will not be profiled; the first version above would be.
  385. Subroutines with peculiar state, such as system call routines,
  386. should not be profiled.
  387. </P>
  388. <P>
  389. Setting the 2 bit allows multiple definitions of the same
  390. <TT>TEXT</TT>
  391. symbol in a program; the loader will place only one such function in the image.
  392. It was emitted only by the Alef compilers.
  393. </P>
  394. <P>
  395. Subroutines to be called from C should place their result in
  396. <TT>R0</TT>,
  397. even if it is an address.
  398. Floating point values are returned in
  399. <TT>F0</TT>.
  400. Functions that return a structure to a C program
  401. receive as their first argument the address of the location to
  402. store the result;
  403. <TT>R0</TT>
  404. is unused in the calling protocol for such procedures.
  405. A subroutine is responsible for saving its own registers,
  406. and therefore is free to use any registers without saving them (``caller saves'').
  407. <TT>A6</TT>
  408. and
  409. <TT>A7</TT>
  410. are the exceptions as described above.
  411. </P>
  412. <H4>When in doubt
  413. </H4>
  414. <P>
  415. If you get confused, try using the
  416. <TT>-S</TT>
  417. option to
  418. <TT>2c</TT>
  419. and compiling a sample program.
  420. The standard output is valid input to the assembler.
  421. </P>
  422. <H4>Instructions
  423. </H4>
  424. <P>
  425. The instruction set of the assembler is not identical to that
  426. of the machine.
  427. It is chosen to match what the compiler generates, augmented
  428. slightly by specific needs of the operating system.
  429. For example,
  430. <TT>2a</TT>
  431. does not distinguish between the various forms of
  432. <TT>MOVE</TT>
  433. instruction: move quick, move address, etc. Instead the context
  434. does the job. For example,
  435. <DL><DT><DD><TT><PRE>
  436. MOVL $1, R1
  437. MOVL A0, R2
  438. MOVW SR, R3
  439. </PRE></TT></DL>
  440. generates official
  441. <TT>MOVEQ</TT>,
  442. <TT>MOVEA</TT>,
  443. and
  444. <TT>MOVESR</TT>
  445. instructions.
  446. A number of instructions do not have the syntax necessary to specify
  447. their entire capabilities. Notable examples are the bitfield
  448. instructions, the
  449. multiply and divide instructions, etc.
  450. For a complete set of generated instruction names (in
  451. <TT>2a</TT>
  452. notation, not Motorola's) see the file
  453. <TT>/sys/src/cmd/2c/2.out.h</TT>.
  454. Despite its name, this file contains an enumeration of the
  455. instructions that appear in the intermediate files generated
  456. by the compiler, which correspond exactly to lines of assembly language.
  457. </P>
  458. <P>
  459. The MC68000 assembler,
  460. <TT>1a</TT>,
  461. is essentially the same, honoring the appropriate subset of the instructions
  462. and addressing modes.
  463. The definitions of these are, nonetheless, part of
  464. <TT>2.out.h</TT>.
  465. </P>
  466. <H4>Laying down instructions
  467. </H4>
  468. <P>
  469. The loader modifies the code produced by the assembler and compiler.
  470. It folds branches,
  471. copies short sequences of code to eliminate branches,
  472. and discards unreachable code.
  473. The first instruction of every function is assumed to be reachable.
  474. The pseudo-instruction
  475. <TT>NOP</TT>,
  476. which you may see in compiler output,
  477. means no instruction at all, rather than an instruction that does nothing.
  478. The loader discards all
  479. <TT>NOP</TT>'s.
  480. </P>
  481. <P>
  482. To generate a true
  483. <TT>NOP</TT>
  484. instruction, or any other instruction not known to the assembler, use a
  485. <TT>WORD</TT>
  486. pseudo-instruction.
  487. Such instructions on RISCs are not scheduled by the loader and must have
  488. their delay slots filled manually.
  489. </P>
  490. <H4>MIPS
  491. </H4>
  492. <P>
  493. The registers are only addressed by number:
  494. <TT>R0</TT>
  495. through
  496. <TT>R31</TT>.
  497. <TT>R29</TT>
  498. is the stack pointer;
  499. <TT>R30</TT>
  500. is used as the static base pointer, the analogue of
  501. <TT>A6</TT>
  502. on the 68020.
  503. Its value is the address of the global symbol
  504. <TT>setR30(SB)</TT>.
  505. The register holding returned values from subroutines is
  506. <TT>R1</TT>.
  507. When a function is called, space for the first argument
  508. is reserved at
  509. <TT>0(FP)</TT>
  510. but in C (not Alef) the value is passed in
  511. <TT>R1</TT>
  512. instead.
  513. </P>
  514. <P>
  515. The loader uses
  516. <TT>R28</TT>
  517. as a temporary. The system uses
  518. <TT>R26</TT>
  519. and
  520. <TT>R27</TT>
  521. as interrupt-time temporaries. Therefore none of these registers
  522. should be used in user code.
  523. </P>
  524. <P>
  525. The control registers are not known to the assembler.
  526. Instead they are numbered registers
  527. <TT>M0</TT>,
  528. <TT>M1</TT>,
  529. etc.
  530. Use this trick to access, say,
  531. <TT>STATUS</TT>:
  532. <DL><DT><DD><TT><PRE>
  533. #define STATUS 12
  534. MOVW M(STATUS), R1
  535. </PRE></TT></DL>
  536. </P>
  537. <P>
  538. Floating point registers are called
  539. <TT>F0</TT>
  540. through
  541. <TT>F31</TT>.
  542. By convention,
  543. <TT>F24</TT>
  544. must be initialized to the value 0.0,
  545. <TT>F26</TT>
  546. to 0.5,
  547. <TT>F28</TT>
  548. to 1.0, and
  549. <TT>F30</TT>
  550. to 2.0;
  551. this is done by the operating system.
  552. </P>
  553. <P>
  554. The instructions and their syntax are different from those of the manufacturer's
  555. manual.
  556. There are no
  557. <TT>lui</TT>
  558. and kin; instead there are
  559. <TT>MOVW</TT>
  560. (move word),
  561. <TT>MOVH</TT>
  562. (move halfword),
  563. and
  564. <TT>MOVB</TT>
  565. (move byte) pseudo-instructions. If the operand is unsigned, the instructions
  566. are
  567. <TT>MOVHU</TT>
  568. and
  569. <TT>MOVBU</TT>.
  570. The order of operands is from left to right in dataflow order, just as
  571. on the 68020 but not as in MIPS documentation.
  572. This means that the
  573. <TT>Bcond</TT>
  574. instructions are reversed with respect to the book; for example, a
  575. <TT>va</TT>
  576. <TT>BGTZ</TT>
  577. generates a MIPS
  578. <TT>bltz</TT>
  579. instruction.
  580. </P>
  581. <P>
  582. The assembler is for the R2000, R3000, and most of the R4000 and R6000 architectures.
  583. It understands the 64-bit instructions
  584. <TT>MOVV</TT>,
  585. <TT>MOVVL</TT>,
  586. <TT>ADDV</TT>,
  587. <TT>ADDVU</TT>,
  588. <TT>SUBV</TT>,
  589. <TT>SUBVU</TT>,
  590. <TT>MULV</TT>,
  591. <TT>MULVU</TT>,
  592. <TT>DIVV</TT>,
  593. <TT>DIVVU</TT>,
  594. <TT>SLLV</TT>,
  595. <TT>SRLV</TT>,
  596. and
  597. <TT>SRAV</TT>.
  598. The assembler does not have any cache, load-linked, or store-conditional instructions.
  599. </P>
  600. <P>
  601. Some assembler instructions are expanded into multiple instructions by the loader.
  602. For example the loader may convert the load of a 32 bit constant into an
  603. <TT>lui</TT>
  604. followed by an
  605. <TT>ori</TT>.
  606. </P>
  607. <P>
  608. Assembler instructions should be laid out as if there
  609. were no load, branch, or floating point compare delay slots;
  610. the loader will rearrange&#173;<I>schedule</I>&#173;the instructions
  611. to guarantee correctness and improve performance.
  612. The only exception is that the correct scheduling of instructions
  613. that use control registers varies from model to model of machine
  614. (and is often undocumented) so you should schedule such instructions
  615. by hand to guarantee correct behavior.
  616. The loader generates
  617. <DL><DT><DD><TT><PRE>
  618. NOR R0, R0, R0
  619. </PRE></TT></DL>
  620. when it needs a true no-op instruction.
  621. Use exactly this instruction when scheduling code manually;
  622. the loader recognizes it and schedules the code before it and after it independently. Also,
  623. <TT>WORD</TT>
  624. pseudo-ops are scheduled like no-ops.
  625. </P>
  626. <P>
  627. The
  628. <TT>NOSCHED</TT>
  629. pseudo-op disables instruction scheduling
  630. (scheduling is enabled by default);
  631. <TT>SCHED</TT>
  632. re-enables it.
  633. Branch folding, code copying, and dead code elimination are
  634. disabled for instructions that are not scheduled.
  635. </P>
  636. <H4>SPARC
  637. </H4>
  638. <P>
  639. Once you understand the Plan 9 model for the MIPS, the SPARC is familiar.
  640. Registers have numerical names only:
  641. <TT>R0</TT>
  642. through
  643. <TT>R31</TT>.
  644. Forget about register windows: Plan 9 doesn't use them at all.
  645. The machine has 32 global registers, period.
  646. <TT>R1</TT>
  647. [sic] is the stack pointer.
  648. <TT>R2</TT>
  649. is the static base register, with value the address of
  650. <TT>setSB(SB)</TT>.
  651. <TT>R7</TT>
  652. is the return register and also the register holding the first
  653. argument to a C (not Alef) function, again with space reserved at
  654. <TT>0(FP)</TT>.
  655. <TT>R14</TT>
  656. is the loader temporary.
  657. </P>
  658. <P>
  659. Floating-point registers are exactly as on the MIPS.
  660. </P>
  661. <P>
  662. The control registers are known by names such as
  663. <TT>FSR</TT>.
  664. The instructions to access these registers are
  665. <TT>MOVW</TT>
  666. instructions, for example
  667. <DL><DT><DD><TT><PRE>
  668. MOVW Y, R8
  669. </PRE></TT></DL>
  670. for the SPARC instruction
  671. <DL><DT><DD><TT><PRE>
  672. rdy %r8
  673. </PRE></TT></DL>
  674. </P>
  675. <P>
  676. Move instructions are similar to those on the MIPS: pseudo-operations
  677. that turn into appropriate sequences of
  678. <TT>sethi</TT>
  679. instructions, adds, etc.
  680. Instructions read from left to right. Because the arguments are
  681. flipped to
  682. <TT>SUBCC</TT>,
  683. the condition codes are not inverted as on the MIPS.
  684. </P>
  685. <P>
  686. The syntax for the ASI stuff is, for example to move a word from ASI 2:
  687. <DL><DT><DD><TT><PRE>
  688. MOVW (R7, 2), R8
  689. </PRE></TT></DL>
  690. The syntax for double indexing is
  691. <DL><DT><DD><TT><PRE>
  692. MOVW (R7+R8), R9
  693. </PRE></TT></DL>
  694. </P>
  695. <P>
  696. The SPARC's instruction scheduling is similar to the MIPS's.
  697. The official no-op instruction is:
  698. <DL><DT><DD><TT><PRE>
  699. ORN R0, R0, R0
  700. </PRE></TT></DL>
  701. </P>
  702. <H4>i960
  703. </H4>
  704. <P>
  705. Registers are numbered
  706. <TT>R0</TT>
  707. through
  708. <TT>R31</TT>.
  709. Stack pointer is
  710. <TT>R29</TT>;
  711. return register is
  712. <TT>R4</TT>;
  713. static base is
  714. <TT>R28</TT>;
  715. it is initialized to the address of
  716. <TT>setSB(SB)</TT>.
  717. <TT>R3</TT>
  718. must be zero; this should be done manually early in execution by
  719. <DL><DT><DD><TT><PRE>
  720. SUBO R3, R3
  721. </PRE></TT></DL>
  722. <TT>R27</TT>
  723. is the loader temporary.
  724. </P>
  725. <P>
  726. There is no support for floating point.
  727. </P>
  728. <P>
  729. The Intel calling convention is not supported and cannot be used; use
  730. <TT>BAL</TT>
  731. instead.
  732. Instructions are mostly as in the book. The major change is that
  733. <TT>LOAD</TT>
  734. and
  735. <TT>STORE</TT>
  736. are both called
  737. <TT>MOV</TT>.
  738. The extension character for
  739. <TT>MOV</TT>
  740. is as in the manual:
  741. <TT>O</TT>
  742. for ordinal,
  743. <TT>W</TT>
  744. for signed, etc.
  745. </P>
  746. <H4>i386
  747. </H4>
  748. <P>
  749. The assembler assumes 32-bit protected mode.
  750. The register names are
  751. <TT>SP</TT>,
  752. <TT>AX</TT>,
  753. <TT>BX</TT>,
  754. <TT>CX</TT>,
  755. <TT>DX</TT>,
  756. <TT>BP</TT>,
  757. <TT>DI</TT>,
  758. and
  759. <TT>SI</TT>.
  760. The stack pointer (not a pseudo-register) is
  761. <TT>SP</TT>
  762. and the return register is
  763. <TT>AX</TT>.
  764. There is no physical frame pointer but, as for the MIPS,
  765. <TT>FP</TT>
  766. is a pseudo-register that acts as
  767. a frame pointer.
  768. </P>
  769. <P>
  770. Opcode names are mostly the same as those listed in the Intel manual
  771. with an
  772. <TT>L</TT>,
  773. <TT>W</TT>,
  774. or
  775. <TT>B</TT>
  776. appended to identify 32-bit,
  777. 16-bit, and 8-bit operations.
  778. The exceptions are loads, stores, and conditionals.
  779. All load and store opcodes to and from general registers, special registers
  780. (such as
  781. <TT>CR0,</TT>
  782. <TT>CR3,</TT>
  783. <TT>GDTR,</TT>
  784. <TT>IDTR,</TT>
  785. <TT>SS,</TT>
  786. <TT>CS,</TT>
  787. <TT>DS,</TT>
  788. <TT>ES,</TT>
  789. <TT>FS,</TT>
  790. and
  791. <TT>GS</TT>)
  792. or memory are written
  793. as
  794. <DL><DT><DD><TT><PRE>
  795. MOV<I>x</I> src,dst
  796. </PRE></TT></DL>
  797. where
  798. <I>x</I>
  799. is
  800. <TT>L</TT>,
  801. <TT>W</TT>,
  802. or
  803. <TT>B</TT>.
  804. Thus to get
  805. <TT>AL</TT>
  806. use a
  807. <TT>MOVB</TT>
  808. instruction. If you need to access
  809. <TT>AH</TT>,
  810. you must mention it explicitly in a
  811. <TT>MOVB</TT>:
  812. <DL><DT><DD><TT><PRE>
  813. MOVB AH, BX
  814. </PRE></TT></DL>
  815. There are many examples of illegal moves, for example,
  816. <DL><DT><DD><TT><PRE>
  817. MOVB BP, DI
  818. </PRE></TT></DL>
  819. that the loader actually implements as pseudo-operations.
  820. </P>
  821. <P>
  822. The names of conditions in all conditional instructions
  823. (<TT>J</TT>,
  824. <TT>SET</TT>)
  825. follow the conventions of the 68020 instead of those of the Intel
  826. assembler:
  827. <TT>JOS</TT>,
  828. <TT>JOC</TT>,
  829. <TT>JCS</TT>,
  830. <TT>JCC</TT>,
  831. <TT>JEQ</TT>,
  832. <TT>JNE</TT>,
  833. <TT>JLS</TT>,
  834. <TT>JHI</TT>,
  835. <TT>JMI</TT>,
  836. <TT>JPL</TT>,
  837. <TT>JPS</TT>,
  838. <TT>JPC</TT>,
  839. <TT>JLT</TT>,
  840. <TT>JGE</TT>,
  841. <TT>JLE</TT>,
  842. and
  843. <TT>JGT</TT>
  844. instead of
  845. <TT>JO</TT>,
  846. <TT>JNO</TT>,
  847. <TT>JB</TT>,
  848. <TT>JNB</TT>,
  849. <TT>JZ</TT>,
  850. <TT>JNZ</TT>,
  851. <TT>JBE</TT>,
  852. <TT>JNBE</TT>,
  853. <TT>JS</TT>,
  854. <TT>JNS</TT>,
  855. <TT>JP</TT>,
  856. <TT>JNP</TT>,
  857. <TT>JL</TT>,
  858. <TT>JNL</TT>,
  859. <TT>JLE</TT>,
  860. and
  861. <TT>JNLE</TT>.
  862. </P>
  863. <P>
  864. The addressing modes have syntax like
  865. <TT>AX</TT>,
  866. <TT>(AX)</TT>,
  867. <TT>(AX)(BX*4)</TT>,
  868. <TT>10(AX)</TT>,
  869. and
  870. <TT>10(AX)(BX*4)</TT>.
  871. The offsets from
  872. <TT>AX</TT>
  873. can be replaced by offsets from
  874. <TT>FP</TT>
  875. or
  876. <TT>SB</TT>
  877. to access names, for example
  878. <TT>extern+5(SB)(AX*2)</TT>.
  879. </P>
  880. <P>
  881. Other notes: Non-relative
  882. <TT>JMP</TT>
  883. and
  884. <TT>CALL</TT>
  885. have a
  886. <TT>*</TT>
  887. added to the syntax.
  888. Only
  889. <TT>LOOP</TT>,
  890. <TT>LOOPEQ</TT>,
  891. and
  892. <TT>LOOPNE</TT>
  893. are legal loop instructions. Only
  894. <TT>REP</TT>
  895. and
  896. <TT>REPN</TT>
  897. are recognized repeaters. These are not prefixes, but rather
  898. stand-alone opcodes that precede the strings, for example
  899. <DL><DT><DD><TT><PRE>
  900. CLD; REP; MOVSL
  901. </PRE></TT></DL>
  902. Segment override prefixes in
  903. <TT>MOD/RM</TT>
  904. fields are not supported.
  905. </P>
  906. <H4>Alpha
  907. </H4>
  908. <P>
  909. On the Alpha, all registers are 64 bits. The architecture handles 32-bit values
  910. by giving them a canonical format (sign extension in the case of integer registers).
  911. Registers are numbered
  912. <TT>R0</TT>
  913. through
  914. <TT>R31</TT>.
  915. <TT>R0</TT>
  916. holds the return value from subroutines, and also the first parameter.
  917. <TT>R30</TT>
  918. is the stack pointer,
  919. <TT>R29</TT>
  920. is the static base,
  921. <TT>R26</TT>
  922. is the link register, and
  923. <TT>R27</TT>
  924. and
  925. <TT>R28</TT>
  926. are linker temporaries.
  927. </P>
  928. <P>
  929. Floating point registers are numbered
  930. <TT>F0</TT>
  931. to
  932. <TT>F31</TT>.
  933. <TT>F28</TT>
  934. contains
  935. <TT>0.5</TT>,
  936. <TT>F29</TT>
  937. contains
  938. <TT>1.0</TT>,
  939. and
  940. <TT>F30</TT>
  941. contains
  942. <TT>2.0</TT>.
  943. <TT>F31</TT>
  944. is always
  945. <TT>0.0</TT>
  946. on the Alpha.
  947. </P>
  948. <P>
  949. The extension character for
  950. <TT>MOV</TT>
  951. follows DEC's notation:
  952. <TT>B</TT>
  953. for byte (8 bits),
  954. <TT>W</TT>
  955. for word (16 bits),
  956. <TT>L</TT>
  957. for long (32 bits),
  958. and
  959. <TT>Q</TT>
  960. for quadword (64 bits).
  961. Byte and ``word'' loads and stores may be made unsigned
  962. by appending a
  963. <TT>U</TT>.
  964. <TT>S</TT>
  965. and
  966. <TT>T</TT>
  967. refer to IEEE floating point single precision (32 bits) and double precision (64 bits), respectively.
  968. </P>
  969. <H4>Power PC
  970. </H4>
  971. <P>
  972. The Power PC follows the Plan 9 model set by the MIPS and SPARC,
  973. not the elaborate ABIs.
  974. The 32-bit instructions of the 60x and 8xx PowerPC architectures are supported;
  975. there is no support for the older POWER instructions.
  976. Registers are
  977. <TT>R0</TT>
  978. through
  979. <TT>R31</TT>.
  980. <TT>R0</TT>
  981. is initialized to zero; this is done by C start up code
  982. and assumed by the compiler and loader.
  983. <TT>R1</TT>
  984. is the stack pointer.
  985. <TT>R2</TT>
  986. is the static base register, with value the address of
  987. <TT>setSB(SB)</TT>.
  988. <TT>R3</TT>
  989. is the return register and also the register holding the first
  990. argument to a C function, with space reserved at
  991. <TT>0(FP)</TT>
  992. as on the MIPS.
  993. <TT>R31</TT>
  994. is the loader temporary.
  995. The external registers in Plan 9's C are allocated from
  996. <TT>R30</TT>
  997. down.
  998. </P>
  999. <P>
  1000. Floating point registers are called
  1001. <TT>F0</TT>
  1002. through
  1003. <TT>F31</TT>.
  1004. By convention, several registers are initialized
  1005. to specific values; this is done by the operating system.
  1006. <TT>F27</TT>
  1007. must be initialized to the value
  1008. <TT>0x4330000080000000</TT>
  1009. (used by float-to-int conversion),
  1010. <TT>F28</TT>
  1011. to the value 0.0,
  1012. <TT>F29</TT>
  1013. to 0.5,
  1014. <TT>F30</TT>
  1015. to 1.0, and
  1016. <TT>F31</TT>
  1017. to 2.0.
  1018. </P>
  1019. <P>
  1020. As on the MIPS and SPARC, the assembler accepts arbitrary literals
  1021. as operands to
  1022. <TT>MOVW</TT>,
  1023. and also to
  1024. <TT>ADD</TT>
  1025. and others where `immediate' variants exist,
  1026. and the loader generates sequences
  1027. of
  1028. <TT>addi</TT>,
  1029. <TT>addis</TT>,
  1030. <TT>oris</TT>,
  1031. etc. as required.
  1032. The register indirect addressing modes use the same syntax as the SPARC,
  1033. including double indexing when allowed.
  1034. </P>
  1035. <P>
  1036. The instruction names are generally derived from the Motorola ones,
  1037. subject to slight transformation:
  1038. the
  1039. `<TT>.</TT>'
  1040. marking the setting of condition codes is replaced by
  1041. <TT>CC</TT>,
  1042. and when the letter
  1043. `<TT>o</TT>'
  1044. represents `OE=1' it is replaced by
  1045. <TT>V</TT>.
  1046. Thus
  1047. <TT>add</TT>,
  1048. <TT>addo.</TT>
  1049. and
  1050. <TT>subfzeo.</TT>
  1051. become
  1052. <TT>ADD</TT>,
  1053. <TT>ADDVCC</TT>
  1054. and
  1055. <TT>SUBFZEVCC</TT>.
  1056. As well as the three-operand conditional branch instruction
  1057. <TT>BC</TT>,
  1058. the assembler provides pseudo-instructions for the common cases:
  1059. <TT>BEQ</TT>,
  1060. <TT>BNE</TT>,
  1061. <TT>BGT</TT>,
  1062. <TT>BGE</TT>,
  1063. <TT>BLT</TT>,
  1064. <TT>BLE</TT>,
  1065. <TT>BVC</TT>,
  1066. and
  1067. <TT>BVS</TT>.
  1068. The unconditional branch instruction is
  1069. <TT>BR</TT>.
  1070. Indirect branches use
  1071. <TT>(CTR)</TT>
  1072. or
  1073. <TT>(LR)</TT>
  1074. as target.
  1075. </P>
  1076. <P>
  1077. Load or store operations are replaced by
  1078. <TT>MOV</TT>
  1079. variants in the usual way:
  1080. <TT>MOVW</TT>
  1081. (move word),
  1082. <TT>MOVH</TT>
  1083. (move halfword with sign extension), and
  1084. <TT>MOVB</TT>
  1085. (move byte with sign extension, a pseudo-instruction),
  1086. with unsigned variants
  1087. <TT>MOVHZ</TT>
  1088. and
  1089. <TT>MOVBZ</TT>,
  1090. and byte-reversing
  1091. <TT>MOVWBR</TT>
  1092. and
  1093. <TT>MOVHBR</TT>.
  1094. `Load or store with update' versions are
  1095. <TT>MOVWU</TT>,
  1096. <TT>MOVHU</TT>,
  1097. and
  1098. <TT>MOVBZU</TT>.
  1099. Load or store multiple is
  1100. <TT>MOVMW</TT>.
  1101. The exceptions are the string instructions, which are
  1102. <TT>LSW</TT>
  1103. and
  1104. <TT>STSW</TT>,
  1105. and the reservation instructions
  1106. <TT>lwarx</TT>
  1107. and
  1108. <TT>stwcx.</TT>,
  1109. which are
  1110. <TT>LWAR</TT>
  1111. and
  1112. <TT>STWCCC</TT>,
  1113. all with operands in the usual data-flow order.
  1114. Floating-point load or store instructions are
  1115. <TT>FMOVD</TT>,
  1116. <TT>FMOVDU</TT>,
  1117. <TT>FMOVS</TT>,
  1118. and
  1119. <TT>FMOVSU</TT>.
  1120. The register to register move instructions
  1121. <TT>fmr</TT>
  1122. and
  1123. <TT>fmr.</TT>
  1124. are written
  1125. <TT>FMOVD</TT>
  1126. and
  1127. <TT>FMOVDCC</TT>.
  1128. </P>
  1129. <P>
  1130. The assembler knows the commonly used special purpose registers:
  1131. <TT>CR</TT>,
  1132. <TT>CTR</TT>,
  1133. <TT>DEC</TT>,
  1134. <TT>LR</TT>,
  1135. <TT>MSR</TT>,
  1136. and
  1137. <TT>XER</TT>.
  1138. The rest, which are often architecture-dependent, are referenced as
  1139. <TT>SPR(n)</TT>.
  1140. The segment registers of the 60x series are similarly
  1141. <TT>SEG(n)</TT>,
  1142. but
  1143. <I>n</I>
  1144. can also be a register name, as in
  1145. <TT>SEG(R3)</TT>.
  1146. Moves between special purpose registers and general purpose ones,
  1147. when allowed by the architecture,
  1148. are written as
  1149. <TT>MOVW</TT>,
  1150. replacing
  1151. <TT>mfcr</TT>,
  1152. <TT>mtcr</TT>,
  1153. <TT>mfmsr</TT>,
  1154. <TT>mtmsr</TT>,
  1155. <TT>mtspr</TT>,
  1156. <TT>mfspr</TT>,
  1157. <TT>mftb</TT>,
  1158. and many others.
  1159. </P>
  1160. <P>
  1161. The fields of the condition register
  1162. <TT>CR</TT>
  1163. are referenced as
  1164. <TT>CR(0)</TT>
  1165. through
  1166. <TT>CR(7)</TT>.
  1167. They are used by the
  1168. <TT>MOVFL</TT>
  1169. (move field) pseudo-instruction,
  1170. which produces
  1171. <TT>mcrf</TT>
  1172. or
  1173. <TT>mtcrf</TT>.
  1174. For example:
  1175. <DL><DT><DD><TT><PRE>
  1176. MOVFL CR(3), CR(0)
  1177. MOVFL R3, CR(1)
  1178. MOVFL R3, $7, CR
  1179. </PRE></TT></DL>
  1180. They are also accepted in
  1181. the conditional branch instruction, for example
  1182. <DL><DT><DD><TT><PRE>
  1183. BEQ CR(7), label
  1184. </PRE></TT></DL>
  1185. Fields of the
  1186. <TT>FPSCR</TT>
  1187. are accessed using
  1188. <TT>MOVFL</TT>
  1189. in a similar way:
  1190. <DL><DT><DD><TT><PRE>
  1191. MOVFL FPSCR, F0
  1192. MOVFL F0, FPSCR
  1193. MOVFL F0, $7, FPSCR
  1194. MOVFL $0, FPSCR(3)
  1195. </PRE></TT></DL>
  1196. producing
  1197. <TT>mffs</TT>,
  1198. <TT>mtfsf</TT>
  1199. or
  1200. <TT>mtfsfi</TT>,
  1201. as appropriate.
  1202. </P>
  1203. <H4>ARM
  1204. </H4>
  1205. <P>
  1206. The assembler provides access to
  1207. <TT>R0</TT>
  1208. through
  1209. <TT>R14</TT>
  1210. and the
  1211. <TT>PC</TT>.
  1212. The stack pointer is
  1213. <TT>R13</TT>,
  1214. the link register is
  1215. <TT>R14</TT>,
  1216. and the static base register is
  1217. <TT>R12</TT>.
  1218. <TT>R0</TT>
  1219. is the return register and also the register holding
  1220. the first argument to a subroutine.
  1221. The assembler supports the
  1222. <TT>CPSR</TT>
  1223. and
  1224. <TT>SPSR</TT>
  1225. registers.
  1226. It also knows about coprocessor registers
  1227. <TT>C0</TT>
  1228. through
  1229. <TT>C15</TT>.
  1230. Floating registers are
  1231. <TT>F0</TT>
  1232. through
  1233. <TT>F7</TT>,
  1234. <TT>FPSR</TT>
  1235. and
  1236. <TT>FPCR</TT>.
  1237. </P>
  1238. <P>
  1239. As with the other architectures, loads and stores are called
  1240. <TT>MOV</TT>,
  1241. e.g.
  1242. <TT>MOVW</TT>
  1243. for load word or store word, and
  1244. <TT>MOVM</TT>
  1245. for
  1246. load or store multiple,
  1247. depending on the operands.
  1248. </P>
  1249. <P>
  1250. Addressing modes are supported by suffixes to the instructions:
  1251. <TT>.IA</TT>
  1252. (increment after),
  1253. <TT>.IB</TT>
  1254. (increment before),
  1255. <TT>.DA</TT>
  1256. (decrement after), and
  1257. <TT>.DB</TT>
  1258. (decrement before).
  1259. These can only be used with the
  1260. <TT>MOV</TT>
  1261. instructions.
  1262. The move multiple instruction,
  1263. <TT>MOVM</TT>,
  1264. defines a range of registers using brackets, e.g.
  1265. <TT>[R0-R12]</TT>.
  1266. The special
  1267. <TT>MOVM</TT>
  1268. addressing mode bits
  1269. <TT>W</TT>,
  1270. <TT>U</TT>,
  1271. and
  1272. <TT>P</TT>
  1273. are written in the same manner, for example,
  1274. <TT>MOVM.DB.W</TT>.
  1275. A
  1276. <TT>.S</TT>
  1277. suffix allows a
  1278. <TT>MOVM</TT>
  1279. instruction to access user
  1280. <TT>R13</TT>
  1281. and
  1282. <TT>R14</TT>
  1283. when in another processor mode.
  1284. Shifts and rotates in addressing modes are supported by binary operators
  1285. <TT><<</TT>
  1286. (logical left shift),
  1287. <TT>>></TT>
  1288. (logical right shift),
  1289. <TT>-></TT>
  1290. (arithmetic right shift), and
  1291. <TT>@></TT>
  1292. (rotate right); for example
  1293. <TT>R7>>R2</TT>or
  1294. <TT>R2@>2</TT>.
  1295. The assembler does not support indexing by a shifted expression;
  1296. only names can be doubly indexed.
  1297. </P>
  1298. <P>
  1299. Any instruction can be followed by a suffix that makes the instruction conditional:
  1300. <TT>.EQ</TT>,
  1301. <TT>.NE</TT>,
  1302. and so on, as in the ARM manual, with synonyms
  1303. <TT>.HS</TT>
  1304. (for
  1305. <TT>.CS</TT>)
  1306. and
  1307. <TT>.LO</TT>
  1308. (for
  1309. for<TT>.CC</TT>),
  1310. <TT>ADD.NE</TT>.
  1311. Arithmetic
  1312. and logical instructions
  1313. can have a
  1314. <TT>.S</TT>
  1315. suffix, as ARM allows, to set condition codes.
  1316. </P>
  1317. <P>
  1318. The syntax of the
  1319. <TT>MCR</TT>
  1320. and
  1321. <TT>MRC</TT>
  1322. coprocessor instructions is largely as in the manual, with the usual adjustments.
  1323. The assembler directly supports only the ARM floating-point coprocessor
  1324. operations used by the compiler:
  1325. <TT>CMP</TT>,
  1326. <TT>ADD</TT>,
  1327. <TT>SUB</TT>,
  1328. <TT>MUL</TT>,
  1329. and
  1330. <TT>DIV</TT>,
  1331. all with
  1332. <TT>F</TT>
  1333. or
  1334. <TT>D</TT>
  1335. suffix selecting single or double precision.
  1336. Floating-point load or store become
  1337. <TT>MOVF</TT>
  1338. and
  1339. <TT>MOVD</TT>.
  1340. Conversion instructions are also specified by moves:
  1341. <TT>MOVWD</TT>,
  1342. <TT>MOVWF</TT>,
  1343. <TT>MOVDW</TT>,
  1344. <TT>MOVWD</TT>,
  1345. <TT>MOVFD</TT>,
  1346. and
  1347. <TT>MOVDF</TT>.
  1348. </P>
  1349. <H4>AMD 29000
  1350. </H4>
  1351. <P>
  1352. For details about this assembly language, which was built for the AMD 29240,
  1353. look at the sources or examine compiler output.
  1354. </P>
  1355. <br>&#32;<br>
  1356. <A href=http://www.lucent.com/copyright.html>
  1357. Copyright</A> &#169; 2000 Lucent Technologies Inc. All rights reserved.
  1358. </body></html>