usbohci.c 53 KB

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  1. /*
  2. * USB Open Host Controller Interface (Ohci) driver
  3. *
  4. * BUGS:
  5. * - Missing isochronous input streams.
  6. * - Too many delays and ilocks.
  7. * - bandwidth admission control must be done per-frame.
  8. * - Buffering could be handled like in uhci, to avoid
  9. * needed block allocation and avoid allocs for small Tds.
  10. * - must warn of power overruns.
  11. */
  12. #include "u.h"
  13. #include "../port/lib.h"
  14. #include "mem.h"
  15. #include "dat.h"
  16. #include "fns.h"
  17. #include "io.h"
  18. #include "../port/error.h"
  19. #include "../port/usb.h"
  20. typedef struct Ctlio Ctlio;
  21. typedef struct Ctlr Ctlr;
  22. typedef struct Ed Ed;
  23. typedef struct Edpool Edpool;
  24. typedef struct Epx Epx;
  25. typedef struct Hcca Hcca;
  26. typedef struct Isoio Isoio;
  27. typedef struct Ohci Ohci;
  28. typedef struct Qio Qio;
  29. typedef struct Qtree Qtree;
  30. typedef struct Td Td;
  31. typedef struct Tdpool Tdpool;
  32. enum
  33. {
  34. Incr = 64, /* for Td and Ed pools */
  35. Align = 0x20, /* OHCI only requires 0x10 */
  36. /* use always a power of 2 */
  37. Abortdelay = 1, /* delay after cancelling Tds (ms) */
  38. Tdatomic = 8, /* max nb. of Tds per bulk I/O op. */
  39. Enabledelay = 100, /* waiting for a port to enable */
  40. /* Queue states (software) */
  41. Qidle = 0,
  42. Qinstall,
  43. Qrun,
  44. Qdone,
  45. Qclose,
  46. Qfree,
  47. /* Ed control bits */
  48. Edmpsmask = 0x7ff, /* max packet size */
  49. Edmpsshift = 16,
  50. Edlow = 1 << 13, /* low speed */
  51. Edskip = 1 << 14, /* skip this ed */
  52. Ediso = 1 << 15, /* iso Tds used */
  53. Edtddir = 0, /* get dir from td */
  54. Edin = 2 << 11, /* direction in */
  55. Edout = 1 << 11, /* direction out */
  56. Eddirmask = 3 << 11, /* direction bits */
  57. Edhalt = 1, /* halted (in head ptr) */
  58. Edtoggle = 2, /* toggle (in head ptr) 1 == data1 */
  59. /* Td control bits */
  60. Tdround = 1<<18, /* (rounding) short packets ok */
  61. Tdtoksetup = 0<<19, /* setup packet */
  62. Tdtokin = 2<<19, /* in packet */
  63. Tdtokout = 1<<19, /* out packet */
  64. Tdtokmask = 3<<19, /* in/out/setup bits */
  65. Tdnoioc = 7<<21, /* intr. cnt. value for no interrupt */
  66. Tdusetog = 1<<25, /* use toggle from Td (1) or Ed (0) */
  67. Tddata1 = 1<<24, /* data toggle (1 == data1) */
  68. Tddata0 = 0<<24,
  69. Tdfcmask = 7, /* frame count (iso) */
  70. Tdfcshift = 24,
  71. Tdsfmask = 0xFFFF, /* starting frame (iso) */
  72. Tderrmask = 3, /* error counter */
  73. Tderrshift = 26,
  74. Tdccmask = 0xf, /* condition code (status) */
  75. Tdccshift = 28,
  76. Tdiccmask = 0xf, /* condition code (iso, offsets) */
  77. Tdiccshift = 12,
  78. Ntdframes = 0x10000, /* # of different iso frame numbers */
  79. /* Td errors (condition code) */
  80. Tdok = 0,
  81. Tdcrc = 1,
  82. Tdbitstuff = 2,
  83. Tdbadtog = 3,
  84. Tdstalled = 4,
  85. Tdtmout = 5,
  86. Tdpidchk = 6,
  87. Tdbadpid = 7,
  88. Tddataovr = 8,
  89. Tddataund = 9,
  90. Tdbufovr = 0xC,
  91. Tdbufund = 0xD,
  92. Tdnotacc = 0xE,
  93. /* control register */
  94. Cple = 0x04, /* periodic list enable */
  95. Cie = 0x08, /* iso. list enable */
  96. Ccle = 0x10, /* ctl list enable */
  97. Cble = 0x20, /* bulk list enable */
  98. Cfsmask = 3 << 6, /* functional state... */
  99. Cfsreset = 0 << 6,
  100. Cfsresume = 1 << 6,
  101. Cfsoper = 2 << 6,
  102. Cfssuspend = 3 << 6,
  103. /* command status */
  104. Sblf = 1 << 2, /* bulk list (load) flag */
  105. Sclf = 1 << 1, /* control list (load) flag */
  106. Shcr = 1 << 0, /* host controller reset */
  107. /* intr enable */
  108. Mie = 1 << 31,
  109. Oc = 1 << 30,
  110. Rhsc = 1 << 6,
  111. Fno = 1 << 5,
  112. Ue = 1 << 4,
  113. Rd = 1 << 3,
  114. Sf = 1 << 2,
  115. Wdh = 1 << 1,
  116. So = 1 << 0,
  117. Fmaxpktmask = 0x7fff,
  118. Fmaxpktshift = 16,
  119. HcRhDescA_POTPGT_MASK = 0xff << 24,
  120. HcRhDescA_POTPGT_SHIFT = 24,
  121. /* Rh status */
  122. Lps = 1 << 0,
  123. Cgp = 1 << 0,
  124. Oci = 1 << 1,
  125. Psm = 1 << 8,
  126. Nps = 1 << 9,
  127. Drwe = 1 << 15,
  128. Srwe = 1 << 15,
  129. Lpsc = 1 << 16,
  130. Ccic = 1 << 17,
  131. Crwe = 1 << 31,
  132. /* port status */
  133. Ccs = 0x00001, /* current connect status */
  134. Pes = 0x00002, /* port enable status */
  135. Pss = 0x00004, /* port suspend status */
  136. Poci = 0x00008, /* over current indicator */
  137. Prs = 0x00010, /* port reset status */
  138. Pps = 0x00100, /* port power status */
  139. Lsda = 0x00200, /* low speed device attached */
  140. Csc = 0x10000, /* connect status change */
  141. Pesc = 0x20000, /* enable status change */
  142. Pssc = 0x40000, /* suspend status change */
  143. Ocic = 0x80000, /* over current ind. change */
  144. Prsc = 0x100000, /* reset status change */
  145. /* port status write bits */
  146. Cpe = 0x001, /* clear port enable */
  147. Spe = 0x002, /* set port enable */
  148. Spr = 0x010, /* set port reset */
  149. Spp = 0x100, /* set port power */
  150. Cpp = 0x200, /* clear port power */
  151. };
  152. /*
  153. * Endpoint descriptor. (first 4 words used by hardware)
  154. */
  155. struct Ed {
  156. ulong ctrl;
  157. ulong tail; /* transfer descriptor */
  158. ulong head;
  159. ulong nexted;
  160. Ed* next; /* sw; in free list or next in list */
  161. Td* tds; /* in use by current xfer; all for iso */
  162. Ep* ep; /* debug/align */
  163. Ed* inext; /* debug/align (dump interrupt eds). */
  164. };
  165. /*
  166. * Endpoint I/O state (software), per direction.
  167. */
  168. struct Qio
  169. {
  170. QLock; /* for the entire I/O process */
  171. Rendez; /* wait for completion */
  172. Ed* ed; /* to place Tds on it */
  173. int sched; /* queue number (intr/iso) */
  174. int toggle; /* Tddata0/Tddata1 */
  175. ulong usbid; /* device/endpoint address */
  176. int tok; /* Tdsetup, Tdtokin, Tdtokout */
  177. long iotime; /* last I/O time; to hold interrupt polls */
  178. int debug; /* for the endpoint */
  179. char* err; /* error status */
  180. int state; /* Qidle -> Qinstall -> Qrun -> Qdone | Qclose */
  181. long bw; /* load (intr/iso) */
  182. };
  183. struct Ctlio
  184. {
  185. Qio; /* single Ed for all transfers */
  186. uchar* data; /* read from last ctl req. */
  187. int ndata; /* number of bytes read */
  188. };
  189. struct Isoio
  190. {
  191. Qio;
  192. int nframes; /* number of frames for a full second */
  193. Td* atds; /* Tds avail for further I/O */
  194. int navail; /* number of avail Tds */
  195. ulong frno; /* next frame number avail for I/O */
  196. ulong left; /* remainder after rounding Hz to samples/ms */
  197. int nerrs; /* consecutive errors on iso I/O */
  198. };
  199. /*
  200. * Transfer descriptor. Size must be multiple of 32
  201. * First block is used by hardware (aligned to 32).
  202. */
  203. struct Td
  204. {
  205. ulong ctrl;
  206. ulong cbp; /* current buffer pointer */
  207. ulong nexttd;
  208. ulong be;
  209. ushort offsets[8]; /* used by Iso Tds only */
  210. Td* next; /* in free or Ed tds list */
  211. Td* anext; /* in avail td list (iso) */
  212. Ep* ep; /* using this Td for I/O */
  213. Qio* io; /* using this Td for I/O */
  214. Block* bp; /* data for this Td */
  215. ulong nbytes; /* bytes in this Td */
  216. ulong cbp0; /* initial value for cbp */
  217. ulong last; /* true for last Td in Qio */
  218. };
  219. /*
  220. * Host controller communication area (hardware)
  221. */
  222. struct Hcca
  223. {
  224. ulong intrtable[32];
  225. ushort framenumber;
  226. ushort pad1;
  227. ulong donehead;
  228. uchar reserved[116];
  229. };
  230. /*
  231. * I/O registers
  232. */
  233. struct Ohci
  234. {
  235. /* control and status group */
  236. ulong revision; /*00*/
  237. ulong control; /*04*/
  238. ulong cmdsts; /*08*/
  239. ulong intrsts; /*0c*/
  240. ulong intrenable; /*10*/
  241. ulong intrdisable; /*14*/
  242. /* memory pointer group */
  243. ulong hcca; /*18*/
  244. ulong periodcurred; /*1c*/
  245. ulong ctlheaded; /*20*/
  246. ulong ctlcurred; /*24*/
  247. ulong bulkheaded; /*28*/
  248. ulong bulkcurred; /*2c*/
  249. ulong donehead; /*30*/
  250. /* frame counter group */
  251. ulong fminterval; /*34*/
  252. ulong fmremaining; /*38*/
  253. ulong fmnumber; /*3c*/
  254. ulong periodicstart; /*40*/
  255. ulong lsthreshold; /*44*/
  256. /* root hub group */
  257. ulong rhdesca; /*48*/
  258. ulong rhdescb; /*4c*/
  259. ulong rhsts; /*50*/
  260. ulong rhportsts[15]; /*54*/
  261. ulong pad25[20]; /*90*/
  262. /* unknown */
  263. ulong hostueaddr; /*e0*/
  264. ulong hostuests; /*e4*/
  265. ulong hosttimeoutctrl; /*e8*/
  266. ulong pad59; /*ec*/
  267. ulong pad60; /*f0*/
  268. ulong hostrevision; /*f4*/
  269. ulong pad62[2];
  270. /*100*/
  271. };
  272. /*
  273. * Endpoint tree (software)
  274. */
  275. struct Qtree
  276. {
  277. int nel;
  278. int depth;
  279. ulong* bw;
  280. Ed** root;
  281. };
  282. struct Tdpool
  283. {
  284. Lock;
  285. Td* free;
  286. int nalloc;
  287. int ninuse;
  288. int nfree;
  289. };
  290. struct Edpool
  291. {
  292. Lock;
  293. Ed* free;
  294. int nalloc;
  295. int ninuse;
  296. int nfree;
  297. };
  298. struct Ctlr
  299. {
  300. Lock; /* for ilock; lists and basic ctlr I/O */
  301. QLock resetl; /* lock controller during USB reset */
  302. int active;
  303. Ctlr* next;
  304. int nports;
  305. Ohci* ohci; /* base I/O address */
  306. Hcca* hcca; /* intr/done Td lists (used by hardware) */
  307. int overrun; /* sched. overrun */
  308. Ed* intrhd; /* list of intr. eds in tree */
  309. Qtree* tree; /* tree for t Ep i/o */
  310. int ntree; /* number of dummy Eds in tree */
  311. Pcidev* pcidev;
  312. };
  313. #define dqprint if(debug || io && io->debug)print
  314. #define ddqprint if(debug>1 || (io && io->debug>1))print
  315. #define diprint if(debug || iso && iso->debug)print
  316. #define ddiprint if(debug>1 || (iso && iso->debug>1))print
  317. #define TRUNC(x, sz) ((x) & ((sz)-1))
  318. static int ohciinterrupts[Nttypes];
  319. static char* iosname[] = { "idle", "install", "run", "done", "close", "FREE" };
  320. static int debug;
  321. static Edpool edpool;
  322. static Tdpool tdpool;
  323. static Ctlr* ctlrs[Nhcis];
  324. static char EnotWritten[] = "usb write unfinished";
  325. static char EnotRead[] = "usb read unfinished";
  326. static char Eunderrun[] = "usb endpoint underrun";
  327. static QLock usbhstate; /* protects name space state */
  328. static int schedendpt(Ctlr *ub, Ep *ep);
  329. static void unschedendpt(Ctlr *ub, Ep *ep);
  330. static long qtd(Ctlr*, Ep*, int, Block*, uchar*, uchar*, int, ulong);
  331. static char* errmsgs[] =
  332. {
  333. [Tdcrc] "crc error",
  334. [Tdbitstuff] "bit stuffing error",
  335. [Tdbadtog] "bad toggle",
  336. [Tdstalled] Estalled,
  337. [Tdtmout] "timeout error",
  338. [Tdpidchk] "pid check error",
  339. [Tdbadpid] "bad pid",
  340. [Tddataovr] "data overrun",
  341. [Tddataund] "data underrun",
  342. [Tdbufovr] "buffer overrun",
  343. [Tdbufund] "buffer underrun",
  344. [Tdnotacc] "not accessed"
  345. };
  346. static void*
  347. pa2ptr(ulong pa)
  348. {
  349. if(pa == 0)
  350. return nil;
  351. else
  352. return KADDR(pa);
  353. }
  354. static ulong
  355. ptr2pa(void *p)
  356. {
  357. if(p == nil)
  358. return 0;
  359. else
  360. return PADDR(p);
  361. }
  362. static void
  363. waitSOF(Ctlr *ub)
  364. {
  365. int frame = ub->hcca->framenumber & 0x3f;
  366. do {
  367. delay(2);
  368. } while(frame == (ub->hcca->framenumber & 0x3f));
  369. }
  370. static char*
  371. errmsg(int err)
  372. {
  373. if(err < nelem(errmsgs))
  374. return errmsgs[err];
  375. return nil;
  376. }
  377. static Ed*
  378. ctlhd(Ctlr *ctlr)
  379. {
  380. return pa2ptr(ctlr->ohci->ctlheaded);
  381. }
  382. static Ed*
  383. bulkhd(Ctlr *ctlr)
  384. {
  385. return pa2ptr(ctlr->ohci->bulkheaded);
  386. }
  387. static void
  388. edlinked(Ed *ed, Ed *next)
  389. {
  390. if(ed == nil)
  391. print("edlinked: nil ed: pc %#p\n", getcallerpc(&ed));
  392. ed->nexted = ptr2pa(next);
  393. ed->next = next;
  394. }
  395. static void
  396. setctlhd(Ctlr *ctlr, Ed *ed)
  397. {
  398. ctlr->ohci->ctlheaded = ptr2pa(ed);
  399. if(ed != nil)
  400. ctlr->ohci->cmdsts |= Sclf; /* reload it on next pass */
  401. }
  402. static void
  403. setbulkhd(Ctlr *ctlr, Ed *ed)
  404. {
  405. ctlr->ohci->bulkheaded = ptr2pa(ed);
  406. if(ed != nil)
  407. ctlr->ohci->cmdsts |= Sblf; /* reload it on next pass */
  408. }
  409. static void
  410. unlinkctl(Ctlr *ctlr, Ed *ed)
  411. {
  412. Ed *this, *prev, *next;
  413. ctlr->ohci->control &= ~Ccle;
  414. waitSOF(ctlr);
  415. this = ctlhd(ctlr);
  416. ctlr->ohci->ctlcurred = 0;
  417. prev = nil;
  418. while(this != nil && this != ed){
  419. prev = this;
  420. this = this->next;
  421. }
  422. if(this == nil){
  423. print("unlinkctl: not found\n");
  424. return;
  425. }
  426. next = this->next;
  427. if(prev == nil)
  428. setctlhd(ctlr, next);
  429. else
  430. edlinked(prev, next);
  431. ctlr->ohci->control |= Ccle;
  432. edlinked(ed, nil); /* wipe out next field */
  433. }
  434. static void
  435. unlinkbulk(Ctlr *ctlr, Ed *ed)
  436. {
  437. Ed *this, *prev, *next;
  438. ctlr->ohci->control &= ~Cble;
  439. waitSOF(ctlr);
  440. this = bulkhd(ctlr);
  441. ctlr->ohci->bulkcurred = 0;
  442. prev = nil;
  443. while(this != nil && this != ed){
  444. prev = this;
  445. this = this->next;
  446. }
  447. if(this == nil){
  448. print("unlinkbulk: not found\n");
  449. return;
  450. }
  451. next = this->next;
  452. if(prev == nil)
  453. setbulkhd(ctlr, next);
  454. else
  455. edlinked(prev, next);
  456. ctlr->ohci->control |= Cble;
  457. edlinked(ed, nil); /* wipe out next field */
  458. }
  459. static void
  460. edsetaddr(Ed *ed, ulong addr)
  461. {
  462. ulong ctrl;
  463. ctrl = ed->ctrl & ~((Epmax<<7)|Devmax);
  464. ctrl |= (addr & ((Epmax<<7)|Devmax));
  465. ed->ctrl = ctrl;
  466. }
  467. static void
  468. edsettog(Ed *ed, int c)
  469. {
  470. if(c != 0)
  471. ed->head |= Edtoggle;
  472. else
  473. ed->head &= ~Edtoggle;
  474. }
  475. static int
  476. edtoggle(Ed *ed)
  477. {
  478. return ed->head & Edtoggle;
  479. }
  480. static int
  481. edhalted(Ed *ed)
  482. {
  483. return ed->head & Edhalt;
  484. }
  485. static int
  486. edmaxpkt(Ed *ed)
  487. {
  488. return (ed->ctrl >> Edmpsshift) & Edmpsmask;
  489. }
  490. static void
  491. edsetmaxpkt(Ed *ed, int m)
  492. {
  493. ulong c;
  494. c = ed->ctrl & ~(Edmpsmask << Edmpsshift);
  495. ed->ctrl = c | ((m&Edmpsmask) << Edmpsshift);
  496. }
  497. static int
  498. tderrs(Td *td)
  499. {
  500. return (td->ctrl >> Tdccshift) & Tdccmask;
  501. }
  502. static int
  503. tdtok(Td *td)
  504. {
  505. return (td->ctrl & Tdtokmask);
  506. }
  507. static Td*
  508. tdalloc(void)
  509. {
  510. Td *td;
  511. Td *pool;
  512. int i;
  513. lock(&tdpool);
  514. if(tdpool.free == nil){
  515. ddprint("ohci: tdalloc %d Tds\n", Incr);
  516. pool = xspanalloc(Incr*sizeof(Td), Align, 0);
  517. if(pool == nil)
  518. panic("tdalloc");
  519. for(i=Incr; --i>=0;){
  520. pool[i].next = tdpool.free;
  521. tdpool.free = &pool[i];
  522. }
  523. tdpool.nalloc += Incr;
  524. tdpool.nfree += Incr;
  525. }
  526. tdpool.ninuse++;
  527. tdpool.nfree--;
  528. td = tdpool.free;
  529. tdpool.free = td->next;
  530. memset(td, 0, sizeof(Td));
  531. unlock(&tdpool);
  532. assert(((uintptr)td & 0xF) == 0);
  533. return td;
  534. }
  535. static void
  536. tdfree(Td *td)
  537. {
  538. if(td == 0)
  539. return;
  540. freeb(td->bp);
  541. td->bp = nil;
  542. lock(&tdpool);
  543. if(td->nexttd == 0x77777777)
  544. panic("ohci: tdfree: double free");
  545. memset(td, 7, sizeof(Td)); /* poison */
  546. td->next = tdpool.free;
  547. tdpool.free = td;
  548. tdpool.ninuse--;
  549. tdpool.nfree++;
  550. unlock(&tdpool);
  551. }
  552. static Ed*
  553. edalloc(void)
  554. {
  555. Ed *ed, *pool;
  556. int i;
  557. lock(&edpool);
  558. if(edpool.free == nil){
  559. ddprint("ohci: edalloc %d Eds\n", Incr);
  560. pool = xspanalloc(Incr*sizeof(Ed), Align, 0);
  561. if(pool == nil)
  562. panic("edalloc");
  563. for(i=Incr; --i>=0;){
  564. pool[i].next = edpool.free;
  565. edpool.free = &pool[i];
  566. }
  567. edpool.nalloc += Incr;
  568. edpool.nfree += Incr;
  569. }
  570. edpool.ninuse++;
  571. edpool.nfree--;
  572. ed = edpool.free;
  573. edpool.free = ed->next;
  574. memset(ed, 0, sizeof(Ed));
  575. unlock(&edpool);
  576. return ed;
  577. }
  578. static void
  579. edfree(Ed *ed)
  580. {
  581. Td *td, *next;
  582. int i;
  583. if(ed == 0)
  584. return;
  585. i = 0;
  586. for(td = ed->tds; td != nil; td = next){
  587. next = td->next;
  588. tdfree(td);
  589. if(i++ > 2000){
  590. print("ohci: bug: ed with more than 2000 tds\n");
  591. break;
  592. }
  593. }
  594. lock(&edpool);
  595. if(ed->nexted == 0x99999999)
  596. panic("ohci: edfree: double free");
  597. memset(ed, 9, sizeof(Ed)); /* poison */
  598. ed->next = edpool.free;
  599. edpool.free = ed;
  600. edpool.ninuse--;
  601. edpool.nfree++;
  602. unlock(&edpool);
  603. ddprint("edfree: ed %#p\n", ed);
  604. }
  605. /*
  606. * return smallest power of 2 >= n
  607. */
  608. static int
  609. flog2(int n)
  610. {
  611. int i;
  612. for(i = 0; (1 << i) < n; i++)
  613. ;
  614. return i;
  615. }
  616. /*
  617. * return smallest power of 2 <= n
  618. */
  619. static int
  620. flog2lower(int n)
  621. {
  622. int i;
  623. for(i = 0; (1 << (i + 1)) <= n; i++)
  624. ;
  625. return i;
  626. }
  627. static int
  628. pickschedq(Qtree *qt, int pollival, ulong bw, ulong limit)
  629. {
  630. int i, j, d, upperb, q;
  631. ulong best, worst, total;
  632. d = flog2lower(pollival);
  633. if(d > qt->depth)
  634. d = qt->depth;
  635. q = -1;
  636. worst = 0;
  637. best = ~0;
  638. upperb = (1 << (d+1)) - 1;
  639. for(i = (1 << d) - 1; i < upperb; i++){
  640. total = qt->bw[0];
  641. for(j = i; j > 0; j = (j - 1) / 2)
  642. total += qt->bw[j];
  643. if(total < best){
  644. best = total;
  645. q = i;
  646. }
  647. if(total > worst)
  648. worst = total;
  649. }
  650. if(worst + bw >= limit)
  651. return -1;
  652. return q;
  653. }
  654. static int
  655. schedq(Ctlr *ctlr, Qio *io, int pollival)
  656. {
  657. int q;
  658. Ed *ted;
  659. q = pickschedq(ctlr->tree, pollival, io->bw, ~0);
  660. ddqprint("ohci: sched %#p q %d, ival %d, bw %ld\n", io, q, pollival, io->bw);
  661. if(q < 0){
  662. print("ohci: no room for ed\n");
  663. return -1;
  664. }
  665. ctlr->tree->bw[q] += io->bw;
  666. ted = ctlr->tree->root[q];
  667. io->sched = q;
  668. edlinked(io->ed, ted->next);
  669. edlinked(ted, io->ed);
  670. io->ed->inext = ctlr->intrhd;
  671. ctlr->intrhd = io->ed;
  672. return 0;
  673. }
  674. static void
  675. unschedq(Ctlr *ctlr, Qio *qio)
  676. {
  677. int q;
  678. Ed *prev, *this, *next;
  679. Ed **l;
  680. q = qio->sched;
  681. if(q < 0)
  682. return;
  683. ctlr->tree->bw[q] -= qio->bw;
  684. prev = ctlr->tree->root[q];
  685. this = prev->next;
  686. while(this != nil && this != qio->ed){
  687. prev = this;
  688. this = this->next;
  689. }
  690. if(this == nil)
  691. print("ohci: unschedq %d: not found\n", q);
  692. else{
  693. next = this->next;
  694. edlinked(prev, next);
  695. }
  696. waitSOF(ctlr);
  697. for(l = &ctlr->intrhd; *l != nil; l = &(*l)->inext)
  698. if(*l == qio->ed){
  699. *l = (*l)->inext;
  700. return;
  701. }
  702. print("ohci: unschedq: ed %#p not found\n", qio->ed);
  703. }
  704. static char*
  705. seprinttdtok(char *s, char *e, int tok)
  706. {
  707. switch(tok){
  708. case Tdtoksetup:
  709. s = seprint(s, e, " setup");
  710. break;
  711. case Tdtokin:
  712. s = seprint(s, e, " in");
  713. break;
  714. case Tdtokout:
  715. s = seprint(s, e, " out");
  716. break;
  717. }
  718. return s;
  719. }
  720. static char*
  721. seprinttd(char *s, char *e, Td *td, int iso)
  722. {
  723. int i;
  724. Block *bp;
  725. if(td == nil)
  726. return seprint(s, e, "<nil td>\n");
  727. s = seprint(s, e, "%#p ep %#p ctrl %#p", td, td->ep, td->ctrl);
  728. s = seprint(s, e, " cc=%#ulx", (td->ctrl >> Tdccshift) & Tdccmask);
  729. if(iso == 0){
  730. if((td->ctrl & Tdround) != 0)
  731. s = seprint(s, e, " rnd");
  732. s = seprinttdtok(s, e, td->ctrl & Tdtokmask);
  733. if((td->ctrl & Tdusetog) != 0)
  734. s = seprint(s, e, " d%d", (td->ctrl & Tddata1) ? 1 : 0);
  735. else
  736. s = seprint(s, e, " d-");
  737. s = seprint(s, e, " ec=%uld", (td->ctrl >> Tderrshift) & Tderrmask);
  738. }else{
  739. s = seprint(s, e, " fc=%uld", (td->ctrl >> Tdfcshift) & Tdfcmask);
  740. s = seprint(s, e, " sf=%uld", td->ctrl & Tdsfmask);
  741. }
  742. s = seprint(s, e, " cbp0 %#p cbp %#p next %#p be %#p %s",
  743. td->cbp0, td->cbp, td->nexttd, td->be, td->last ? "last" : "");
  744. s = seprint(s, e, "\n\t\t%ld bytes", td->nbytes);
  745. if((bp = td->bp) != nil){
  746. s = seprint(s, e, " rp %#p wp %#p ", bp->rp, bp->wp);
  747. if(BLEN(bp) > 0)
  748. s = seprintdata(s, e, bp->rp, bp->wp - bp->rp);
  749. }
  750. if(iso == 0)
  751. return seprint(s, e, "\n");
  752. s = seprint(s, e, "\n\t\t");
  753. /* we use only offsets[0] */
  754. i = 0;
  755. s = seprint(s, e, "[%d] %#ux cc=%#ux sz=%ud\n", i, td->offsets[i],
  756. (td->offsets[i] >> Tdiccshift) & Tdiccmask,
  757. td->offsets[i] & 0x7FF);
  758. return s;
  759. }
  760. static void
  761. dumptd(Td *td, char *p, int iso)
  762. {
  763. static char buf[512]; /* Too much */
  764. char *s;
  765. s = seprint(buf, buf+sizeof(buf), "%s: ", p);
  766. s = seprinttd(s, buf+sizeof(buf), td, iso);
  767. if(s > buf && s[-1] != '\n')
  768. s[-1] = '\n';
  769. print("\t%s", buf);
  770. }
  771. static void
  772. dumptds(Td *td, char *p, int iso)
  773. {
  774. int i;
  775. for(i = 0; td != nil; td = td->next){
  776. dumptd(td, p, iso);
  777. if(td->last)
  778. break;
  779. if(tdtok(td) == Tdtokin && ++i > 2){
  780. print("\t\t...\n");
  781. break;
  782. }
  783. }
  784. }
  785. static void
  786. dumped(Ed *ed)
  787. {
  788. char *buf, *s, *e;
  789. if(ed == nil){
  790. print("<null ed>\n");
  791. return;
  792. }
  793. buf = malloc(512);
  794. /* no waserror; may want to use from interrupt context */
  795. if(buf == nil)
  796. return;
  797. e = buf+512;
  798. s = seprint(buf, e, "\ted %#p: ctrl %#p", ed, ed->ctrl);
  799. if((ed->ctrl & Edskip) != 0)
  800. s = seprint(s, e, " skip");
  801. if((ed->ctrl & Ediso) != 0)
  802. s = seprint(s, e, " iso");
  803. if((ed->ctrl & Edlow) != 0)
  804. s = seprint(s, e, " low");
  805. s = seprint(s, e, " d%d", (ed->head & Edtoggle) ? 1 : 0);
  806. if((ed->ctrl & Eddirmask) == Edin)
  807. s = seprint(s, e, " in");
  808. if((ed->ctrl & Eddirmask) == Edout)
  809. s = seprint(s, e, " out");
  810. if(edhalted(ed))
  811. s = seprint(s, e, " hlt");
  812. s = seprint(s, e, " ep%uld.%uld", (ed->ctrl>>7)&Epmax, ed->ctrl&0x7f);
  813. s = seprint(s, e, " maxpkt %uld", (ed->ctrl>>Edmpsshift)&Edmpsmask);
  814. seprint(s, e, " tail %#p head %#p next %#p\n",ed->tail,ed->head,ed->nexted);
  815. print("%s", buf);
  816. free(buf);
  817. if(ed->tds != nil && (ed->ctrl & Ediso) == 0)
  818. dumptds(ed->tds, "td", 0);
  819. }
  820. static char*
  821. seprintio(char *s, char *e, Qio *io, char *pref)
  822. {
  823. s = seprint(s, e, "%s qio %#p ed %#p", pref, io, io->ed);
  824. s = seprint(s, e, " tog %d iot %ld err %s id %#ulx",
  825. io->toggle, io->iotime, io->err, io->usbid);
  826. s = seprinttdtok(s, e, io->tok);
  827. s = seprint(s, e, " %s\n", iosname[io->state]);
  828. return s;
  829. }
  830. static char*
  831. seprintep(char* s, char* e, Ep *ep)
  832. {
  833. Isoio *iso;
  834. Qio *io;
  835. Ctlio *cio;
  836. if(ep == nil)
  837. return seprint(s, e, "<nil ep>\n");
  838. if(ep->aux == nil)
  839. return seprint(s, e, "no mdep\n");
  840. switch(ep->ttype){
  841. case Tctl:
  842. cio = ep->aux;
  843. s = seprintio(s, e, cio, "c");
  844. s = seprint(s, e, "\trepl %d ndata %d\n", ep->rhrepl, cio->ndata);
  845. break;
  846. case Tbulk:
  847. case Tintr:
  848. io = ep->aux;
  849. if(ep->mode != OWRITE)
  850. s = seprintio(s, e, &io[OREAD], "r");
  851. if(ep->mode != OREAD)
  852. s = seprintio(s, e, &io[OWRITE], "w");
  853. break;
  854. case Tiso:
  855. iso = ep->aux;
  856. s = seprintio(s, e, iso, "w");
  857. s = seprint(s, e, "\tntds %d avail %d frno %uld left %uld next avail %#p\n",
  858. iso->nframes, iso->navail, iso->frno, iso->left, iso->atds);
  859. break;
  860. }
  861. return s;
  862. }
  863. static char*
  864. seprintctl(char *s, char *se, ulong ctl)
  865. {
  866. s = seprint(s, se, "en=");
  867. if((ctl&Cple) != 0)
  868. s = seprint(s, se, "p");
  869. if((ctl&Cie) != 0)
  870. s = seprint(s, se, "i");
  871. if((ctl&Ccle) != 0)
  872. s = seprint(s, se, "c");
  873. if((ctl&Cble) != 0)
  874. s = seprint(s, se, "b");
  875. switch(ctl & Cfsmask){
  876. case Cfsreset:
  877. return seprint(s, se, " reset");
  878. case Cfsresume:
  879. return seprint(s, se, " resume");
  880. case Cfsoper:
  881. return seprint(s, se, " run");
  882. case Cfssuspend:
  883. return seprint(s, se, " suspend");
  884. default:
  885. return seprint(s, se, " ???");
  886. }
  887. }
  888. static void
  889. dump(Hci *hp)
  890. {
  891. Ctlr *ctlr;
  892. Ed *ed;
  893. char cs[20];
  894. ctlr = hp->aux;
  895. ilock(ctlr);
  896. seprintctl(cs, cs+sizeof(cs), ctlr->ohci->control);
  897. print("ohci ctlr %#p: frno %#ux ctl %#lux %s sts %#lux intr %#lux\n",
  898. ctlr, ctlr->hcca->framenumber, ctlr->ohci->control, cs,
  899. ctlr->ohci->cmdsts, ctlr->ohci->intrsts);
  900. print("ctlhd %#ulx cur %#ulx bulkhd %#ulx cur %#ulx done %#ulx\n",
  901. ctlr->ohci->ctlheaded, ctlr->ohci->ctlcurred,
  902. ctlr->ohci->bulkheaded, ctlr->ohci->bulkcurred,
  903. ctlr->ohci->donehead);
  904. if(ctlhd(ctlr) != nil)
  905. print("[ctl]\n");
  906. for(ed = ctlhd(ctlr); ed != nil; ed = ed->next)
  907. dumped(ed);
  908. if(bulkhd(ctlr) != nil)
  909. print("[bulk]\n");
  910. for(ed = bulkhd(ctlr); ed != nil; ed = ed->next)
  911. dumped(ed);
  912. if(ctlr->intrhd != nil)
  913. print("[intr]\n");
  914. for(ed = ctlr->intrhd; ed != nil; ed = ed->inext)
  915. dumped(ed);
  916. if(ctlr->tree->root[0]->next != nil)
  917. print("[iso]");
  918. for(ed = ctlr->tree->root[0]->next; ed != nil; ed = ed->next)
  919. dumped(ed);
  920. print("%d eds in tree\n", ctlr->ntree);
  921. iunlock(ctlr);
  922. lock(&tdpool);
  923. print("%d tds allocated = %d in use + %d free\n",
  924. tdpool.nalloc, tdpool.ninuse, tdpool.nfree);
  925. unlock(&tdpool);
  926. lock(&edpool);
  927. print("%d eds allocated = %d in use + %d free\n",
  928. edpool.nalloc, edpool.ninuse, edpool.nfree);
  929. unlock(&edpool);
  930. }
  931. /*
  932. * Compute size for the next iso Td and setup its
  933. * descriptor for I/O according to the buffer size.
  934. */
  935. static void
  936. isodtdinit(Ep *ep, Isoio *iso, Td *td)
  937. {
  938. Block *bp;
  939. long size;
  940. int i;
  941. bp = td->bp;
  942. assert(bp != nil && BLEN(bp) == 0);
  943. size = (ep->hz+iso->left) * ep->pollival / 1000;
  944. iso->left = (ep->hz+iso->left) * ep->pollival % 1000;
  945. size *= ep->samplesz;
  946. if(size > ep->maxpkt){
  947. print("ohci: ep%d.%d: size > maxpkt\n",
  948. ep->dev->nb, ep->nb);
  949. print("size = %uld max = %ld\n", size, ep->maxpkt);
  950. size = ep->maxpkt;
  951. }
  952. td->nbytes = size;
  953. memset(bp->wp, 0, size); /* in case we don't fill it on time */
  954. td->cbp0 = td->cbp = ptr2pa(bp->rp) & ~0xFFF;
  955. td->ctrl = TRUNC(iso->frno, Ntdframes);
  956. td->offsets[0] = (ptr2pa(bp->rp) & 0xFFF);
  957. td->offsets[0] |= (Tdnotacc << Tdiccshift);
  958. /* in case the controller checks out the offests... */
  959. for(i = 1; i < nelem(td->offsets); i++)
  960. td->offsets[i] = td->offsets[0];
  961. td->be = ptr2pa(bp->rp + size - 1);
  962. td->ctrl |= (0 << Tdfcshift); /* frame count is 1 */
  963. iso->frno = TRUNC(iso->frno + ep->pollival, Ntdframes);
  964. }
  965. /*
  966. * start I/O on the dummy td and setup a new dummy to fill up.
  967. */
  968. static void
  969. isoadvance(Ep *ep, Isoio *iso, Td *td)
  970. {
  971. Td *dtd;
  972. dtd = iso->atds;
  973. iso->atds = dtd->anext;
  974. iso->navail--;
  975. dtd->anext = nil;
  976. dtd->bp->wp = dtd->bp->rp;
  977. dtd->nexttd = 0;
  978. td->nexttd = ptr2pa(dtd);
  979. isodtdinit(ep, iso, dtd);
  980. iso->ed->tail = ptr2pa(dtd);
  981. }
  982. static int
  983. isocanwrite(void *a)
  984. {
  985. Isoio *iso;
  986. iso = a;
  987. return iso->state == Qclose || iso->err != nil ||
  988. iso->navail > iso->nframes / 2;
  989. }
  990. /*
  991. * Service a completed/failed Td from the done queue.
  992. * It may be of any transfer type.
  993. * The queue is not in completion order.
  994. * (It's actually in reverse completion order).
  995. *
  996. * When an error, a short packet, or a last Td is found
  997. * we awake the process waiting for the transfer.
  998. * Although later we will process other Tds completed
  999. * before, epio won't be able to touch the current Td
  1000. * until interrupt returns and releases the lock on the
  1001. * controller.
  1002. */
  1003. static void
  1004. qhinterrupt(Ctlr *, Ep *ep, Qio *io, Td *td, int)
  1005. {
  1006. Block *bp;
  1007. int mode, err;
  1008. Ed *ed;
  1009. ed = io->ed;
  1010. if(io->state != Qrun)
  1011. return;
  1012. if(tdtok(td) == Tdtokin)
  1013. mode = OREAD;
  1014. else
  1015. mode = OWRITE;
  1016. bp = td->bp;
  1017. err = tderrs(td);
  1018. switch(err){
  1019. case Tddataovr: /* Overrun is not an error */
  1020. break;
  1021. case Tdok:
  1022. /* virtualbox doesn't always report underflow on short packets */
  1023. if(td->cbp == 0)
  1024. break;
  1025. /* fall through */
  1026. case Tddataund:
  1027. /* short input packets are ok */
  1028. if(mode == OREAD){
  1029. if(td->cbp == 0)
  1030. panic("ohci: short packet but cbp == 0");
  1031. /*
  1032. * td->cbp and td->cbp0 are the real addresses
  1033. * corresponding to virtual addresses bp->wp and
  1034. * bp->rp respectively.
  1035. */
  1036. bp->wp = bp->rp + (td->cbp - td->cbp0);
  1037. if(bp->wp < bp->rp)
  1038. panic("ohci: wp < rp");
  1039. /*
  1040. * It's ok. clear error and flag as last in xfer.
  1041. * epio must ignore following Tds.
  1042. */
  1043. td->last = 1;
  1044. td->ctrl &= ~(Tdccmask << Tdccshift);
  1045. break;
  1046. }
  1047. /* else fall; it's an error */
  1048. case Tdcrc:
  1049. case Tdbitstuff:
  1050. case Tdbadtog:
  1051. case Tdstalled:
  1052. case Tdtmout:
  1053. case Tdpidchk:
  1054. case Tdbadpid:
  1055. bp->wp = bp->rp; /* no bytes in xfer. */
  1056. io->err = errmsg(err);
  1057. if(debug || ep->debug){
  1058. print("tdinterrupt: failed err %d (%s)\n", err, io->err);
  1059. dumptd(td, "failed", ed->ctrl & Ediso);
  1060. }
  1061. td->last = 1;
  1062. break;
  1063. default:
  1064. panic("ohci: td cc %ud unknown", err);
  1065. }
  1066. if(td->last != 0){
  1067. /*
  1068. * clear td list and halt flag.
  1069. */
  1070. ed->head = (ed->head & Edtoggle) | ed->tail;
  1071. ed->tds = pa2ptr(ed->tail);
  1072. io->state = Qdone;
  1073. wakeup(io);
  1074. }
  1075. }
  1076. /*
  1077. * BUG: Iso input streams are not implemented.
  1078. */
  1079. static void
  1080. isointerrupt(Ctlr *ctlr, Ep *ep, Qio *io, Td *td, int)
  1081. {
  1082. Isoio *iso;
  1083. Block *bp;
  1084. Ed *ed;
  1085. int err, isoerr;
  1086. iso = ep->aux;
  1087. ed = io->ed;
  1088. if(io->state == Qclose)
  1089. return;
  1090. bp = td->bp;
  1091. /*
  1092. * When we get more than half the frames consecutive errors
  1093. * we signal an actual error. Errors in the entire Td are
  1094. * more serious and are always singaled.
  1095. * Errors like overrun are not really errors. In fact, for
  1096. * output, errors cannot be really detected. The driver will
  1097. * hopefully notice I/O errors on input endpoints and detach the device.
  1098. */
  1099. err = tderrs(td);
  1100. isoerr = (td->offsets[0] >> Tdiccshift) & Tdiccmask;
  1101. if(isoerr == Tdok || isoerr == Tdnotacc)
  1102. iso->nerrs = 0;
  1103. else if(iso->nerrs++ > iso->nframes/2)
  1104. err = Tdstalled;
  1105. if(err != Tdok && err != Tddataovr){
  1106. bp->wp = bp->rp;
  1107. io->err = errmsg(err);
  1108. if(debug || ep->debug){
  1109. print("ohci: isointerrupt: ep%d.%d: err %d (%s) frnum 0x%lux\n",
  1110. ep->dev->nb, ep->nb,
  1111. err, errmsg(err), ctlr->ohci->fmnumber);
  1112. dumptd(td, "failed", ed->ctrl & Ediso);
  1113. }
  1114. }
  1115. td->bp->wp = td->bp->rp;
  1116. td->nbytes = 0;
  1117. td->anext = iso->atds;
  1118. iso->atds = td;
  1119. iso->navail++;
  1120. /*
  1121. * If almost all Tds are avail the user is not doing I/O at the
  1122. * required rate. We put another Td in place to keep the polling rate.
  1123. */
  1124. if(iso->err == nil && iso->navail > iso->nframes - 10)
  1125. isoadvance(ep, iso, pa2ptr(iso->ed->tail));
  1126. /*
  1127. * If there's enough buffering futher I/O can be done.
  1128. */
  1129. if(isocanwrite(iso))
  1130. wakeup(iso);
  1131. }
  1132. static void
  1133. interrupt(Ureg *, void *arg)
  1134. {
  1135. Td *td, *ntd;
  1136. Hci *hp;
  1137. Ctlr *ctlr;
  1138. ulong status, curred;
  1139. int i, frno;
  1140. hp = arg;
  1141. ctlr = hp->aux;
  1142. ilock(ctlr);
  1143. ctlr->ohci->intrdisable = Mie;
  1144. coherence();
  1145. status = ctlr->ohci->intrsts & ctlr->ohci->intrenable;
  1146. status &= Oc|Rhsc|Fno|Ue|Rd|Sf|Wdh|So;
  1147. frno = TRUNC(ctlr->ohci->fmnumber, Ntdframes);
  1148. if(status & Wdh){
  1149. /* lsb of donehead has bit to flag other intrs. */
  1150. td = pa2ptr(ctlr->hcca->donehead & ~0xF);
  1151. for(i = 0; td != nil && i < 1024; i++){
  1152. if(0)ddprint("ohci tdinterrupt: td %#p\n", td);
  1153. ntd = pa2ptr(td->nexttd & ~0xF);
  1154. td->nexttd = 0;
  1155. if(td->ep == nil || td->io == nil)
  1156. panic("ohci: interrupt: ep %#p io %#p",
  1157. td->ep, td->io);
  1158. ohciinterrupts[td->ep->ttype]++;
  1159. if(td->ep->ttype == Tiso)
  1160. isointerrupt(ctlr, td->ep, td->io, td, frno);
  1161. else
  1162. qhinterrupt(ctlr, td->ep, td->io, td, frno);
  1163. td = ntd;
  1164. }
  1165. if(i >= 1024)
  1166. print("ohci: bug: more than 1024 done Tds?\n");
  1167. ctlr->hcca->donehead = 0;
  1168. }
  1169. ctlr->ohci->intrsts = status;
  1170. status &= ~Wdh;
  1171. status &= ~Sf;
  1172. if(status & So){
  1173. print("ohci: sched overrun: too much load\n");
  1174. ctlr->overrun++;
  1175. status &= ~So;
  1176. }
  1177. if((status & Ue) != 0){
  1178. curred = ctlr->ohci->periodcurred;
  1179. print("ohci: unrecoverable error frame 0x%.8lux ed 0x%.8lux, "
  1180. "ints %d %d %d %d\n",
  1181. ctlr->ohci->fmnumber, curred,
  1182. ohciinterrupts[Tctl], ohciinterrupts[Tintr],
  1183. ohciinterrupts[Tbulk], ohciinterrupts[Tiso]);
  1184. if(curred != 0)
  1185. dumped(pa2ptr(curred));
  1186. status &= ~Ue;
  1187. }
  1188. if(status != 0)
  1189. print("ohci interrupt: unhandled sts 0x%.8lux\n", status);
  1190. ctlr->ohci->intrenable = Mie | Wdh | Ue;
  1191. iunlock(ctlr);
  1192. }
  1193. /*
  1194. * The old dummy Td is used to implement the new Td.
  1195. * A new dummy is linked at the end of the old one and
  1196. * returned, to link further Tds if needed.
  1197. */
  1198. static Td*
  1199. epgettd(Ep *ep, Qio *io, Td **dtdp, int flags, void *a, int count)
  1200. {
  1201. Td *td, *dtd;
  1202. Block *bp;
  1203. if(count <= BY2PG)
  1204. bp = allocb(count);
  1205. else{
  1206. if(count > 2*BY2PG)
  1207. panic("ohci: transfer > two pages");
  1208. /* maximum of one physical page crossing allowed */
  1209. bp = allocb(count+BY2PG);
  1210. bp->rp = (uchar*)PGROUND((uintptr)bp->rp);
  1211. bp->wp = bp->rp;
  1212. }
  1213. dtd = *dtdp;
  1214. td = dtd;
  1215. td->bp = bp;
  1216. if(count > 0){
  1217. td->cbp0 = td->cbp = ptr2pa(bp->wp);
  1218. td->be = ptr2pa(bp->wp + count - 1);
  1219. if(a != nil){
  1220. /* validaddr((uintptr)a, count, 0); DEBUG */
  1221. memmove(bp->wp, a, count);
  1222. }
  1223. bp->wp += count;
  1224. }
  1225. td->nbytes = count;
  1226. td->ctrl = io->tok|Tdusetog|io->toggle|flags;
  1227. if(io->toggle == Tddata0)
  1228. io->toggle = Tddata1;
  1229. else
  1230. io->toggle = Tddata0;
  1231. assert(td->ep == ep);
  1232. td->io = io;
  1233. dtd = tdalloc(); /* new dummy */
  1234. dtd->ep = ep;
  1235. td->nexttd = ptr2pa(dtd);
  1236. td->next = dtd;
  1237. *dtdp = dtd;
  1238. return td;
  1239. }
  1240. /*
  1241. * Try to get them idle
  1242. */
  1243. static void
  1244. aborttds(Qio *io)
  1245. {
  1246. Ed *ed;
  1247. Td *td;
  1248. ed = io->ed;
  1249. if(ed == nil)
  1250. return;
  1251. ed->ctrl |= Edskip;
  1252. for(td = ed->tds; td != nil; td = td->next)
  1253. if(td->bp != nil)
  1254. td->bp->wp = td->bp->rp;
  1255. ed->head = (ed->head&0xF) | ed->tail;
  1256. if((ed->ctrl & Ediso) == 0)
  1257. ed->tds = pa2ptr(ed->tail);
  1258. }
  1259. static int
  1260. epiodone(void *a)
  1261. {
  1262. Qio *io;
  1263. io = a;
  1264. return io->state != Qrun;
  1265. }
  1266. static void
  1267. epiowait(Ctlr *ctlr, Qio *io, int tmout, ulong)
  1268. {
  1269. Ed *ed;
  1270. int timedout;
  1271. ed = io->ed;
  1272. if(0)ddqprint("ohci io %#p sleep on ed %#p state %s\n",
  1273. io, ed, iosname[io->state]);
  1274. timedout = 0;
  1275. if(waserror()){
  1276. dqprint("ohci io %#p ed %#p timed out\n", io, ed);
  1277. timedout++;
  1278. }else{
  1279. if(tmout == 0)
  1280. sleep(io, epiodone, io);
  1281. else
  1282. tsleep(io, epiodone, io, tmout);
  1283. poperror();
  1284. }
  1285. ilock(ctlr);
  1286. if(io->state == Qrun)
  1287. timedout = 1;
  1288. else if(io->state != Qdone && io->state != Qclose)
  1289. panic("epio: ed not done and not closed");
  1290. if(timedout){
  1291. aborttds(io);
  1292. io->err = "request timed out";
  1293. iunlock(ctlr);
  1294. if(!waserror()){
  1295. tsleep(&up->sleep, return0, 0, Abortdelay);
  1296. poperror();
  1297. }
  1298. ilock(ctlr);
  1299. }
  1300. if(io->state != Qclose)
  1301. io->state = Qidle;
  1302. iunlock(ctlr);
  1303. }
  1304. /*
  1305. * Non iso I/O.
  1306. * To make it work for control transfers, the caller may
  1307. * lock the Qio for the entire control transfer.
  1308. */
  1309. static long
  1310. epio(Ep *ep, Qio *io, void *a, long count, int mustlock)
  1311. {
  1312. Ed *ed;
  1313. Ctlr *ctlr;
  1314. char buf[80];
  1315. char *err;
  1316. uchar *c;
  1317. Td *td, *ltd, *ntd, *td0;
  1318. int last, ntds, tmout;
  1319. long tot, n;
  1320. ulong load;
  1321. ed = io->ed;
  1322. ctlr = ep->hp->aux;
  1323. io->debug = ep->debug;
  1324. tmout = ep->tmout;
  1325. ddeprint("ohci: %s ep%d.%d io %#p count %ld\n",
  1326. io->tok == Tdtokin ? "in" : "out",
  1327. ep->dev->nb, ep->nb, io, count);
  1328. if((debug > 1 || ep->debug > 1) && io->tok != Tdtokin){
  1329. seprintdata(buf, buf+sizeof(buf), a, count);
  1330. print("\t%s\n", buf);
  1331. }
  1332. if(mustlock){
  1333. qlock(io);
  1334. if(waserror()){
  1335. qunlock(io);
  1336. nexterror();
  1337. }
  1338. }
  1339. io->err = nil;
  1340. ilock(ctlr);
  1341. if(io->state == Qclose){ /* Tds released by cancelio */
  1342. iunlock(ctlr);
  1343. error(io->err ? io->err : Eio);
  1344. }
  1345. if(io->state != Qidle)
  1346. panic("epio: qio not idle");
  1347. io->state = Qinstall;
  1348. c = a;
  1349. ltd = td0 = ed->tds;
  1350. load = tot = 0;
  1351. do{
  1352. n = 2*BY2PG;
  1353. if(count-tot < n)
  1354. n = count-tot;
  1355. if(c != nil && io->tok != Tdtokin)
  1356. td = epgettd(ep, io, &ltd, 0, c+tot, n);
  1357. else
  1358. td = epgettd(ep, io, &ltd, 0, nil, n);
  1359. tot += n;
  1360. load += ep->load;
  1361. }while(tot < count);
  1362. if(td0 == nil || ltd == nil || td0 == ltd)
  1363. panic("epio: no td");
  1364. td->last = 1;
  1365. if(debug > 2 || ep->debug > 2)
  1366. dumptds(td0, "put td", ep->ttype == Tiso);
  1367. iunlock(ctlr);
  1368. ilock(ctlr);
  1369. if(io->state != Qclose){
  1370. io->iotime = TK2MS(MACHP(0)->ticks);
  1371. io->state = Qrun;
  1372. ed->tail = ptr2pa(ltd);
  1373. if(ep->ttype == Tctl)
  1374. ctlr->ohci->cmdsts |= Sclf;
  1375. else if(ep->ttype == Tbulk)
  1376. ctlr->ohci->cmdsts |= Sblf;
  1377. }
  1378. iunlock(ctlr);
  1379. epiowait(ctlr, io, tmout, load);
  1380. ilock(ctlr);
  1381. if(debug > 1 || ep->debug > 1)
  1382. dumptds(td0, "got td", 0);
  1383. iunlock(ctlr);
  1384. tot = 0;
  1385. c = a;
  1386. ntds = last = 0;
  1387. for(td = td0; td != ltd; td = ntd){
  1388. ntds++;
  1389. /*
  1390. * If the Td is flagged as last we must
  1391. * ignore any following Td. The block may
  1392. * seem to have bytes but interrupt has not seen
  1393. * those Tds through the done queue, and they are void.
  1394. */
  1395. if(last == 0 && tderrs(td) == Tdok){
  1396. n = BLEN(td->bp);
  1397. tot += n;
  1398. if(c != nil && tdtok(td) == Tdtokin && n > 0){
  1399. memmove(c, td->bp->rp, n);
  1400. c += n;
  1401. }
  1402. }
  1403. last |= td->last;
  1404. ntd = td->next;
  1405. tdfree(td);
  1406. }
  1407. if(edtoggle(ed) == 0)
  1408. io->toggle = Tddata0;
  1409. else
  1410. io->toggle = Tddata1;
  1411. err = io->err;
  1412. if(mustlock){
  1413. qunlock(io);
  1414. poperror();
  1415. }
  1416. ddeprint("ohci: io %#p: %d tds: return %ld err '%s'\n\n",
  1417. io, ntds, tot, err);
  1418. if(err != nil)
  1419. error(err);
  1420. if(tot < 0)
  1421. error(Eio);
  1422. return tot;
  1423. }
  1424. /*
  1425. * halt condition was cleared on the endpoint. update our toggles.
  1426. */
  1427. static void
  1428. clrhalt(Ep *ep)
  1429. {
  1430. Qio *io;
  1431. ep->clrhalt = 0;
  1432. switch(ep->ttype){
  1433. case Tbulk:
  1434. case Tintr:
  1435. io = ep->aux;
  1436. if(ep->mode != OREAD){
  1437. qlock(&io[OWRITE]);
  1438. io[OWRITE].toggle = Tddata0;
  1439. deprint("ep clrhalt for io %#p\n", io+OWRITE);
  1440. qunlock(&io[OWRITE]);
  1441. }
  1442. if(ep->mode != OWRITE){
  1443. qlock(&io[OREAD]);
  1444. io[OREAD].toggle = Tddata0;
  1445. deprint("ep clrhalt for io %#p\n", io+OREAD);
  1446. qunlock(&io[OREAD]);
  1447. }
  1448. break;
  1449. }
  1450. }
  1451. static long
  1452. epread(Ep *ep, void *a, long count)
  1453. {
  1454. Ctlio *cio;
  1455. Qio *io;
  1456. char buf[80];
  1457. ulong delta;
  1458. if(ep->aux == nil)
  1459. panic("epread: not open");
  1460. switch(ep->ttype){
  1461. case Tctl:
  1462. cio = ep->aux;
  1463. qlock(cio);
  1464. if(waserror()){
  1465. qunlock(cio);
  1466. nexterror();
  1467. }
  1468. ddeprint("epread ctl ndata %d\n", cio->ndata);
  1469. if(cio->ndata < 0)
  1470. error("request expected");
  1471. else if(cio->ndata == 0){
  1472. cio->ndata = -1;
  1473. count = 0;
  1474. }else{
  1475. if(count > cio->ndata)
  1476. count = cio->ndata;
  1477. if(count > 0)
  1478. memmove(a, cio->data, count);
  1479. /* BUG for big transfers */
  1480. free(cio->data);
  1481. cio->data = nil;
  1482. cio->ndata = 0; /* signal EOF next time */
  1483. }
  1484. qunlock(cio);
  1485. poperror();
  1486. if(debug>1 || ep->debug){
  1487. seprintdata(buf, buf+sizeof(buf), a, count);
  1488. print("epread: %s\n", buf);
  1489. }
  1490. return count;
  1491. case Tbulk:
  1492. io = ep->aux;
  1493. if(ep->clrhalt)
  1494. clrhalt(ep);
  1495. return epio(ep, &io[OREAD], a, count, 1);
  1496. case Tintr:
  1497. io = ep->aux;
  1498. delta = TK2MS(MACHP(0)->ticks) - io[OREAD].iotime + 1;
  1499. if(delta < ep->pollival / 2)
  1500. tsleep(&up->sleep, return0, 0, ep->pollival/2 - delta);
  1501. if(ep->clrhalt)
  1502. clrhalt(ep);
  1503. return epio(ep, &io[OREAD], a, count, 1);
  1504. case Tiso:
  1505. panic("ohci: iso read not implemented");
  1506. break;
  1507. default:
  1508. panic("epread: bad ep ttype %d", ep->ttype);
  1509. }
  1510. return -1;
  1511. }
  1512. /*
  1513. * Control transfers are one setup write (data0)
  1514. * plus zero or more reads/writes (data1, data0, ...)
  1515. * plus a final write/read with data1 to ack.
  1516. * For both host to device and device to host we perform
  1517. * the entire transfer when the user writes the request,
  1518. * and keep any data read from the device for a later read.
  1519. * We call epio three times instead of placing all Tds at
  1520. * the same time because doing so leads to crc/tmout errors
  1521. * for some devices.
  1522. * Upon errors on the data phase we must still run the status
  1523. * phase or the device may cease responding in the future.
  1524. */
  1525. static long
  1526. epctlio(Ep *ep, Ctlio *cio, void *a, long count)
  1527. {
  1528. uchar *c;
  1529. long len;
  1530. ddeprint("epctlio: cio %#p ep%d.%d count %ld\n",
  1531. cio, ep->dev->nb, ep->nb, count);
  1532. if(count < Rsetuplen)
  1533. error("short usb command");
  1534. qlock(cio);
  1535. free(cio->data);
  1536. cio->data = nil;
  1537. cio->ndata = 0;
  1538. if(waserror()){
  1539. qunlock(cio);
  1540. free(cio->data);
  1541. cio->data = nil;
  1542. cio->ndata = 0;
  1543. nexterror();
  1544. }
  1545. /* set the address if unset and out of configuration state */
  1546. if(ep->dev->state != Dconfig && ep->dev->state != Dreset)
  1547. if(cio->usbid == 0){
  1548. cio->usbid = (ep->nb<<7)|(ep->dev->nb & Devmax);
  1549. edsetaddr(cio->ed, cio->usbid);
  1550. }
  1551. /* adjust maxpkt if the user has learned a different one */
  1552. if(edmaxpkt(cio->ed) != ep->maxpkt)
  1553. edsetmaxpkt(cio->ed, ep->maxpkt);
  1554. c = a;
  1555. cio->tok = Tdtoksetup;
  1556. cio->toggle = Tddata0;
  1557. if(epio(ep, cio, a, Rsetuplen, 0) < Rsetuplen)
  1558. error(Eio);
  1559. a = c + Rsetuplen;
  1560. count -= Rsetuplen;
  1561. cio->toggle = Tddata1;
  1562. if(c[Rtype] & Rd2h){
  1563. cio->tok = Tdtokin;
  1564. len = GET2(c+Rcount);
  1565. if(len <= 0)
  1566. error("bad length in d2h request");
  1567. if(len > Maxctllen)
  1568. error("d2h data too large to fit in ohci");
  1569. a = cio->data = smalloc(len+1);
  1570. }else{
  1571. cio->tok = Tdtokout;
  1572. len = count;
  1573. }
  1574. if(len > 0)
  1575. if(waserror())
  1576. len = -1;
  1577. else{
  1578. len = epio(ep, cio, a, len, 0);
  1579. poperror();
  1580. }
  1581. if(c[Rtype] & Rd2h){
  1582. count = Rsetuplen;
  1583. cio->ndata = len;
  1584. cio->tok = Tdtokout;
  1585. }else{
  1586. if(len < 0)
  1587. count = -1;
  1588. else
  1589. count = Rsetuplen + len;
  1590. cio->tok = Tdtokin;
  1591. }
  1592. cio->toggle = Tddata1;
  1593. epio(ep, cio, nil, 0, 0);
  1594. qunlock(cio);
  1595. poperror();
  1596. ddeprint("epctlio cio %#p return %ld\n", cio, count);
  1597. return count;
  1598. }
  1599. /*
  1600. * Put new samples in the dummy Td.
  1601. * BUG: This does only a transfer per Td. We could do up to 8.
  1602. */
  1603. static long
  1604. putsamples(Ctlr *ctlr, Ep *ep, Isoio *iso, uchar *b, long count)
  1605. {
  1606. Td *td;
  1607. ulong n;
  1608. td = pa2ptr(iso->ed->tail);
  1609. n = count;
  1610. if(n > td->nbytes - BLEN(td->bp))
  1611. n = td->nbytes - BLEN(td->bp);
  1612. assert(td->bp->wp + n <= td->bp->lim);
  1613. memmove(td->bp->wp, b, n);
  1614. td->bp->wp += n;
  1615. if(BLEN(td->bp) == td->nbytes){ /* full Td: activate it */
  1616. ilock(ctlr);
  1617. isoadvance(ep, iso, td);
  1618. iunlock(ctlr);
  1619. }
  1620. return n;
  1621. }
  1622. static long
  1623. episowrite(Ep *ep, void *a, long count)
  1624. {
  1625. long tot, nw;
  1626. char *err;
  1627. uchar *b;
  1628. Ctlr *ctlr;
  1629. Isoio *iso;
  1630. ctlr = ep->hp->aux;
  1631. iso = ep->aux;
  1632. iso->debug = ep->debug;
  1633. qlock(iso);
  1634. if(waserror()){
  1635. qunlock(iso);
  1636. nexterror();
  1637. }
  1638. diprint("ohci: episowrite: %#p ep%d.%d\n", iso, ep->dev->nb, ep->nb);
  1639. ilock(ctlr);
  1640. if(iso->state == Qclose){
  1641. iunlock(ctlr);
  1642. error(iso->err ? iso->err : Eio);
  1643. }
  1644. iso->state = Qrun;
  1645. b = a;
  1646. for(tot = 0; tot < count; tot += nw){
  1647. while(isocanwrite(iso) == 0){
  1648. iunlock(ctlr);
  1649. diprint("ohci: episowrite: %#p sleep\n", iso);
  1650. if(waserror()){
  1651. if(iso->err == nil)
  1652. iso->err = "I/O timed out";
  1653. ilock(ctlr);
  1654. break;
  1655. }
  1656. tsleep(iso, isocanwrite, iso, ep->tmout);
  1657. poperror();
  1658. ilock(ctlr);
  1659. }
  1660. err = iso->err;
  1661. iso->err = nil;
  1662. if(iso->state == Qclose || err != nil){
  1663. iunlock(ctlr);
  1664. error(err ? err : Eio);
  1665. }
  1666. if(iso->state != Qrun)
  1667. panic("episowrite: iso not running");
  1668. iunlock(ctlr); /* We could page fault here */
  1669. nw = putsamples(ctlr, ep, iso, b+tot, count-tot);
  1670. ilock(ctlr);
  1671. }
  1672. if(iso->state != Qclose)
  1673. iso->state = Qdone;
  1674. iunlock(ctlr);
  1675. err = iso->err; /* in case it failed early */
  1676. iso->err = nil;
  1677. qunlock(iso);
  1678. poperror();
  1679. if(err != nil)
  1680. error(err);
  1681. diprint("ohci: episowrite: %#p %ld bytes\n", iso, tot);
  1682. return tot;
  1683. }
  1684. static long
  1685. epwrite(Ep *ep, void *a, long count)
  1686. {
  1687. Qio *io;
  1688. Ctlio *cio;
  1689. ulong delta;
  1690. uchar *b;
  1691. long tot, nw;
  1692. if(ep->aux == nil)
  1693. panic("ohci: epwrite: not open");
  1694. switch(ep->ttype){
  1695. case Tctl:
  1696. cio = ep->aux;
  1697. return epctlio(ep, cio, a, count);
  1698. case Tbulk:
  1699. io = ep->aux;
  1700. if(ep->clrhalt)
  1701. clrhalt(ep);
  1702. /*
  1703. * Put at most Tdatomic Tds (512 bytes) at a time.
  1704. * Otherwise some devices produce babble errors.
  1705. */
  1706. b = a;
  1707. assert(a != nil);
  1708. for(tot = 0; tot < count ; tot += nw){
  1709. nw = count - tot;
  1710. if(nw > Tdatomic * ep->maxpkt)
  1711. nw = Tdatomic * ep->maxpkt;
  1712. nw = epio(ep, &io[OWRITE], b+tot, nw, 1);
  1713. }
  1714. return tot;
  1715. case Tintr:
  1716. io = ep->aux;
  1717. delta = TK2MS(MACHP(0)->ticks) - io[OWRITE].iotime + 1;
  1718. if(delta < ep->pollival)
  1719. tsleep(&up->sleep, return0, 0, ep->pollival - delta);
  1720. if(ep->clrhalt)
  1721. clrhalt(ep);
  1722. return epio(ep, &io[OWRITE], a, count, 1);
  1723. case Tiso:
  1724. return episowrite(ep, a, count);
  1725. default:
  1726. panic("ohci: epwrite: bad ep ttype %d", ep->ttype);
  1727. }
  1728. return -1;
  1729. }
  1730. static Ed*
  1731. newed(Ctlr *ctlr, Ep *ep, Qio *io, char *)
  1732. {
  1733. Ed *ed;
  1734. Td *td;
  1735. ed = io->ed = edalloc(); /* no errors raised here, really */
  1736. td = tdalloc();
  1737. td->ep = ep;
  1738. td->io = io;
  1739. ed->tail = ptr2pa(td);
  1740. ed->head = ptr2pa(td);
  1741. ed->tds = td;
  1742. ed->ep = ep;
  1743. ed->ctrl = (ep->maxpkt & Edmpsmask) << Edmpsshift;
  1744. if(ep->ttype == Tiso)
  1745. ed->ctrl |= Ediso;
  1746. if(waserror()){
  1747. edfree(ed);
  1748. io->ed = nil;
  1749. nexterror();
  1750. }
  1751. /* For setup endpoints we start with the config address */
  1752. if(ep->ttype != Tctl)
  1753. edsetaddr(io->ed, io->usbid);
  1754. if(ep->dev->speed == Lowspeed)
  1755. ed->ctrl |= Edlow;
  1756. switch(io->tok){
  1757. case Tdtokin:
  1758. ed->ctrl |= Edin;
  1759. break;
  1760. case Tdtokout:
  1761. ed->ctrl |= Edout;
  1762. break;
  1763. default:
  1764. ed->ctrl |= Edtddir; /* Td will say */
  1765. break;
  1766. }
  1767. switch(ep->ttype){
  1768. case Tctl:
  1769. ilock(ctlr);
  1770. edlinked(ed, ctlhd(ctlr));
  1771. setctlhd(ctlr, ed);
  1772. iunlock(ctlr);
  1773. break;
  1774. case Tbulk:
  1775. ilock(ctlr);
  1776. edlinked(ed, bulkhd(ctlr));
  1777. setbulkhd(ctlr, ed);
  1778. iunlock(ctlr);
  1779. break;
  1780. case Tintr:
  1781. case Tiso:
  1782. ilock(ctlr);
  1783. schedq(ctlr, io, ep->pollival);
  1784. iunlock(ctlr);
  1785. break;
  1786. default:
  1787. panic("ohci: newed: bad ttype");
  1788. }
  1789. poperror();
  1790. return ed;
  1791. }
  1792. static void
  1793. isoopen(Ctlr *ctlr, Ep *ep)
  1794. {
  1795. Td *td, *edtds;
  1796. Isoio *iso;
  1797. int i;
  1798. iso = ep->aux;
  1799. iso->usbid = (ep->nb<<7)|(ep->dev->nb & Devmax);
  1800. iso->bw = ep->hz * ep->samplesz; /* bytes/sec */
  1801. if(ep->mode != OWRITE){
  1802. print("ohci: bug: iso input streams not implemented\n");
  1803. error("ohci iso input streams not implemented");
  1804. }else
  1805. iso->tok = Tdtokout;
  1806. iso->left = 0;
  1807. iso->nerrs = 0;
  1808. iso->frno = TRUNC(ctlr->ohci->fmnumber + 10, Ntdframes);
  1809. iso->nframes = 1000 / ep->pollival;
  1810. if(iso->nframes < 10){
  1811. print("ohci: isoopen: less than 10 frames; using 10.\n");
  1812. iso->nframes = 10;
  1813. }
  1814. iso->navail = iso->nframes;
  1815. iso->atds = edtds = nil;
  1816. for(i = 0; i < iso->nframes-1; i++){ /* -1 for dummy */
  1817. td = tdalloc();
  1818. td->ep = ep;
  1819. td->io = iso;
  1820. td->bp = allocb(ep->maxpkt);
  1821. td->anext = iso->atds; /* link as avail */
  1822. iso->atds = td;
  1823. td->next = edtds;
  1824. edtds = td;
  1825. }
  1826. newed(ctlr, ep, iso, "iso"); /* allocates a dummy td */
  1827. iso->ed->tds->bp = allocb(ep->maxpkt); /* but not its block */
  1828. iso->ed->tds->next = edtds;
  1829. isodtdinit(ep, iso, iso->ed->tds);
  1830. }
  1831. /*
  1832. * Allocate the endpoint and set it up for I/O
  1833. * in the controller. This must follow what's said
  1834. * in Ep regarding configuration, including perhaps
  1835. * the saved toggles (saved on a previous close of
  1836. * the endpoint data file by epclose).
  1837. */
  1838. static void
  1839. epopen(Ep *ep)
  1840. {
  1841. Ctlr *ctlr;
  1842. Qio *io;
  1843. Ctlio *cio;
  1844. ulong usbid;
  1845. ctlr = ep->hp->aux;
  1846. deprint("ohci: epopen ep%d.%d\n", ep->dev->nb, ep->nb);
  1847. if(ep->aux != nil)
  1848. panic("ohci: epopen called with open ep");
  1849. if(waserror()){
  1850. free(ep->aux);
  1851. ep->aux = nil;
  1852. nexterror();
  1853. }
  1854. switch(ep->ttype){
  1855. case Tnone:
  1856. error("endpoint not configured");
  1857. case Tiso:
  1858. ep->aux = smalloc(sizeof(Isoio));
  1859. isoopen(ctlr, ep);
  1860. break;
  1861. case Tctl:
  1862. cio = ep->aux = smalloc(sizeof(Ctlio));
  1863. cio->debug = ep->debug;
  1864. cio->ndata = -1;
  1865. cio->data = nil;
  1866. cio->tok = -1; /* invalid; Tds will say */
  1867. if(ep->dev->isroot != 0 && ep->nb == 0) /* root hub */
  1868. break;
  1869. newed(ctlr, ep, cio, "epc");
  1870. break;
  1871. case Tbulk:
  1872. ep->pollival = 1; /* assume this; doesn't really matter */
  1873. /* and fall... */
  1874. case Tintr:
  1875. io = ep->aux = smalloc(sizeof(Qio)*2);
  1876. io[OREAD].debug = io[OWRITE].debug = ep->debug;
  1877. usbid = (ep->nb<<7)|(ep->dev->nb & Devmax);
  1878. if(ep->mode != OREAD){
  1879. if(ep->toggle[OWRITE] != 0)
  1880. io[OWRITE].toggle = Tddata1;
  1881. else
  1882. io[OWRITE].toggle = Tddata0;
  1883. io[OWRITE].tok = Tdtokout;
  1884. io[OWRITE].usbid = usbid;
  1885. io[OWRITE].bw = ep->maxpkt*1000/ep->pollival; /* bytes/s */
  1886. newed(ctlr, ep, io+OWRITE, "epw");
  1887. }
  1888. if(ep->mode != OWRITE){
  1889. if(ep->toggle[OREAD] != 0)
  1890. io[OREAD].toggle = Tddata1;
  1891. else
  1892. io[OREAD].toggle = Tddata0;
  1893. io[OREAD].tok = Tdtokin;
  1894. io[OREAD].usbid = usbid;
  1895. io[OREAD].bw = ep->maxpkt*1000/ep->pollival; /* bytes/s */
  1896. newed(ctlr, ep, io+OREAD, "epr");
  1897. }
  1898. break;
  1899. }
  1900. deprint("ohci: epopen done:\n");
  1901. if(debug || ep->debug)
  1902. dump(ep->hp);
  1903. poperror();
  1904. }
  1905. static void
  1906. cancelio(Ep *ep, Qio *io)
  1907. {
  1908. Ed *ed;
  1909. Ctlr *ctlr;
  1910. ctlr = ep->hp->aux;
  1911. ilock(ctlr);
  1912. if(io == nil || io->state == Qclose){
  1913. assert(io == nil || io->ed == nil);
  1914. iunlock(ctlr);
  1915. return;
  1916. }
  1917. ed = io->ed;
  1918. io->state = Qclose;
  1919. io->err = Eio;
  1920. aborttds(io);
  1921. iunlock(ctlr);
  1922. if(!waserror()){
  1923. tsleep(&up->sleep, return0, 0, Abortdelay);
  1924. poperror();
  1925. }
  1926. wakeup(io);
  1927. qlock(io);
  1928. /* wait for epio if running */
  1929. qunlock(io);
  1930. ilock(ctlr);
  1931. switch(ep->ttype){
  1932. case Tctl:
  1933. unlinkctl(ctlr, ed);
  1934. break;
  1935. case Tbulk:
  1936. unlinkbulk(ctlr, ed);
  1937. break;
  1938. case Tintr:
  1939. case Tiso:
  1940. unschedq(ctlr, io);
  1941. break;
  1942. default:
  1943. panic("ohci cancelio: bad ttype");
  1944. }
  1945. iunlock(ctlr);
  1946. edfree(io->ed);
  1947. io->ed = nil;
  1948. }
  1949. static void
  1950. epclose(Ep *ep)
  1951. {
  1952. Ctlio *cio;
  1953. Isoio *iso;
  1954. Qio *io;
  1955. deprint("ohci: epclose ep%d.%d\n", ep->dev->nb, ep->nb);
  1956. if(ep->aux == nil)
  1957. panic("ohci: epclose called with closed ep");
  1958. switch(ep->ttype){
  1959. case Tctl:
  1960. cio = ep->aux;
  1961. cancelio(ep, cio);
  1962. free(cio->data);
  1963. cio->data = nil;
  1964. break;
  1965. case Tbulk:
  1966. case Tintr:
  1967. io = ep->aux;
  1968. if(ep->mode != OWRITE){
  1969. cancelio(ep, &io[OREAD]);
  1970. if(io[OREAD].toggle == Tddata1)
  1971. ep->toggle[OREAD] = 1;
  1972. }
  1973. if(ep->mode != OREAD){
  1974. cancelio(ep, &io[OWRITE]);
  1975. if(io[OWRITE].toggle == Tddata1)
  1976. ep->toggle[OWRITE] = 1;
  1977. }
  1978. break;
  1979. case Tiso:
  1980. iso = ep->aux;
  1981. cancelio(ep, iso);
  1982. break;
  1983. default:
  1984. panic("epclose: bad ttype %d", ep->ttype);
  1985. }
  1986. deprint("ohci: epclose ep%d.%d: done\n", ep->dev->nb, ep->nb);
  1987. free(ep->aux);
  1988. ep->aux = nil;
  1989. }
  1990. static int
  1991. portreset(Hci *hp, int port, int on)
  1992. {
  1993. Ctlr *ctlr;
  1994. Ohci *ohci;
  1995. if(on == 0)
  1996. return 0;
  1997. ctlr = hp->aux;
  1998. qlock(&ctlr->resetl);
  1999. if(waserror()){
  2000. qunlock(&ctlr->resetl);
  2001. nexterror();
  2002. }
  2003. ilock(ctlr);
  2004. ohci = ctlr->ohci;
  2005. ohci->rhportsts[port - 1] = Spp;
  2006. if((ohci->rhportsts[port - 1] & Ccs) == 0){
  2007. iunlock(ctlr);
  2008. error("port not connected");
  2009. }
  2010. ohci->rhportsts[port - 1] = Spr;
  2011. while((ohci->rhportsts[port - 1] & Prsc) == 0){
  2012. iunlock(ctlr);
  2013. dprint("ohci: portreset, wait for reset complete\n");
  2014. ilock(ctlr);
  2015. }
  2016. ohci->rhportsts[port - 1] = Prsc;
  2017. iunlock(ctlr);
  2018. poperror();
  2019. qunlock(&ctlr->resetl);
  2020. return 0;
  2021. }
  2022. static int
  2023. portenable(Hci *hp, int port, int on)
  2024. {
  2025. Ctlr *ctlr;
  2026. ctlr = hp->aux;
  2027. dprint("ohci: %#p port %d enable=%d\n", ctlr->ohci, port, on);
  2028. qlock(&ctlr->resetl);
  2029. if(waserror()){
  2030. qunlock(&ctlr->resetl);
  2031. nexterror();
  2032. }
  2033. ilock(ctlr);
  2034. if(on)
  2035. ctlr->ohci->rhportsts[port - 1] = Spe | Spp;
  2036. else
  2037. ctlr->ohci->rhportsts[port - 1] = Cpe;
  2038. iunlock(ctlr);
  2039. tsleep(&up->sleep, return0, 0, Enabledelay);
  2040. poperror();
  2041. qunlock(&ctlr->resetl);
  2042. return 0;
  2043. }
  2044. static int
  2045. portstatus(Hci *hp, int port)
  2046. {
  2047. int v;
  2048. Ctlr *ub;
  2049. ulong ohcistatus;
  2050. /*
  2051. * We must return status bits as a
  2052. * get port status hub request would do.
  2053. */
  2054. ub = hp->aux;
  2055. ohcistatus = ub->ohci->rhportsts[port - 1];
  2056. v = 0;
  2057. if(ohcistatus & Ccs)
  2058. v |= HPpresent;
  2059. if(ohcistatus & Pes)
  2060. v |= HPenable;
  2061. if(ohcistatus & Pss)
  2062. v |= HPsuspend;
  2063. if(ohcistatus & Prs)
  2064. v |= HPreset;
  2065. else {
  2066. /* port is not in reset; these potential writes are ok */
  2067. if(ohcistatus & Csc){
  2068. v |= HPstatuschg;
  2069. ub->ohci->rhportsts[port - 1] = Csc;
  2070. }
  2071. if(ohcistatus & Pesc){
  2072. v |= HPchange;
  2073. ub->ohci->rhportsts[port - 1] = Pesc;
  2074. }
  2075. }
  2076. if(ohcistatus & Lsda)
  2077. v |= HPslow;
  2078. if(v & (HPstatuschg|HPchange))
  2079. ddprint("ohci port %d sts %#ulx hub sts %#x\n", port, ohcistatus, v);
  2080. return v;
  2081. }
  2082. static void
  2083. dumpohci(Ctlr *ctlr)
  2084. {
  2085. int i;
  2086. ulong *ohci;
  2087. ohci = &ctlr->ohci->revision;
  2088. print("ohci registers: \n");
  2089. for(i = 0; i < sizeof(Ohci)/sizeof(ulong); i++)
  2090. if(i < 3 || ohci[i] != 0)
  2091. print("\t[%#2.2x]\t%#8.8ulx\n", i * 4, ohci[i]);
  2092. print("\n");
  2093. }
  2094. static void
  2095. init(Hci *hp)
  2096. {
  2097. Ctlr *ctlr;
  2098. Ohci *ohci;
  2099. int i;
  2100. ulong ival, ctrl, fmi;
  2101. ctlr = hp->aux;
  2102. dprint("ohci %#p init\n", ctlr->ohci);
  2103. ohci = ctlr->ohci;
  2104. fmi = ctlr->ohci->fminterval;
  2105. ctlr->ohci->cmdsts = Shcr; /* reset the block */
  2106. while(ctlr->ohci->cmdsts & Shcr)
  2107. delay(1); /* wait till reset complete, Ohci says 10us max. */
  2108. ctlr->ohci->fminterval = fmi;
  2109. /*
  2110. * now that soft reset is done we are in suspend state.
  2111. * Setup registers which take in suspend state
  2112. * (will only be here for 2ms).
  2113. */
  2114. ctlr->ohci->hcca = ptr2pa(ctlr->hcca);
  2115. setctlhd(ctlr, nil);
  2116. ctlr->ohci->ctlcurred = 0;
  2117. setbulkhd(ctlr, nil);
  2118. ctlr->ohci->bulkcurred = 0;
  2119. ohci->intrenable = Mie | Wdh | Ue;
  2120. ohci->control |= Ccle | Cble | Cple | Cie | Cfsoper;
  2121. /* set frame after operational */
  2122. ohci->rhdesca = Nps; /* no power switching */
  2123. if(ohci->rhdesca & Nps){
  2124. dprint("ohci: ports are not power switched\n");
  2125. }else{
  2126. dprint("ohci: ports are power switched\n");
  2127. ohci->rhdesca &= ~Psm;
  2128. ohci->rhsts &= ~Lpsc;
  2129. }
  2130. for(i = 0; i < ctlr->nports; i++) /* paranoia */
  2131. ohci->rhportsts[i] = 0; /* this has no effect */
  2132. delay(50);
  2133. for(i = 0; i < ctlr->nports; i++){
  2134. ohci->rhportsts[i] = Spp;
  2135. if((ohci->rhportsts[i] & Ccs) != 0)
  2136. ohci->rhportsts[i] |= Spr;
  2137. }
  2138. delay(100);
  2139. ctrl = ohci->control;
  2140. if((ctrl & Cfsmask) != Cfsoper){
  2141. ctrl = (ctrl & ~Cfsmask) | Cfsoper;
  2142. ohci->control = ctrl;
  2143. ohci->rhsts = Lpsc;
  2144. }
  2145. ival = ohci->fminterval & ~(Fmaxpktmask << Fmaxpktshift);
  2146. ohci->fminterval = ival | (5120 << Fmaxpktshift);
  2147. if(debug > 1)
  2148. dumpohci(ctlr);
  2149. }
  2150. static void
  2151. scanpci(void)
  2152. {
  2153. ulong mem;
  2154. Ctlr *ctlr;
  2155. Pcidev *p;
  2156. int i;
  2157. static int already = 0;
  2158. if(already)
  2159. return;
  2160. already = 1;
  2161. p = nil;
  2162. while(p = pcimatch(p, 0, 0)) {
  2163. /*
  2164. * Find Ohci controllers (Programming Interface = 0x10).
  2165. */
  2166. if(p->ccrb != Pcibcserial || p->ccru != Pciscusb ||
  2167. p->ccrp != 0x10)
  2168. continue;
  2169. mem = p->mem[0].bar & ~0x0F;
  2170. dprint("ohci: %x/%x port 0x%lux size 0x%x irq %d\n",
  2171. p->vid, p->did, mem, p->mem[0].size, p->intl);
  2172. if(mem == 0){
  2173. print("ohci: failed to map registers\n");
  2174. continue;
  2175. }
  2176. if(p->intl == 0xFF || p->intl == 0) {
  2177. print("ohci: no irq assigned for port %#lux\n", mem);
  2178. continue;
  2179. }
  2180. ctlr = malloc(sizeof(Ctlr));
  2181. if (ctlr == nil)
  2182. panic("ohci: out of memory");
  2183. ctlr->pcidev = p;
  2184. ctlr->ohci = vmap(mem, p->mem[0].size);
  2185. dprint("scanpci: ctlr %#p, ohci %#p\n", ctlr, ctlr->ohci);
  2186. pcisetbme(p);
  2187. pcisetpms(p, 0);
  2188. for(i = 0; i < Nhcis; i++)
  2189. if(ctlrs[i] == nil){
  2190. ctlrs[i] = ctlr;
  2191. break;
  2192. }
  2193. if(i == Nhcis)
  2194. print("ohci: bug: no more controllers\n");
  2195. }
  2196. }
  2197. static void
  2198. usbdebug(Hci*, int d)
  2199. {
  2200. debug = d;
  2201. }
  2202. /*
  2203. * build the periodic scheduling tree:
  2204. * framesize must be a multiple of the tree size
  2205. */
  2206. static void
  2207. mkqhtree(Ctlr *ctlr)
  2208. {
  2209. int i, n, d, o, leaf0, depth;
  2210. Ed **tree;
  2211. Qtree *qt;
  2212. depth = flog2(32);
  2213. n = (1 << (depth+1)) - 1;
  2214. qt = mallocz(sizeof(*qt), 1);
  2215. if(qt == nil)
  2216. panic("usb: can't allocate scheduling tree");
  2217. qt->nel = n;
  2218. qt->depth = depth;
  2219. qt->bw = mallocz(n * sizeof(qt->bw), 1);
  2220. qt->root = tree = mallocz(n * sizeof(Ed *), 1);
  2221. if(qt->bw == nil || qt->root == nil)
  2222. panic("usb: can't allocate scheduling tree");
  2223. for(i = 0; i < n; i++){
  2224. if((tree[i] = edalloc()) == nil)
  2225. panic("mkqhtree");
  2226. tree[i]->ctrl = (8 << Edmpsshift); /* not needed */
  2227. tree[i]->ctrl |= Edskip;
  2228. if(i > 0)
  2229. edlinked(tree[i], tree[(i-1)/2]);
  2230. else
  2231. edlinked(tree[i], nil);
  2232. }
  2233. ctlr->ntree = i;
  2234. dprint("ohci: tree: %d endpoints allocated\n", i);
  2235. /* distribute leaves evenly round the frame list */
  2236. leaf0 = n / 2;
  2237. for(i = 0; i < 32; i++){
  2238. o = 0;
  2239. for(d = 0; d < depth; d++){
  2240. o <<= 1;
  2241. if(i & (1 << d))
  2242. o |= 1;
  2243. }
  2244. if(leaf0 + o >= n){
  2245. print("leaf0=%d o=%d i=%d n=%d\n", leaf0, o, i, n);
  2246. break;
  2247. }
  2248. ctlr->hcca->intrtable[i] = ptr2pa(tree[leaf0 + o]);
  2249. }
  2250. ctlr->tree = qt;
  2251. }
  2252. static void
  2253. ohcimeminit(Ctlr *ctlr)
  2254. {
  2255. Hcca *hcca;
  2256. edfree(edalloc()); /* allocate pools now */
  2257. tdfree(tdalloc());
  2258. hcca = xspanalloc(sizeof(Hcca), 256, 0);
  2259. if(hcca == nil)
  2260. panic("usbhreset: no memory for Hcca");
  2261. memset(hcca, 0, sizeof(*hcca));
  2262. ctlr->hcca = hcca;
  2263. mkqhtree(ctlr);
  2264. }
  2265. static void
  2266. ohcireset(Ctlr *ctlr)
  2267. {
  2268. ilock(ctlr);
  2269. dprint("ohci %#p reset\n", ctlr->ohci);
  2270. /*
  2271. * usually enter here in reset, wait till its through,
  2272. * then do our own so we are on known timing conditions.
  2273. * Is this needed?
  2274. */
  2275. delay(100);
  2276. ctlr->ohci->control = 0;
  2277. delay(100);
  2278. /* legacy support register: turn off lunacy mode */
  2279. pcicfgw16(ctlr->pcidev, 0xc0, 0x2000);
  2280. iunlock(ctlr);
  2281. }
  2282. static void
  2283. shutdown(Hci *hp)
  2284. {
  2285. Ctlr *ctlr;
  2286. ctlr = hp->aux;
  2287. ilock(ctlr);
  2288. ctlr->ohci->intrdisable = Mie;
  2289. ctlr->ohci->control = 0;
  2290. coherence();
  2291. delay(100);
  2292. iunlock(ctlr);
  2293. }
  2294. static int
  2295. reset(Hci *hp)
  2296. {
  2297. int i;
  2298. Ctlr *ctlr;
  2299. Pcidev *p;
  2300. static Lock resetlck;
  2301. if(getconf("*nousbohci"))
  2302. return -1;
  2303. ilock(&resetlck);
  2304. scanpci();
  2305. /*
  2306. * Any adapter matches if no hp->port is supplied,
  2307. * otherwise the ports must match.
  2308. */
  2309. ctlr = nil;
  2310. for(i = 0; i < Nhcis && ctlrs[i] != nil; i++){
  2311. ctlr = ctlrs[i];
  2312. if(ctlr->active == 0)
  2313. if(hp->port == 0 || hp->port == (uintptr)ctlr->ohci){
  2314. ctlr->active = 1;
  2315. break;
  2316. }
  2317. }
  2318. iunlock(&resetlck);
  2319. if(ctlrs[i] == nil || i == Nhcis)
  2320. return -1;
  2321. if(ctlr->ohci->control == ~0)
  2322. return -1;
  2323. p = ctlr->pcidev;
  2324. hp->aux = ctlr;
  2325. hp->port = (uintptr)ctlr->ohci;
  2326. hp->irq = p->intl;
  2327. hp->tbdf = p->tbdf;
  2328. ctlr->nports = hp->nports = ctlr->ohci->rhdesca & 0xff;
  2329. ohcireset(ctlr);
  2330. ohcimeminit(ctlr);
  2331. /*
  2332. * Linkage to the generic HCI driver.
  2333. */
  2334. hp->init = init;
  2335. hp->dump = dump;
  2336. hp->interrupt = interrupt;
  2337. hp->epopen = epopen;
  2338. hp->epclose = epclose;
  2339. hp->epread = epread;
  2340. hp->epwrite = epwrite;
  2341. hp->seprintep = seprintep;
  2342. hp->portenable = portenable;
  2343. hp->portreset = portreset;
  2344. hp->portstatus = portstatus;
  2345. hp->shutdown = shutdown;
  2346. hp->debug = usbdebug;
  2347. hp->type = "ohci";
  2348. return 0;
  2349. }
  2350. void
  2351. usbohcilink(void)
  2352. {
  2353. addhcitype("ohci", reset);
  2354. }