2db.c 60 KB

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  1. #include <u.h>
  2. #include <libc.h>
  3. #include <bio.h>
  4. #include <mach.h>
  5. /*
  6. * 68020-specific debugger interface
  7. */
  8. static char *m68020excep(Map*, Rgetter);
  9. static int m68020foll(Map*, uvlong, Rgetter, uvlong*);
  10. static int m68020inst(Map*, uvlong, char, char*, int);
  11. static int m68020das(Map*, uvlong, char*, int);
  12. static int m68020instlen(Map*, uvlong);
  13. Machdata m68020mach =
  14. {
  15. {0x48,0x48,0,0}, /* break point #0 instr. */
  16. 2, /* size of break point instr. */
  17. beswab, /* convert short to local byte order */
  18. beswal, /* convert long to local byte order */
  19. beswav, /* convert vlong to local byte order */
  20. cisctrace, /* C traceback */
  21. ciscframe, /* frame finder */
  22. m68020excep, /* print exception */
  23. 0, /* breakpoint fixup */
  24. beieeesftos,
  25. beieeedftos,
  26. m68020foll, /* follow-set calculation */
  27. m68020inst, /* print instruction */
  28. m68020das, /* dissembler */
  29. m68020instlen, /* instruction size */
  30. };
  31. /*
  32. * 68020 exception frames
  33. */
  34. #define BPTTRAP 4 /* breakpoint gives illegal inst */
  35. static char * excep[] = {
  36. [2] "bus error",
  37. [3] "address error",
  38. [4] "illegal instruction",
  39. [5] "zero divide",
  40. [6] "CHK",
  41. [7] "TRAP",
  42. [8] "privilege violation",
  43. [9] "Trace",
  44. [10] "line 1010",
  45. [11] "line 1011",
  46. [13] "coprocessor protocol violation",
  47. [24] "spurious",
  48. [25] "incon",
  49. [26] "tac",
  50. [27] "auto 3",
  51. [28] "clock",
  52. [29] "auto 5",
  53. [30] "parity",
  54. [31] "mouse",
  55. [32] "system call",
  56. [33] "system call 1",
  57. [48] "FPCP branch",
  58. [49] "FPCP inexact",
  59. [50] "FPCP zero div",
  60. [51] "FPCP underflow",
  61. [52] "FPCP operand err",
  62. [53] "FPCP overflow",
  63. [54] "FPCP signal NAN",
  64. };
  65. static int m68020vec;
  66. static
  67. struct ftype{
  68. short fmt;
  69. short len;
  70. char *name;
  71. } ftype[] = { /* section 6.5.7 page 6-24 */
  72. { 0, 4*2, "Short Format" },
  73. { 1, 4*2, "Throwaway" },
  74. { 2, 6*2, "Instruction Exception" },
  75. { 3, 6*2, "MC68040 Floating Point Exception" },
  76. { 8, 29*2, "MC68010 Bus Fault" },
  77. { 7, 30*2, "MC68040 Bus Fault" },
  78. { 9, 10*2, "Coprocessor mid-Instruction" },
  79. { 10, 16*2, "MC68020 Short Bus Fault" },
  80. { 11, 46*2, "MC68020 Long Bus Fault" },
  81. { 0, 0, 0 }
  82. };
  83. static int
  84. m68020ufix(Map *map)
  85. {
  86. struct ftype *ft;
  87. int i, size, vec;
  88. ulong efl[2];
  89. uchar *ef=(uchar*)efl;
  90. ulong l;
  91. uvlong stktop;
  92. short fvo;
  93. /* The kernel proc pointer on a 68020 is always
  94. * at #8xxxxxxx; on the 68040 NeXT, the address
  95. * is always #04xxxxxx. the sun3 port at sydney
  96. * uses 0xf8xxxxxx to 0xffxxxxxx.
  97. */
  98. m68020vec = 0;
  99. if (get4(map, mach->kbase, (&l)) < 0)
  100. return -1;
  101. if ((l&0xfc000000) == 0x04000000) /* if NeXT */
  102. size = 30*2;
  103. else
  104. size = 46*2; /* 68020 */
  105. USED(size);
  106. stktop = mach->kbase+mach->pgsize;
  107. for(i=3; i<100; i++){
  108. if (get1(map, stktop-i*4, (uchar*)&l, 4)< 0)
  109. return -1;
  110. if(machdata->swal(l) == 0xBADC0C0A){
  111. if (get1(map, stktop-(i-1)*4, (uchar *)&efl[0], 4) < 0)
  112. return -1;
  113. if (get1(map, stktop-(i-2)*4, (uchar *)&efl[1], 4) < 0)
  114. return -1;
  115. fvo = (ef[6]<<8)|ef[7];
  116. vec = fvo & 0xfff;
  117. vec >>= 2;
  118. if(vec >= 256)
  119. continue;
  120. for(ft=ftype; ft->name; ft++) {
  121. if(ft->fmt == ((fvo>>12) & 0xF)){
  122. m68020vec = vec;
  123. return 1;
  124. }
  125. }
  126. break;
  127. }
  128. }
  129. return -1;
  130. }
  131. static char *
  132. m68020excep(Map *map, Rgetter rget)
  133. {
  134. uvlong pc;
  135. uchar buf[4];
  136. if (m68020ufix(map) < 0)
  137. return "bad exception frame";
  138. if(excep[m68020vec] == 0)
  139. return "bad exeception type";
  140. if(m68020vec == BPTTRAP) {
  141. pc = (*rget)(map, "PC");
  142. if (get1(map, pc, buf, machdata->bpsize) > 0)
  143. if(memcmp(buf, machdata->bpinst, machdata->bpsize) == 0)
  144. return "breakpoint";
  145. }
  146. return excep[m68020vec];
  147. }
  148. /* 68020 Disassembler and related functions */
  149. /*
  150. not supported: cpBcc, cpDBcc, cpGEN, cpScc, cpTRAPcc, cpRESTORE, cpSAVE
  151. opcode: 1 1 1 1 1 1
  152. 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
  153. %y - register number x x x
  154. %f - trap vector x x x
  155. %e - destination eff addr x x x x x x
  156. %p - conditional predicate x x x x x x
  157. %s - size code x x
  158. %C - cache code x x
  159. %E - source eff addr. x x x x x x
  160. %d - direction bit x
  161. %c - condition code x x x x
  162. %x - register number x x x
  163. %b - shift count x x x
  164. %q - daffy 3-bit quick operand or shift count x x x
  165. %i - immediate operand <varies>
  166. %t - offset(PC) <varies>
  167. word 1: 1 1 1 1 1 1
  168. 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
  169. %a - register number x x x
  170. %w - bit field width x x x x x
  171. %L - MMU function code (SFC/DFC/D%a/#[0-3]) x x x x x
  172. %P - conditional predicate x x x x x x
  173. %k - k factor x x x x x x x
  174. %m - register mask x x x x x x x x
  175. %N - control register id x x x x x x x x x x x x
  176. %j - (Dq != Dr) ? Dq:Dr : Dr x x x x x x
  177. %K - dynamic k register x x x
  178. %h - register number x x x
  179. %I - MMU function code mask x x x x
  180. %o - bit field offset x x x x x
  181. %u - register number x x x
  182. %D - float dest reg x x x
  183. %F - (fdr==fsr) ? "F%D" :"F%B,F%D" x x x x x x
  184. %S - float source type x x x
  185. %B - float source register x x x
  186. %Z - ATC level number x x x
  187. %H - MMU register x x x x
  188. %r - register type/number x x x x
  189. word 2: 1 1 1 1 1 1
  190. 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
  191. %A - register number x x x
  192. %U - register number x x x
  193. %R - register type,number x x x x
  194. -----------------------------------------------------------------------------
  195. %a - register [word 1: 0-2]
  196. %c - condition code [opcode: 8-11]
  197. %d - direction [opcode: 8]
  198. %e - destination effective address [opcode: 0-5]
  199. %f - trap vector [opcode: 0-3]
  200. %h - register [word 1: 5-7]
  201. %i - immediate operand (1, 2, or 4 bytes)
  202. %j - Dq:Dr if Dq != Dr; else Dr => Dr [word 1: 0-2] Dq [word 1: 12-14]
  203. %k - k factor [word 1: 0-6]
  204. %m - register mask [word 1: 0-7]
  205. %o - bit field offset [word 1: 6-10]
  206. %p - conditional predicate [opcode: 0-5]
  207. %q - daffy 3-bit quick operand [opcode: 9-11]
  208. %r - register type, [word 1: 15], register [word 1: 12-14]
  209. %s - size [opcode: 6-7]
  210. %t - offset beyond pc (text address) (2 or 4 bytes)
  211. %u - register [word 1: 6-8]
  212. %w - bit field width [word 1: 0-4]
  213. %x - register [opcode: 9-11]
  214. %y - register [opcode: 0-2]
  215. %A - register [word 2: 0-2]
  216. %B - float source register [word 1: 10-12]
  217. %C - cache identifier [opcode: 6-7] (IC, DC, or BC)
  218. %D - float dest reg [word 1: 7-9]
  219. %E - dest effective address [opcode: 6-11]
  220. %F - float dest reg == float src reg => "F%D"; else "F%B,F%D"
  221. %H - MMU reg [word 1: 10-13] (see above & p 4-53/54)
  222. %I - MMU function code mask [word 1: 5-8]
  223. %K - dynamic k factor register [word 1: 4-6]
  224. %L - MMU function code [word 1: 0-4] (SFC, DFC, D%a, or #[0-3])
  225. %N - control register [word 1: 0-11]
  226. %P - conditional predicate [word 1: 0-5]
  227. %R - register type, [word 2: 15], register [word 2: 12-14]
  228. %S - float source type code [word 1: 10-12]
  229. %U - register [word 2: 6-8]
  230. %Z - ATC level number [word 1: 10-12]
  231. %1 - Special case: EA as second operand
  232. */
  233. /* Operand classes */
  234. enum {
  235. EAPI = 1, /* extended address: pre decrement only */
  236. EACA, /* extended address: control alterable */
  237. EACAD, /* extended address: control alterable or Dreg */
  238. EACAPI, /* extended address: control alterable or post-incr */
  239. EACAPD, /* extended address: control alterable or pre-decr */
  240. EAMA, /* extended address: memory alterable */
  241. EADA, /* extended address: data alterable */
  242. EAA, /* extended address: alterable */
  243. EAC, /* extended address: control addressing */
  244. EACPI, /* extended address: control addressing or post-incr */
  245. EACD, /* extended address: control addressing or Dreg */
  246. EAD, /* extended address: data addressing */
  247. EAM, /* extended address: memory addressing */
  248. EAM_B, /* EAM with byte immediate data */
  249. EADI, /* extended address: data addressing or immediate */
  250. EADI_L, /* EADI with long immediate data */
  251. EADI_W, /* EADI with word immediate data */
  252. EAALL, /* extended address: all modes */
  253. EAALL_L, /* EAALL with long immediate data */
  254. EAALL_W, /* EAALL with word immediate data */
  255. EAALL_B, /* EAALL with byte immediate date */
  256. /* special codes not directly used for validation */
  257. EAFLT, /* extended address: EADI for B, W, L, or S; else EAM */
  258. EADDA, /* destination extended address: EADA */
  259. BREAC, /* EAC operand for JMP or CALL */
  260. OP8, /* low 8 bits of op word */
  261. I8, /* low 8-bits of first extension word */
  262. I16, /* 16 bits in first extension word */
  263. I32, /* 32 bits in first and second extension words */
  264. IV, /* 8, 16 or 32 bit data in first & 2nd extension words */
  265. C16, /* CAS2 16 bit immediate with bits 9-11 & 3-5 zero */
  266. BR8, /* 8 bits in op word or 16 or 32 bits in extension words
  267. branch instruction format (p. 2-25) */
  268. BR16, /* 16-bit branch displacement */
  269. BR32, /* 32-bit branch displacement */
  270. STACK, /* return PC on stack - follow set only */
  271. };
  272. /* validation bit masks for various EA classes */
  273. enum {
  274. Dn = 0x0001, /* Data register */
  275. An = 0x0002, /* Address register */
  276. Ind = 0x0004, /* Address register indirect */
  277. Pinc = 0x0008, /* Address register indirect post-increment */
  278. Pdec = 0x0010, /* Address register indirect pre-decrement */
  279. Bdisp = 0x0020, /* Base/Displacement in all its forms */
  280. PCrel = 0x0040, /* PC relative addressing in all its forms */
  281. Imm = 0x0080, /* Immediate data */
  282. Abs = 0x0100, /* Absolute */
  283. };
  284. /* EA validation table indexed by operand class number */
  285. static short validea[] =
  286. {
  287. 0, /* none */
  288. Pdec, /* EAPI */
  289. Abs|Bdisp|Ind, /* EACA */
  290. Abs|Bdisp|Ind|Dn, /* EACAD */
  291. Abs|Bdisp|Pinc|Ind, /* EACAPI */
  292. Abs|Bdisp|Pdec|Ind, /* EACAPD */
  293. Abs|Bdisp|Pdec|Pinc|Ind, /* EAMA */
  294. Abs|Bdisp|Pdec|Pinc|Ind|Dn, /* EADA */
  295. Abs|Bdisp|Pdec|Pinc|Ind|An|Dn, /* EAA */
  296. Abs|PCrel|Bdisp|Ind, /* EAC */
  297. Abs|PCrel|Bdisp|Pinc|Ind, /* EACPI */
  298. Abs|PCrel|Bdisp|Ind|Dn, /* EACD */
  299. Abs|PCrel|Bdisp|Pdec|Pinc|Ind|Dn, /* EAD */
  300. Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind, /* EAM */
  301. Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind, /* EAM_B */
  302. Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind|Dn, /* EADI */
  303. Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind|Dn, /* EADI_L */
  304. Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind|Dn, /* EADI_W */
  305. Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind|An|Dn, /* EAALL */
  306. Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind|An|Dn, /* EAALL_L */
  307. Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind|An|Dn, /* EAALL_W */
  308. Abs|Imm|PCrel|Bdisp|Pdec|Pinc|Ind|An|Dn, /* EAALL_B */
  309. };
  310. /* EA types */
  311. enum
  312. {
  313. Dreg, /* Dn */
  314. Areg, /* An */
  315. AInd, /* (An) */
  316. APdec, /* -(An) */
  317. APinc, /* (An)+ */
  318. ADisp, /* Displacement beyond (An) */
  319. BXD, /* Base, Index, Displacement */
  320. PDisp, /* Displacement beyond PC */
  321. PXD, /* PC, Index, Displacement */
  322. ABS, /* absolute */
  323. IMM, /* immediate */
  324. IREAL, /* single precision real immediate */
  325. IEXT, /* extended precision real immediate */
  326. IPACK, /* packed real immediate */
  327. IDBL, /* double precision real immediate */
  328. };
  329. typedef struct optable Optable;
  330. typedef struct operand Operand;
  331. typedef struct inst Inst;
  332. struct optable
  333. {
  334. ushort opcode;
  335. ushort mask0;
  336. ushort op2;
  337. ushort mask1;
  338. char opdata[2];
  339. char *format;
  340. };
  341. struct operand
  342. {
  343. int eatype;
  344. short ext;
  345. union {
  346. long immediate; /* sign-extended integer byte/word/long */
  347. struct { /* index mode displacements */
  348. long disp;
  349. long outer;
  350. };
  351. char floater[24]; /* floating point immediates */
  352. };
  353. };
  354. struct inst
  355. {
  356. int n; /* # bytes in instruction */
  357. uvlong addr; /* addr of start of instruction */
  358. ushort raw[4+12]; /* longest instruction: 24 byte packed immediate */
  359. Operand and[2];
  360. char *end; /* end of print buffer */
  361. char *curr; /* current fill point in buffer */
  362. char *errmsg;
  363. };
  364. /* class 0: bit field, MOVEP & immediate instructions */
  365. static Optable t0[] = {
  366. { 0x003c, 0xffff, 0x0000, 0xff00, {I8}, "ORB %i,CCR" },
  367. { 0x007c, 0xffff, 0x0000, 0x0000, {I16}, "ORW %i,SR" },
  368. { 0x023c, 0xffff, 0x0000, 0xff00, {I8}, "ANDB %i,CCR" },
  369. { 0x027c, 0xffff, 0x0000, 0x0000, {I16}, "ANDW %i,SR" },
  370. { 0x0a3c, 0xffff, 0x0000, 0xff00, {I8}, "EORB %i,CCR" },
  371. { 0x0a7c, 0xffff, 0x0000, 0x0000, {I16}, "EORW %i,SR" },
  372. { 0x0cfc, 0xffff, 0x0000, 0x0000, {C16,C16}, "CAS2W R%a:R%A,R%u:R%U,(%r):(%R)"} ,
  373. { 0x0efc, 0xffff, 0x0000, 0x0000, {C16,C16}, "CAS2L R%a:R%A,R%u:R%U,(%r):(%R)"} ,
  374. { 0x06c0, 0xfff8, 0x0000, 0x0000, {0}, "RTM R%y" },
  375. { 0x06c8, 0xfff8, 0x0000, 0x0000, {0}, "RTM A%y" },
  376. { 0x0800, 0xfff8, 0x0000, 0x0000, {I16}, "BTSTL %i,R%y" },
  377. { 0x0840, 0xfff8, 0x0000, 0x0000, {I16}, "BCHGL %i,R%y" },
  378. { 0x0880, 0xfff8, 0x0000, 0x0000, {I16}, "BCLRL %i,R%y" },
  379. { 0x00c0, 0xffc0, 0x0000, 0x0fff, {EAC}, "CMP2B %e,%r" },
  380. { 0x00c0, 0xffc0, 0x0800, 0x0fff, {EAC}, "CHK2B %e,%r" },
  381. { 0x02c0, 0xffc0, 0x0000, 0x0fff, {EAC}, "CMP2W %e,%r" },
  382. { 0x02c0, 0xffc0, 0x0800, 0x0fff, {EAC}, "CHK2W %e,%r" },
  383. { 0x04c0, 0xffc0, 0x0000, 0x0fff, {EAC}, "CMP2L %e,%r" },
  384. { 0x04c0, 0xffc0, 0x0800, 0x0fff, {EAC}, "CHK2L %e,%r" },
  385. { 0x06c0, 0xffc0, 0x0000, 0x0000, {I16, BREAC}, "CALLM %i,%e" },
  386. { 0x0800, 0xffc0, 0x0000, 0x0000, {I16, EAD}, "BTSTB %i,%e" },
  387. { 0x0840, 0xffc0, 0x0000, 0x0000, {I16, EADA}, "BCHG %i,%e" },
  388. { 0x0880, 0xffc0, 0x0000, 0x0000, {I16, EADA}, "BCLR %i,%e" },
  389. { 0x08c0, 0xffc0, 0x0000, 0x0000, {I16, EADA}, "BSET %i,%e" },
  390. { 0x0ac0, 0xffc0, 0x0000, 0xfe38, {EAMA}, "CASB R%a,R%u,%e" },
  391. { 0x0cc0, 0xffc0, 0x0000, 0xfe38, {EAMA}, "CASW R%a,R%u,%e" },
  392. { 0x0ec0, 0xffc0, 0x0000, 0xfe38, {EAMA}, "CASL R%a,R%u,%e" },
  393. { 0x0000, 0xff00, 0x0000, 0x0000, {IV, EADA}, "OR%s %i,%e" },
  394. { 0x0200, 0xff00, 0x0000, 0x0000, {IV, EADA}, "AND%s %i,%e" },
  395. { 0x0400, 0xff00, 0x0000, 0x0000, {IV, EADA}, "SUB%s %i,%e" },
  396. { 0x0600, 0xff00, 0x0000, 0x0000, {IV, EADA}, "ADD%s %i,%e" },
  397. { 0x0a00, 0xff00, 0x0000, 0x0000, {IV, EADA}, "EOR%s %i,%e" },
  398. { 0x0c00, 0xff00, 0x0000, 0x0000, {IV, EAD}, "CMP%s %i,%e" },
  399. { 0x0e00, 0xff00, 0x0000, 0x0800, {EAMA}, "MOVES%s %e,%r" },
  400. { 0x0e00, 0xff00, 0x0800, 0x0800, {EAMA}, "MOVES%s %r,%e" },
  401. { 0x0108, 0xf1f8, 0x0000, 0x0000, {I16}, "MOVEPW (%i,A%y),R%x" },
  402. { 0x0148, 0xf1f8, 0x0000, 0x0000, {I16}, "MOVEPL (%i,A%y),R%x" },
  403. { 0x0188, 0xf1f8, 0x0000, 0x0000, {I16}, "MOVEPW R%x,(%i,A%y)" },
  404. { 0x01c8, 0xf1f8, 0x0000, 0x0000, {I16}, "MOVEPL R%x,(%i,A%y)" },
  405. { 0x0100, 0xf1f8, 0x0000, 0x0000, {0}, "BTSTL R%x,R%y" },
  406. { 0x0140, 0xf1f8, 0x0000, 0x0000, {0}, "BCHGL R%x,R%y" },
  407. { 0x0180, 0xf1f8, 0x0000, 0x0000, {0}, "BCLRL R%x,R%y" },
  408. { 0x01c0, 0xf1f8, 0x0000, 0x0000, {0}, "BSET R%x,R%y" },
  409. { 0x0100, 0xf1c0, 0x0000, 0x0000, {EAM_B}, "BTSTB R%x,%e" },
  410. { 0x0140, 0xf1c0, 0x0000, 0x0000, {EAMA}, "BCHG R%x,%e" },
  411. { 0x0180, 0xf1c0, 0x0000, 0x0000, {EAMA}, "BCLR R%x,%e" },
  412. { 0x01c0, 0xf1c0, 0x0000, 0x0000, {EAMA}, "BSET R%x,%e" },
  413. { 0,0,0,0,{0},0 },
  414. };
  415. /* class 1: move byte */
  416. static Optable t1[] = {
  417. { 0x1000, 0xf000, 0x0000, 0x0000, {EAALL_B,EADDA},"MOVB %e,%E" },
  418. { 0,0,0,0,{0},0 },
  419. };
  420. /* class 2: move long */
  421. static Optable t2[] = {
  422. { 0x2040, 0xf1c0, 0x0000, 0x0000, {EAALL_L}, "MOVL %e,A%x" },
  423. { 0x2000, 0xf000, 0x0000, 0x0000, {EAALL_L,EADDA},"MOVL %e,%E" },
  424. { 0,0,0,0,{0},0 },
  425. };
  426. /* class 3: move word */
  427. static Optable t3[] = {
  428. { 0x3040, 0xf1c0, 0x0000, 0x0000, {EAALL_W}, "MOVW %e,A%x" },
  429. { 0x3000, 0xf000, 0x0000, 0x0000, {EAALL_W,EADDA},"MOVW %e,%E" },
  430. { 0,0,0,0,{0},0 },
  431. };
  432. /* class 4: miscellaneous */
  433. static Optable t4[] = {
  434. { 0x4e75, 0xffff, 0x0000, 0x0000, {STACK}, "RTS" },
  435. { 0x4e77, 0xffff, 0x0000, 0x0000, {STACK}, "RTR" },
  436. { 0x4afc, 0xffff, 0x0000, 0x0000, {0}, "ILLEGAL" },
  437. { 0x4e71, 0xffff, 0x0000, 0x0000, {0}, "NOP" },
  438. { 0x4e74, 0xffff, 0x0000, 0x0000, {I16, STACK}, "RTD %i" },
  439. { 0x4e76, 0xffff, 0x0000, 0x0000, {0}, "TRAPV" },
  440. { 0x4e70, 0xffff, 0x0000, 0x0000, {0}, "RESET" },
  441. { 0x4e72, 0xffff, 0x0000, 0x0000, {I16}, "STOP %i" },
  442. { 0x4e73, 0xffff, 0x0000, 0x0000, {0}, "RTE" },
  443. { 0x4e7a, 0xffff, 0x0000, 0x0000, {I16}, "MOVEL %N,%r" },
  444. { 0x4e7b, 0xffff, 0x0000, 0x0000, {I16}, "MOVEL %r,%N" },
  445. { 0x4808, 0xfff8, 0x0000, 0x0000, {I32}, "LINKL A%y,%i" },
  446. { 0x4840, 0xfff8, 0x0000, 0x0000, {0}, "SWAPW R%y" },
  447. { 0x4848, 0xfff8, 0x0000, 0x0000, {0}, "BKPT #%y" },
  448. { 0x4880, 0xfff8, 0x0000, 0x0000, {0}, "EXTW R%y" },
  449. { 0x48C0, 0xfff8, 0x0000, 0x0000, {0}, "EXTL R%y" },
  450. { 0x49C0, 0xfff8, 0x0000, 0x0000, {0}, "EXTBL R%y" },
  451. { 0x4e50, 0xfff8, 0x0000, 0x0000, {I16}, "LINKW A%y,%i" },
  452. { 0x4e58, 0xfff8, 0x0000, 0x0000, {0}, "UNLK A%y" },
  453. { 0x4e60, 0xfff8, 0x0000, 0x0000, {0}, "MOVEL (A%y),USP" },
  454. { 0x4e68, 0xfff8, 0x0000, 0x0000, {0}, "MOVEL USP,(A%y)" },
  455. { 0x4e40, 0xfff0, 0x0000, 0x0000, {0}, "SYS %f" },
  456. { 0x40c0, 0xffc0, 0x0000, 0x0000, {EADA}, "MOVW SR,%e" },
  457. { 0x42c0, 0xffc0, 0x0000, 0x0000, {EADA}, "MOVW CCR,%e" },
  458. { 0x44c0, 0xffc0, 0x0000, 0x0000, {EADI_W}, "MOVW %e,CCR" },
  459. { 0x46c0, 0xffc0, 0x0000, 0x0000, {EADI_W}, "MOVW %e,SR" },
  460. { 0x4800, 0xffc0, 0x0000, 0x0000, {EADA}, "NBCDB %e" },
  461. { 0x4840, 0xffc0, 0x0000, 0x0000, {EAC}, "PEA %e" },
  462. { 0x4880, 0xffc0, 0x0000, 0x0000, {I16, EACAPD},"MOVEMW %i,%e" },
  463. { 0x48c0, 0xffc0, 0x0000, 0x0000, {I16, EACAPD},"MOVEML %i,%e" },
  464. { 0x4ac0, 0xffc0, 0x0000, 0x0000, {EADA}, "TAS %e" },
  465. { 0x4a00, 0xffc0, 0x0000, 0x0000, {EAD}, "TSTB %e" },
  466. { 0x4c00, 0xffc0, 0x0000, 0x8ff8, {EADI_L}, "MULUL %e,%r" },
  467. { 0x4c00, 0xffc0, 0x0400, 0x8ff8, {EADI_L}, "MULUL %e,R%a:%r" },
  468. { 0x4c00, 0xffc0, 0x0800, 0x8ff8, {EADI_L}, "MULSL %e,%r" },
  469. { 0x4c00, 0xffc0, 0x0c00, 0x8ff8, {EADI_L}, "MULSL %e,R%a:%r" },
  470. { 0x4c40, 0xffc0, 0x0000, 0x8ff8, {EADI_L}, "DIVUL %e,%j" },
  471. { 0x4c40, 0xffc0, 0x0400, 0x8ff8, {EADI_L}, "DIVUD %e,%r:R%a" },
  472. { 0x4c40, 0xffc0, 0x0800, 0x8ff8, {EADI_L}, "DIVSL %e,%j" },
  473. { 0x4c40, 0xffc0, 0x0c00, 0x8ff8, {EADI_L}, "DIVSD %e,%r:R%a" },
  474. { 0x4c80, 0xffc0, 0x0000, 0x0000, {I16, EACPI}, "MOVEMW %1,%i" },
  475. { 0x4cc0, 0xffc0, 0x0000, 0x0000, {I16, EACPI}, "MOVEML %1,%i" },
  476. { 0x4e80, 0xffc0, 0x0000, 0x0000, {BREAC}, "JSR %e" },
  477. { 0x4ec0, 0xffc0, 0x0000, 0x0000, {BREAC}, "JMP %e" },
  478. { 0x4000, 0xff00, 0x0000, 0x0000, {EADA}, "NEGX%s %e" },
  479. { 0x4200, 0xff00, 0x0000, 0x0000, {EADA}, "CLR%s %e" },
  480. { 0x4400, 0xff00, 0x0000, 0x0000, {EADA}, "NEG%s %e" },
  481. { 0x4600, 0xff00, 0x0000, 0x0000, {EADA}, "NOT%s %e" },
  482. { 0x4a00, 0xff00, 0x0000, 0x0000, {EAALL}, "TST%s %e" },
  483. { 0x4180, 0xf1c0, 0x0000, 0x0000, {EADI_W}, "CHKW %e,R%x" },
  484. { 0x41c0, 0xf1c0, 0x0000, 0x0000, {EAC}, "LEA %e,A%x" },
  485. { 0x4100, 0xf1c0, 0x0000, 0x0000, {EADI_L}, "CHKL %e,R%x" },
  486. { 0,0,0,0,{0},0 },
  487. };
  488. /* class 5: miscellaneous quick, branch & trap instructions */
  489. static Optable t5[] = {
  490. { 0x5000, 0xf1c0, 0x0000, 0x0000, {EADA}, "ADDB $Q#%q,%e" },
  491. { 0x5100, 0xf1c0, 0x0000, 0x0000, {EADA}, "SUBB $Q#%q,%e" },
  492. { 0x50c8, 0xf1f8, 0x0000, 0x0000, {BR16}, "DB%c R%y,%t" },
  493. { 0x51c8, 0xf1f8, 0x0000, 0x0000, {BR16}, "DB%c R%y,%t" },
  494. { 0x5000, 0xf1c0, 0x0000, 0x0000, {EAA}, "ADDB $Q#%q,%e" },
  495. { 0x5040, 0xf1c0, 0x0000, 0x0000, {EAA}, "ADDW $Q#%q,%e" },
  496. { 0x5080, 0xf1c0, 0x0000, 0x0000, {EAA}, "ADDL $Q#%q,%e" },
  497. { 0x5100, 0xf1c0, 0x0000, 0x0000, {EAA}, "SUBB $Q#%q,%e" },
  498. { 0x5140, 0xf1c0, 0x0000, 0x0000, {EAA}, "SUBW $Q#%q,%e" },
  499. { 0x5180, 0xf1c0, 0x0000, 0x0000, {EAA}, "SUBL $Q#%q,%e" },
  500. { 0x50fa, 0xf0ff, 0x0000, 0x0000, {I16}, "TRAP%cW %i" },
  501. { 0x50fb, 0xf0ff, 0x0000, 0x0000, {I32}, "TRAP%cL %i" },
  502. { 0x50fc, 0xf0ff, 0x0000, 0x0000, {0}, "TRAP%c" },
  503. { 0x50c0, 0xf0c0, 0x0000, 0x0000, {EADA}, "S%c %e" },
  504. { 0,0,0,0,{0},0 },
  505. };
  506. /* class 6: branch instructions */
  507. static Optable t6[] = {
  508. { 0x6000, 0xff00, 0x0000, 0x0000, {BR8}, "BRA %t" },
  509. { 0x6100, 0xff00, 0x0000, 0x0000, {BR8}, "BSR %t" },
  510. { 0x6000, 0xf000, 0x0000, 0x0000, {BR8}, "B%c %t" },
  511. { 0,0,0,0,{0},0 },
  512. };
  513. /* class 7: move quick */
  514. static Optable t7[] = {
  515. { 0x7000, 0xf100, 0x0000, 0x0000, {OP8}, "MOVL $Q%i,R%x" },
  516. { 0,0,0,0,{0},0 },
  517. };
  518. /* class 8: BCD operations, DIV, and OR instructions */
  519. static Optable t8[] = {
  520. { 0x8100, 0xf1f8, 0x0000, 0x0000, {0}, "SBCDB R%y,R%x" },
  521. { 0x8108, 0xf1f8, 0x0000, 0x0000, {0}, "SBCDB -(A%y),-(A%x)" },
  522. { 0x8140, 0xf1f8, 0x0000, 0x0000, {I16}, "PACK R%y,R%x,%i" },
  523. { 0x8148, 0xf1f8, 0x0000, 0x0000, {I16}, "PACK -(A%y),-(A%x),%i" },
  524. { 0x8180, 0xf1f8, 0x0000, 0x0000, {I16}, "UNPK R%y,R%x,%i" },
  525. { 0x8188, 0xf1f8, 0x0000, 0x0000, {I16}, "UNPK -(A%y),-(A%x),%i" },
  526. { 0x80c0, 0xf1c0, 0x0000, 0x0000, {EADI_W}, "DIVUW %e,R%x" },
  527. { 0x81c0, 0xf1c0, 0x0000, 0x0000, {EADI_W}, "DIVSW %e,R%x" },
  528. { 0x8000, 0xf100, 0x0000, 0x0000, {EADI}, "OR%s %e,R%x" },
  529. { 0x8100, 0xf100, 0x0000, 0x0000, {EAMA}, "OR%s R%x,%e" },
  530. { 0,0,0,0,{0},0 },
  531. };
  532. /* class 9: subtract instruction */
  533. static Optable t9[] = {
  534. { 0x90c0, 0xf1c0, 0x0000, 0x0000, {EAALL_W}, "SUBW %e,A%x" },
  535. { 0x91c0, 0xf1c0, 0x0000, 0x0000, {EAALL_L}, "SUBL %e,A%x" },
  536. { 0x9100, 0xf138, 0x0000, 0x0000, {0}, "SUBX%s R%y,R%x" },
  537. { 0x9108, 0xf138, 0x0000, 0x0000, {0}, "SUBX%s -(A%y),-(A%x)" },
  538. { 0x9000, 0xf100, 0x0000, 0x0000, {EAALL}, "SUB%s %e,R%x" },
  539. { 0x9100, 0xf100, 0x0000, 0x0000, {EAMA}, "SUB%s R%x,%e" },
  540. { 0,0,0,0,{0},0 },
  541. };
  542. /* class b: CMP & EOR */
  543. static Optable tb[] = {
  544. { 0xb000, 0xf1c0, 0x0000, 0x0000, {EADI}, "CMPB R%x,%e" },
  545. { 0xb040, 0xf1c0, 0x0000, 0x0000, {EAALL_W}, "CMPW R%x,%e" },
  546. { 0xb080, 0xf1c0, 0x0000, 0x0000, {EAALL_L}, "CMPL R%x,%e" },
  547. { 0xb0c0, 0xf1c0, 0x0000, 0x0000, {EAALL_W}, "CMPW A%x,%e" },
  548. { 0xb1c0, 0xf1c0, 0x0000, 0x0000, {EAALL_L}, "CMPL A%x,%e" },
  549. { 0xb108, 0xf138, 0x0000, 0x0000, {0}, "CMP%s (A%y)+,(A%x)+" },
  550. { 0xb100, 0xf100, 0x0000, 0x0000, {EADA}, "EOR%s %e,R%x" },
  551. { 0,0,0,0,{0},0 },
  552. };
  553. /* class c: AND, MUL, BCD & Exchange */
  554. static Optable tc[] = {
  555. { 0xc100, 0xf1f8, 0x0000, 0x0000, {0}, "ABCDB R%y,R%x" },
  556. { 0xc108, 0xf1f8, 0x0000, 0x0000, {0}, "ABCDB -(A%y),-(A%x)" },
  557. { 0xc140, 0xf1f8, 0x0000, 0x0000, {0}, "EXG R%x,R%y" },
  558. { 0xc148, 0xf1f8, 0x0000, 0x0000, {0}, "EXG A%x,A%y" },
  559. { 0xc188, 0xf1f8, 0x0000, 0x0000, {0}, "EXG R%x,A%y" },
  560. { 0xc0c0, 0xf1c0, 0x0000, 0x0000, {EADI_W}, "MULUW %e,R%x" },
  561. { 0xc1c0, 0xf1c0, 0x0000, 0x0000, {EADI_W}, "MULSW %e,R%x" },
  562. { 0xc000, 0xf100, 0x0000, 0x0000, {EADI}, "AND%s %e,R%x" },
  563. { 0xc100, 0xf100, 0x0000, 0x0000, {EAMA}, "AND%s R%x,%e" },
  564. { 0,0,0,0,{0},0 },
  565. };
  566. /* class d: addition */
  567. static Optable td[] = {
  568. { 0xd000, 0xf1c0, 0x0000, 0x0000, {EADI}, "ADDB %e,R%x" },
  569. { 0xd0c0, 0xf1c0, 0x0000, 0x0000, {EAALL_W}, "ADDW %e,A%x" },
  570. { 0xd1c0, 0xf1c0, 0x0000, 0x0000, {EAALL_L}, "ADDL %e,A%x" },
  571. { 0xd100, 0xf138, 0x0000, 0x0000, {0}, "ADDX%s R%y,R%x" },
  572. { 0xd108, 0xf138, 0x0000, 0x0000, {0}, "ADDX%s -(A%y),-(A%x)" },
  573. { 0xd000, 0xf100, 0x0000, 0x0000, {EAALL}, "ADD%s %e,R%x" },
  574. { 0xd100, 0xf100, 0x0000, 0x0000, {EAMA}, "ADD%s R%x,%e" },
  575. { 0,0,0,0,{0},0 },
  576. };
  577. /* class e: shift, rotate, bit field operations */
  578. static Optable te[] = {
  579. { 0xe8c0, 0xffc0, 0x0820, 0xfe38, {EACD}, "BFTST %e{R%u:R%a}" },
  580. { 0xe8c0, 0xffc0, 0x0800, 0xfe20, {EACD}, "BFTST %e{R%u:%w}" },
  581. { 0xe8c0, 0xffc0, 0x0020, 0xf838, {EACD}, "BFTST %e{%o:R%a}" },
  582. { 0xe8c0, 0xffc0, 0x0000, 0xf820, {EACD}, "BFTST %e{%o:%w}" },
  583. { 0xe9c0, 0xffc0, 0x0820, 0x8e38, {EACD}, "BFEXTU %e{R%u:R%a},%r" },
  584. { 0xe9c0, 0xffc0, 0x0800, 0x8e20, {EACD}, "BFEXTU %e{R%u:%w},%r" },
  585. { 0xe9c0, 0xffc0, 0x0020, 0x8838, {EACD}, "BFEXTU %e{%o:R%a},%r" },
  586. { 0xe9c0, 0xffc0, 0x0000, 0x8820, {EACD}, "BFEXTU %e{%o:%w},%r" },
  587. { 0xeac0, 0xffc0, 0x0820, 0xfe38, {EACAD}, "BFCHG %e{R%u:R%a}" },
  588. { 0xeac0, 0xffc0, 0x0800, 0xfe20, {EACAD}, "BFCHG %e{R%u:%w}" },
  589. { 0xeac0, 0xffc0, 0x0020, 0xf838, {EACAD}, "BFCHG %e{%o:R%a}" },
  590. { 0xeac0, 0xffc0, 0x0000, 0xf820, {EACAD}, "BFCHG %e{%o:%w}" },
  591. { 0xebc0, 0xffc0, 0x0820, 0x8e38, {EACD}, "BFEXTS %e{R%u:R%a},%r" },
  592. { 0xebc0, 0xffc0, 0x0800, 0x8e20, {EACD}, "BFEXTS %e{R%u:%w},%r" },
  593. { 0xebc0, 0xffc0, 0x0020, 0x8838, {EACD}, "BFEXTS %e{%o:R%a},%r" },
  594. { 0xebc0, 0xffc0, 0x0000, 0x8820, {EACD}, "BFEXTS %e{%o:%w},%r" },
  595. { 0xecc0, 0xffc0, 0x0820, 0xfe38, {EACAD}, "BFCLR %e{R%u:R%a}" },
  596. { 0xecc0, 0xffc0, 0x0800, 0xfe20, {EACAD}, "BFCLR %e{R%u:%w}" },
  597. { 0xecc0, 0xffc0, 0x0020, 0xf838, {EACAD}, "BFCLR %e{%o:R%a}" },
  598. { 0xecc0, 0xffc0, 0x0000, 0xf820, {EACAD}, "BFCLR %e{%o:%w}" },
  599. { 0xedc0, 0xffc0, 0x0820, 0x8e38, {EACAD}, "BFFFO %e{R%u:R%a},%r" },
  600. { 0xedc0, 0xffc0, 0x0800, 0x8e20, {EACAD}, "BFFFO %e{R%u:%w},%r" },
  601. { 0xedc0, 0xffc0, 0x0020, 0x8838, {EACAD}, "BFFFO %e{%o:R%a},%r" },
  602. { 0xedc0, 0xffc0, 0x0000, 0x8820, {EACAD}, "BFFFO %e{%o:%w},%r" },
  603. { 0xeec0, 0xffc0, 0x0820, 0xfe38, {EACAD}, "BFSET %e{R%u:R%a}" },
  604. { 0xeec0, 0xffc0, 0x0800, 0xfe20, {EACAD}, "BFSET %e{R%u:%w}" },
  605. { 0xeec0, 0xffc0, 0x0020, 0xf838, {EACAD}, "BFSET %e{%o:R%a}" },
  606. { 0xeec0, 0xffc0, 0x0000, 0xf820, {EACAD}, "BFSET %e{%o:%w}" },
  607. { 0xefc0, 0xffc0, 0x0820, 0x8e38, {EACAD}, "BFINS %r,%e{R%u:R%a}" },
  608. { 0xefc0, 0xffc0, 0x0800, 0x8e20, {EACAD}, "BFINS %r,%e{R%u:%w}" },
  609. { 0xefc0, 0xffc0, 0x0020, 0x8838, {EACAD}, "BFINS %r,%e{%o:R%a}" },
  610. { 0xefc0, 0xffc0, 0x0000, 0x8820, {EACAD}, "BFINS %r,%e{%o:%w}" },
  611. { 0xe0c0, 0xfec0, 0x0000, 0x0000, {EAMA}, "AS%dW %e" },
  612. { 0xe2c0, 0xfec0, 0x0000, 0x0000, {EAMA}, "LS%dW %e" },
  613. { 0xe4c0, 0xfec0, 0x0000, 0x0000, {EAMA}, "ROX%dW %e" },
  614. { 0xe6c0, 0xfec0, 0x0000, 0x0000, {EAMA}, "RO%dW %e" },
  615. { 0xe000, 0xf038, 0x0000, 0x0000, {0}, "AS%d%s #%q,R%y" },
  616. { 0xe008, 0xf038, 0x0000, 0x0000, {0}, "LS%d%s #%q,R%y" },
  617. { 0xe010, 0xf038, 0x0000, 0x0000, {0}, "ROX%d%s #%q,R%y" },
  618. { 0xe018, 0xf038, 0x0000, 0x0000, {0}, "RO%d%s #%q,R%y" },
  619. { 0xe020, 0xf038, 0x0000, 0x0000, {0}, "AS%d%s R%x,R%y" },
  620. { 0xe028, 0xf038, 0x0000, 0x0000, {0}, "LS%d%s R%x,R%y" },
  621. { 0xe030, 0xf038, 0x0000, 0x0000, {0}, "ROX%d%s R%x,R%y" },
  622. { 0xe038, 0xf038, 0x0000, 0x0000, {0}, "RO%d%s R%x,R%y" },
  623. { 0,0,0,0,{0},0 },
  624. };
  625. /* class f: coprocessor and mmu instructions */
  626. static Optable tf[] = {
  627. { 0xf280, 0xffff, 0x0000, 0xffff, {0}, "FNOP" },
  628. { 0xf200, 0xffff, 0x5c00, 0xfc00, {0}, "FMOVECRX %k,F%D" },
  629. { 0xf27a, 0xffff, 0x0000, 0xffc0, {I16}, "FTRAP%P %i" },
  630. { 0xf27b, 0xffff, 0x0000, 0xffc0, {I32}, "FTRAP%P %i" },
  631. { 0xf27c, 0xffff, 0x0000, 0xffc0, {0}, "FTRAP%P" },
  632. { 0xf248, 0xfff8, 0x0000, 0xffc0, {BR16}, "FDB%P R%y,%t" },
  633. { 0xf620, 0xfff8, 0x8000, 0x8fff, {0}, "MOVE16 (A%y)+,(%r)+" },
  634. { 0xf500, 0xfff8, 0x0000, 0x0000, {0}, "PFLUSHN (A%y)" },
  635. { 0xf508, 0xfff8, 0x0000, 0x0000, {0}, "PFLUSH (A%y)" },
  636. { 0xf510, 0xfff8, 0x0000, 0x0000, {0}, "PFLUSHAN" },
  637. { 0xf518, 0xfff8, 0x0000, 0x0000, {0}, "PFLUSHA" },
  638. { 0xf548, 0xfff8, 0x0000, 0x0000, {0}, "PTESTW (A%y)" },
  639. { 0xf568, 0xfff8, 0x0000, 0x0000, {0}, "PTESTR (A%y)" },
  640. { 0xf600, 0xfff8, 0x0000, 0x0000, {I32}, "MOVE16 (A%y)+,$%i" },
  641. { 0xf608, 0xfff8, 0x0000, 0x0000, {I32}, "MOVE16 $%i,(A%y)-" },
  642. { 0xf610, 0xfff8, 0x0000, 0x0000, {I32}, "MOVE16 (A%y),$%i" },
  643. { 0xf618, 0xfff8, 0x0000, 0x0000, {I32}, "MOVE16 $%i,(A%y)" },
  644. { 0xf000, 0xffc0, 0x0800, 0xffff, {EACA}, "PMOVE %e,TT0" },
  645. { 0xf000, 0xffc0, 0x0900, 0xffff, {EACA}, "PMOVEFD %e,TT0" },
  646. { 0xf000, 0xffc0, 0x0a00, 0xffff, {EACA}, "PMOVE TT0,%e" },
  647. { 0xf000, 0xffc0, 0x0b00, 0xffff, {EACA}, "PMOVEFD TT0,%e" },
  648. { 0xf000, 0xffc0, 0x0c00, 0xffff, {EACA}, "PMOVE %e,TT1" },
  649. { 0xf000, 0xffc0, 0x0d00, 0xffff, {EACA}, "PMOVEFD %e,TT1" },
  650. { 0xf000, 0xffc0, 0x0e00, 0xffff, {EACA}, "PMOVE TT1,%e" },
  651. { 0xf000, 0xffc0, 0x0f00, 0xffff, {EACA}, "PMOVEFD TT1,%e" },
  652. { 0xf000, 0xffc0, 0x2400, 0xffff, {0}, "PFLUSHA" },
  653. { 0xf000, 0xffc0, 0x2800, 0xffff, {EACA}, "PVALID VAL,%e" },
  654. { 0xf000, 0xffc0, 0x6000, 0xffff, {EACA}, "PMOVE %e,MMUSR" },
  655. { 0xf000, 0xffc0, 0x6200, 0xffff, {EACA}, "PMOVE MMUSR,%e" },
  656. { 0xf000, 0xffc0, 0x2800, 0xfff8, {EACA}, "PVALID A%a,%e" },
  657. { 0xf000, 0xffc0, 0x2000, 0xffe0, {EACA}, "PLOADW %L,%e" },
  658. { 0xf000, 0xffc0, 0x2200, 0xffe0, {EACA}, "PLOADR %L,%e" },
  659. { 0xf000, 0xffc0, 0x8000, 0xffe0, {EACA}, "PTESTW %L,%e,#0" },
  660. { 0xf000, 0xffc0, 0x8200, 0xffe0, {EACA}, "PTESTR %L,%e,#0" },
  661. { 0xf000, 0xffc0, 0x3000, 0xfe00, {0}, "PFLUSH %L,#%I" },
  662. { 0xf000, 0xffc0, 0x3800, 0xfe00, {EACA}, "PFLUSH %L,#%I,%e" },
  663. { 0xf000, 0xffc0, 0x8000, 0xe300, {EACA}, "PTESTW %L,%e,#%Z" },
  664. { 0xf000, 0xffc0, 0x8100, 0xe300, {EACA}, "PTESTW %L,%e,#%Z,A%h" },
  665. { 0xf000, 0xffc0, 0x8200, 0xe300, {EACA}, "PTESTR %L,%e,#%Z" },
  666. { 0xf000, 0xffc0, 0x8300, 0xe300, {EACA}, "PTESTR %L,%e,#%Z,A%h" },
  667. { 0xf000, 0xffc0, 0x4000, 0xc3ff, {EACA}, "PMOVE %e,%H" },
  668. { 0xf000, 0xffc0, 0x4100, 0xc3ff, {EACA}, "PMOVEFD %e,%H" },
  669. { 0xf000, 0xffc0, 0x4200, 0xc3ff, {EACA}, "PMOVE %H,%e" },
  670. /* floating point (coprocessor 1)*/
  671. { 0xf200, 0xffc0, 0x8400, 0xffff, {EAALL_L}, "FMOVEL %e,FPIAR" },
  672. { 0xf200, 0xffc0, 0x8800, 0xffff, {EADI_L}, "FMOVEL %e,FPSR" },
  673. { 0xf200, 0xffc0, 0x9000, 0xffff, {EADI_L}, "FMOVEL %e,FPCR" },
  674. { 0xf200, 0xffc0, 0xa400, 0xffff, {EAA}, "FMOVEL FPIAR,%e" },
  675. { 0xf200, 0xffc0, 0xa800, 0xffff, {EADA}, "FMOVEL FPSR,%e" },
  676. { 0xf200, 0xffc0, 0xb000, 0xffff, {EADA}, "FMOVEL FPCR,%e" },
  677. { 0xf240, 0xffc0, 0x0000, 0xffc0, {EADA}, "FS%P %e" },
  678. { 0xf200, 0xffc0, 0xd000, 0xff00, {EACPI}, "FMOVEMX %e,%m" },
  679. { 0xf200, 0xffc0, 0xd800, 0xff00, {EACPI}, "FMOVEMX %e,R%K" },
  680. { 0xf200, 0xffc0, 0xe000, 0xff00, {EAPI}, "FMOVEMX %m,-(A%y)" },
  681. { 0xf200, 0xffc0, 0xe800, 0xff00, {EAPI}, "FMOVEMX R%K,-(A%y)" },
  682. { 0xf200, 0xffc0, 0xf000, 0xff00, {EACAPD}, "FMOVEMX %m,%e" },
  683. { 0xf200, 0xffc0, 0xf800, 0xff00, {EACAPD}, "FMOVEMX R%K,%e" },
  684. { 0xf200, 0xffc0, 0x6800, 0xfc00, {EAMA}, "FMOVEX F%D,%e" },
  685. { 0xf200, 0xffc0, 0x6c00, 0xfc00, {EAMA}, "FMOVEP F%D,%e,{%k}" },
  686. { 0xf200, 0xffc0, 0x7400, 0xfc00, {EAMA}, "FMOVED F%D,%e" },
  687. { 0xf200, 0xffc0, 0x7c00, 0xfc00, {EAMA}, "FMOVEP F%D,%e,{R%K}" },
  688. { 0xf200, 0xffc0, 0x8000, 0xe3ff, {EAM}, "FMOVEML #%B,%e" },
  689. { 0xf200, 0xffc0, 0xa000, 0xe3ff, {EAMA}, "FMOVEML %e,#%B" },
  690. { 0xf200, 0xffc0, 0x0000, 0xe07f, {0}, "FMOVE F%B,F%D" },
  691. { 0xf200, 0xffc0, 0x0001, 0xe07f, {0}, "FINTX %F" },
  692. { 0xf200, 0xffc0, 0x0002, 0xe07f, {0}, "FSINHX %F" },
  693. { 0xf200, 0xffc0, 0x0003, 0xe07f, {0}, "FINTRZ %F" },
  694. { 0xf200, 0xffc0, 0x0004, 0xe07f, {0}, "FSQRTX %F" },
  695. { 0xf200, 0xffc0, 0x0006, 0xe07f, {0}, "FLOGNP1X %F" },
  696. { 0xf200, 0xffc0, 0x0009, 0xe07f, {0}, "FTANHX %F" },
  697. { 0xf200, 0xffc0, 0x000a, 0xe07f, {0}, "FATANX %F" },
  698. { 0xf200, 0xffc0, 0x000c, 0xe07f, {0}, "FASINX %F" },
  699. { 0xf200, 0xffc0, 0x000d, 0xe07f, {0}, "FATANHX %F" },
  700. { 0xf200, 0xffc0, 0x000e, 0xe07f, {0}, "FSINX %F" },
  701. { 0xf200, 0xffc0, 0x000f, 0xe07f, {0}, "FTANX %F" },
  702. { 0xf200, 0xffc0, 0x0010, 0xe07f, {0}, "FETOXX %F" },
  703. { 0xf200, 0xffc0, 0x0011, 0xe07f, {0}, "FTWOTOXX %F" },
  704. { 0xf200, 0xffc0, 0x0012, 0xe07f, {0}, "FTENTOXX %F" },
  705. { 0xf200, 0xffc0, 0x0014, 0xe07f, {0}, "FLOGNX %F" },
  706. { 0xf200, 0xffc0, 0x0015, 0xe07f, {0}, "FLOG10X %F" },
  707. { 0xf200, 0xffc0, 0x0016, 0xe07f, {0}, "FLOG2X %F" },
  708. { 0xf200, 0xffc0, 0x0018, 0xe07f, {0}, "FABSX %F" },
  709. { 0xf200, 0xffc0, 0x0019, 0xe07f, {0}, "FCOSHX %F" },
  710. { 0xf200, 0xffc0, 0x001a, 0xe07f, {0}, "FNEGX %F" },
  711. { 0xf200, 0xffc0, 0x001c, 0xe07f, {0}, "FACOSX %F" },
  712. { 0xf200, 0xffc0, 0x001d, 0xe07f, {0}, "FCOSX %F" },
  713. { 0xf200, 0xffc0, 0x001e, 0xe07f, {0}, "FGETEXPX %F" },
  714. { 0xf200, 0xffc0, 0x001f, 0xe07f, {0}, "FGETMANX %F" },
  715. { 0xf200, 0xffc0, 0x0020, 0xe07f, {0}, "FDIVX F%B,F%D" },
  716. { 0xf200, 0xffc0, 0x0021, 0xe07f, {0}, "FMODX F%B,F%D" },
  717. { 0xf200, 0xffc0, 0x0022, 0xe07f, {0}, "FADDX F%B,F%D" },
  718. { 0xf200, 0xffc0, 0x0023, 0xe07f, {0}, "FMULX F%B,F%D" },
  719. { 0xf200, 0xffc0, 0x0024, 0xe07f, {0}, "FSGLDIVX F%B,F%D" },
  720. { 0xf200, 0xffc0, 0x0025, 0xe07f, {0}, "FREMX F%B,F%D" },
  721. { 0xf200, 0xffc0, 0x0026, 0xe07f, {0}, "FSCALEX F%B,F%D" },
  722. { 0xf200, 0xffc0, 0x0027, 0xe07f, {0}, "FSGLMULX F%B,F%D" },
  723. { 0xf200, 0xffc0, 0x0028, 0xe07f, {0}, "FSUBX F%B,F%D" },
  724. { 0xf200, 0xffc0, 0x0038, 0xe07f, {0}, "FCMPX F%B,F%D" },
  725. { 0xf200, 0xffc0, 0x003a, 0xe07f, {0}, "FTSTX F%B" },
  726. { 0xf200, 0xffc0, 0x0040, 0xe07f, {0}, "FSMOVE F%B,F%D" },
  727. { 0xf200, 0xffc0, 0x0041, 0xe07f, {0}, "FSSQRTX %F"},
  728. { 0xf200, 0xffc0, 0x0044, 0xe07f, {0}, "FDMOVE F%B,F%D" },
  729. { 0xf200, 0xffc0, 0x0045, 0xe07f, {0}, "FDSQRTX %F" },
  730. { 0xf200, 0xffc0, 0x0058, 0xe07f, {0}, "FSABSX %F" },
  731. { 0xf200, 0xffc0, 0x005a, 0xe07f, {0}, "FSNEGX %F" },
  732. { 0xf200, 0xffc0, 0x005c, 0xe07f, {0}, "FDABSX %F" },
  733. { 0xf200, 0xffc0, 0x005e, 0xe07f, {0}, "FDNEGX %F" },
  734. { 0xf200, 0xffc0, 0x0060, 0xe07f, {0}, "FSDIVX F%B,F%D" },
  735. { 0xf200, 0xffc0, 0x0062, 0xe07f, {0}, "FSADDX F%B,F%D" },
  736. { 0xf200, 0xffc0, 0x0063, 0xe07f, {0}, "FSMULX F%B,F%D" },
  737. { 0xf200, 0xffc0, 0x0064, 0xe07f, {0}, "FDDIVX F%B,F%D" },
  738. { 0xf200, 0xffc0, 0x0066, 0xe07f, {0}, "FDADDX F%B,F%D" },
  739. { 0xf200, 0xffc0, 0x0067, 0xe07f, {0}, "FDMULX F%B,F%D" },
  740. { 0xf200, 0xffc0, 0x0068, 0xe07f, {0}, "FSSUBX F%B,F%D" },
  741. { 0xf200, 0xffc0, 0x006c, 0xe07f, {0}, "FDSUBX F%B,F%D" },
  742. { 0xf200, 0xffc0, 0x4000, 0xe07f, {EAFLT}, "FMOVE%S %e,F%D" },
  743. { 0xf200, 0xffc0, 0x4001, 0xe07f, {EAFLT}, "FINT%S %e,F%D" },
  744. { 0xf200, 0xffc0, 0x4002, 0xe07f, {EAFLT}, "FSINH%S %e,F%D" },
  745. { 0xf200, 0xffc0, 0x4003, 0xe07f, {EAFLT}, "FINTRZ%S %e,F%D" },
  746. { 0xf200, 0xffc0, 0x4004, 0xe07f, {EAFLT}, "FSQRT%S %e,F%D" },
  747. { 0xf200, 0xffc0, 0x4006, 0xe07f, {EAFLT}, "FLOGNP1%S %e,F%D" },
  748. { 0xf200, 0xffc0, 0x4009, 0xe07f, {EAFLT}, "FTANH%S %e,F%D" },
  749. { 0xf200, 0xffc0, 0x400a, 0xe07f, {EAFLT}, "FATAN%S %e,F%D" },
  750. { 0xf200, 0xffc0, 0x400c, 0xe07f, {EAFLT}, "FASIN%S %e,F%D" },
  751. { 0xf200, 0xffc0, 0x400d, 0xe07f, {EAFLT}, "FATANH%S %e,F%D" },
  752. { 0xf200, 0xffc0, 0x400e, 0xe07f, {EAFLT}, "FSIN%S %e,F%D" },
  753. { 0xf200, 0xffc0, 0x400f, 0xe07f, {EAFLT}, "FTAN%S %e,F%D" },
  754. { 0xf200, 0xffc0, 0x4010, 0xe07f, {EAFLT}, "FETOX%S %e,F%D" },
  755. { 0xf200, 0xffc0, 0x4011, 0xe07f, {EAFLT}, "FTWOTOX%S %e,F%D" },
  756. { 0xf200, 0xffc0, 0x4012, 0xe07f, {EAFLT}, "FTENTOX%S %e,F%D" },
  757. { 0xf200, 0xffc0, 0x4014, 0xe07f, {EAFLT}, "FLOGN%S %e,F%D" },
  758. { 0xf200, 0xffc0, 0x4015, 0xe07f, {EAFLT}, "FLOG10%S %e,F%D" },
  759. { 0xf200, 0xffc0, 0x4016, 0xe07f, {EAFLT}, "FLOG2%S %e,F%D" },
  760. { 0xf200, 0xffc0, 0x4018, 0xe07f, {EAFLT}, "FABS%S %e,F%D" },
  761. { 0xf200, 0xffc0, 0x4019, 0xe07f, {EAFLT}, "FCOSH%S %e,F%D" },
  762. { 0xf200, 0xffc0, 0x401a, 0xe07f, {EAFLT}, "FNEG%S %e,F%D" },
  763. { 0xf200, 0xffc0, 0x401c, 0xe07f, {EAFLT}, "FACOS%S %e,F%D" },
  764. { 0xf200, 0xffc0, 0x401d, 0xe07f, {EAFLT}, "FCOS%S %e,F%D" },
  765. { 0xf200, 0xffc0, 0x401e, 0xe07f, {EAFLT}, "FGETEXP%S %e,F%D" },
  766. { 0xf200, 0xffc0, 0x401f, 0xe07f, {EAFLT}, "FGETMAN%S %e,F%D" },
  767. { 0xf200, 0xffc0, 0x4020, 0xe07f, {EAFLT}, "FDIV%S %e,F%D" },
  768. { 0xf200, 0xffc0, 0x4021, 0xe07f, {EAFLT}, "FMOD%S %e,F%D" },
  769. { 0xf200, 0xffc0, 0x4022, 0xe07f, {EAFLT}, "FADD%S %e,F%D" },
  770. { 0xf200, 0xffc0, 0x4023, 0xe07f, {EAFLT}, "FMUL%S %e,F%D" },
  771. { 0xf200, 0xffc0, 0x4024, 0xe07f, {EAFLT}, "FSGLDIV%S %e,F%D" },
  772. { 0xf200, 0xffc0, 0x4025, 0xe07f, {EAFLT}, "FREM%S %e,F%D" },
  773. { 0xf200, 0xffc0, 0x4026, 0xe07f, {EAFLT}, "FSCALE%S %e,F%D" },
  774. { 0xf200, 0xffc0, 0x4027, 0xe07f, {EAFLT}, "FSGLMUL%S %e,F%D" },
  775. { 0xf200, 0xffc0, 0x4028, 0xe07f, {EAFLT}, "FSUB%S %e,F%D" },
  776. { 0xf200, 0xffc0, 0x4038, 0xe07f, {EAFLT}, "FCMP%S %e,F%D" },
  777. { 0xf200, 0xffc0, 0x403a, 0xe07f, {EAFLT}, "FTST%S %e" },
  778. { 0xf200, 0xffc0, 0x4040, 0xe07f, {EAFLT}, "FSMOVE%S %e,F%D" },
  779. { 0xf200, 0xffc0, 0x4041, 0xe07f, {EAFLT}, "FSSQRT%S %e,F%D" },
  780. { 0xf200, 0xffc0, 0x4044, 0xe07f, {EAFLT}, "FDMOVE%S %e,F%D" },
  781. { 0xf200, 0xffc0, 0x4045, 0xe07f, {EAFLT}, "FDSQRT%S %e,F%D" },
  782. { 0xf200, 0xffc0, 0x4058, 0xe07f, {EAFLT}, "FSABS%S %e,F%D" },
  783. { 0xf200, 0xffc0, 0x405a, 0xe07f, {EAFLT}, "FSNEG%S %e,F%D" },
  784. { 0xf200, 0xffc0, 0x405c, 0xe07f, {EAFLT}, "FDABS%S %e,F%D" },
  785. { 0xf200, 0xffc0, 0x405e, 0xe07f, {EAFLT}, "FDNEG%S %e,F%D" },
  786. { 0xf200, 0xffc0, 0x4060, 0xe07f, {EAFLT}, "FSDIV%S %e,F%D" },
  787. { 0xf200, 0xffc0, 0x4062, 0xe07f, {EAFLT}, "FSADD%S %e,F%D" },
  788. { 0xf200, 0xffc0, 0x4063, 0xe07f, {EAFLT}, "FSMUL%S %e,F%D" },
  789. { 0xf200, 0xffc0, 0x4064, 0xe07f, {EAFLT}, "FDDIV%S %e,F%D" },
  790. { 0xf200, 0xffc0, 0x4066, 0xe07f, {EAFLT}, "FDADD%S %e,F%D" },
  791. { 0xf200, 0xffc0, 0x4067, 0xe07f, {EAFLT}, "FDMUL%S %e,F%D" },
  792. { 0xf200, 0xffc0, 0x4068, 0xe07f, {EAFLT}, "FSSUB%S %e,F%D" },
  793. { 0xf200, 0xffc0, 0x406c, 0xe07f, {EAFLT}, "FDSUB%S %e,F%D" },
  794. { 0xf200, 0xffc0, 0x0030, 0xe078, {0}, "FSINCOSX F%B,F%a:F%D" },
  795. { 0xf200, 0xffc0, 0x4030, 0xe078, {EAFLT}, "FSINCOS%S %e,F%a:F%D" },
  796. { 0xf200, 0xffc0, 0x6000, 0xe000, {EADA}, "FMOVE%S F%D,%e" },
  797. { 0xf300, 0xffc0, 0x0000, 0x0000, {EACAPD}, "FSAVE %e" },
  798. { 0xf340, 0xffc0, 0x0000, 0x0000, {EACAPI}, "FRESTORE %e" },
  799. { 0xf280, 0xffc0, 0x0000, 0x0000, {BR16}, "FB%p %t" },
  800. { 0xf2c0, 0xffc0, 0x0000, 0x0000, {BR32}, "FB%p %t" },
  801. { 0xf408, 0xff38, 0x0000, 0x0000, {0}, "CINVL %C,(A%y)" },
  802. { 0xf410, 0xff38, 0x0000, 0x0000, {0}, "CINVP %C,(A%y)" },
  803. { 0xf418, 0xff38, 0x0000, 0x0000, {0}, "CINVA %C" },
  804. { 0xf428, 0xff38, 0x0000, 0x0000, {0}, "CPUSHL %C,(A%y)" },
  805. { 0xf430, 0xff38, 0x0000, 0x0000, {0}, "CPUSHP %C,(A%y)" },
  806. { 0xf438, 0xff38, 0x0000, 0x0000, {0}, "CPUSHA %C" },
  807. { 0,0,0,0,{0},0 },
  808. };
  809. static Optable *optables[] =
  810. {
  811. t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, 0, tb, tc, td, te, tf,
  812. };
  813. static Map *mymap;
  814. static int
  815. dumpinst(Inst *ip, char *buf, int n)
  816. {
  817. int i;
  818. if (n <= 0)
  819. return 0;
  820. *buf++ = '#';
  821. for (i = 0; i < ip->n && i*4+1 < n-4; i++, buf += 4)
  822. _hexify(buf, ip->raw[i], 3);
  823. *buf = 0;
  824. return i*4+1;
  825. }
  826. static int
  827. getword(Inst *ip, uvlong offset)
  828. {
  829. if (ip->n < nelem(ip->raw)) {
  830. if (get2(mymap, offset, &ip->raw[ip->n++]) > 0)
  831. return 1;
  832. werrstr("can't read instruction: %r");
  833. } else
  834. werrstr("instruction too big: %r");
  835. return -1;
  836. }
  837. static int
  838. getshorts(Inst *ip, void *where, int n)
  839. {
  840. if (ip->n+n < nelem(ip->raw)) {
  841. if (get1(mymap, ip->addr+ip->n*2, (uchar*)&ip->raw[ip->n], n*2) < 0) {
  842. werrstr("can't read instruction: %r");
  843. return 0;
  844. }
  845. memmove(where, &ip->raw[ip->n], n*2);
  846. ip->n += n;
  847. return 1;
  848. }
  849. werrstr("instruction too big: %r");
  850. return 0;
  851. }
  852. static int
  853. i8(Inst *ip, long *l)
  854. {
  855. if (getword(ip, ip->addr+ip->n*2) < 0)
  856. return -1;
  857. *l = ip->raw[ip->n-1]&0xff;
  858. if (*l&0x80)
  859. *l |= ~0xff;
  860. return 1;
  861. }
  862. static int
  863. i16(Inst *ip, long *l)
  864. {
  865. if (getword(ip, ip->addr+ip->n*2) < 0)
  866. return -1;
  867. *l = ip->raw[ip->n-1];
  868. if (*l&0x8000)
  869. *l |= ~0xffff;
  870. return 1;
  871. }
  872. static int
  873. i32(Inst *ip, long *l)
  874. {
  875. if (getword(ip, ip->addr+ip->n*2) < 0)
  876. return -1;
  877. if (getword(ip, ip->addr+ip->n*2) < 0)
  878. return -1;
  879. *l = (ip->raw[ip->n-2]<<16)|ip->raw[ip->n-1];
  880. return 1;
  881. }
  882. static int
  883. getimm(Inst *ip, Operand *ap, int mode)
  884. {
  885. ap->eatype = IMM;
  886. switch(mode)
  887. {
  888. case EAM_B: /* byte */
  889. case EAALL_B:
  890. return i8(ip, &ap->immediate);
  891. case EADI_W: /* word */
  892. case EAALL_W:
  893. return i16(ip, &ap->immediate);
  894. case EADI_L: /* long */
  895. case EAALL_L:
  896. return i32(ip, &ap->immediate);
  897. case EAFLT: /* floating point - size in bits 10-12 or word 1 */
  898. switch((ip->raw[1]>>10)&0x07)
  899. {
  900. case 0: /* long integer */
  901. return i32(ip, &ap->immediate);
  902. case 1: /* single precision real */
  903. ap->eatype = IREAL;
  904. return getshorts(ip, ap->floater, 2);
  905. case 2: /* extended precision real - not supported */
  906. ap->eatype = IEXT;
  907. return getshorts(ip, ap->floater, 6);
  908. case 3: /* packed decimal real - not supported */
  909. ap->eatype = IPACK;
  910. return getshorts(ip, ap->floater, 12);
  911. case 4: /* integer word */
  912. return i16(ip, &ap->immediate);
  913. case 5: /* double precision real */
  914. ap->eatype = IDBL;
  915. return getshorts(ip, ap->floater, 4);
  916. case 6: /* integer byte */
  917. return i8(ip, &ap->immediate);
  918. default:
  919. ip->errmsg = "bad immediate float data";
  920. return -1;
  921. }
  922. break;
  923. case IV: /* size encoded in bits 6&7 of opcode word */
  924. default:
  925. switch((ip->raw[0]>>6)&0x03)
  926. {
  927. case 0x00: /* integer byte */
  928. return i8(ip, &ap->immediate);
  929. case 0x01: /* integer word */
  930. return i16(ip, &ap->immediate);
  931. case 0x02: /* integer long */
  932. return i32(ip, &ap->immediate);
  933. default:
  934. ip->errmsg = "bad immediate size";
  935. return -1;
  936. }
  937. break;
  938. }
  939. return 1;
  940. }
  941. static int
  942. getdisp(Inst *ip, Operand *ap)
  943. {
  944. short ext;
  945. if (getword(ip, ip->addr+ip->n*2) < 0)
  946. return -1;
  947. ext = ip->raw[ip->n-1];
  948. ap->ext = ext;
  949. if ((ext&0x100) == 0) { /* indexed with 7-bit displacement */
  950. ap->disp = ext&0x7f;
  951. if (ap->disp&0x40)
  952. ap->disp |= ~0x7f;
  953. return 1;
  954. }
  955. switch(ext&0x30) /* first (inner) displacement */
  956. {
  957. case 0x10:
  958. break;
  959. case 0x20:
  960. if (i16(ip, &ap->disp) < 0)
  961. return -1;
  962. break;
  963. case 0x30:
  964. if (i32(ip, &ap->disp) < 0)
  965. return -1;
  966. break;
  967. default:
  968. ip->errmsg = "bad EA displacement";
  969. return -1;
  970. }
  971. switch (ext&0x03) /* outer displacement */
  972. {
  973. case 0x02: /* 16 bit displacement */
  974. return i16(ip, &ap->outer);
  975. case 0x03: /* 32 bit displacement */
  976. return i32(ip, &ap->outer);
  977. default:
  978. break;
  979. }
  980. return 1;
  981. }
  982. static int
  983. ea(Inst *ip, int ea, Operand *ap, int mode)
  984. {
  985. int type, size;
  986. type = 0;
  987. ap->ext = 0;
  988. switch((ea>>3)&0x07)
  989. {
  990. case 0x00:
  991. ap->eatype = Dreg;
  992. type = Dn;
  993. break;
  994. case 0x01:
  995. ap->eatype = Areg;
  996. type = An;
  997. break;
  998. case 0x02:
  999. ap->eatype = AInd;
  1000. type = Ind;
  1001. break;
  1002. case 0x03:
  1003. ap->eatype = APinc;
  1004. type = Pinc;
  1005. break;
  1006. case 0x04:
  1007. ap->eatype = APdec;
  1008. type = Pdec;
  1009. break;
  1010. case 0x05:
  1011. ap->eatype = ADisp;
  1012. type = Bdisp;
  1013. if (i16(ip, &ap->disp) < 0)
  1014. return -1;
  1015. break;
  1016. case 0x06:
  1017. ap->eatype = BXD;
  1018. type = Bdisp;
  1019. if (getdisp(ip, ap) < 0)
  1020. return -1;
  1021. break;
  1022. case 0x07:
  1023. switch(ea&0x07)
  1024. {
  1025. case 0x00:
  1026. type = Abs;
  1027. ap->eatype = ABS;
  1028. if (i16(ip, &ap->immediate) < 0)
  1029. return -1;
  1030. break;
  1031. case 0x01:
  1032. type = Abs;
  1033. ap->eatype = ABS;
  1034. if (i32(ip, &ap->immediate) < 0)
  1035. return -1;
  1036. break;
  1037. case 0x02:
  1038. type = PCrel;
  1039. ap->eatype = PDisp;
  1040. if (i16(ip, &ap->disp) < 0)
  1041. return -1;
  1042. break;
  1043. case 0x03:
  1044. type = PCrel;
  1045. ap->eatype = PXD;
  1046. if (getdisp(ip, ap) < 0)
  1047. return -1;
  1048. break;
  1049. case 0x04:
  1050. type = Imm;
  1051. if (getimm(ip, ap, mode) < 0)
  1052. return -1;
  1053. break;
  1054. default:
  1055. ip->errmsg = "bad EA mode";
  1056. return -1;
  1057. }
  1058. }
  1059. /* Allowable floating point EAs are restricted for packed,
  1060. * extended, and double precision operands
  1061. */
  1062. if (mode == EAFLT) {
  1063. size = (ip->raw[1]>>10)&0x07;
  1064. if (size == 2 || size == 3 || size == 5)
  1065. mode = EAM;
  1066. else
  1067. mode = EADI;
  1068. }
  1069. if (!(validea[mode]&type)) {
  1070. ip->errmsg = "invalid EA";
  1071. return -1;
  1072. }
  1073. return 1;
  1074. }
  1075. static int
  1076. decode(Inst *ip, Optable *op)
  1077. {
  1078. int i, t, mode;
  1079. Operand *ap;
  1080. short opcode;
  1081. opcode = ip->raw[0];
  1082. for (i = 0; i < nelem(op->opdata) && op->opdata[i]; i++) {
  1083. ap = &ip->and[i];
  1084. mode = op->opdata[i];
  1085. switch(mode)
  1086. {
  1087. case EAPI: /* normal EA modes */
  1088. case EACA:
  1089. case EACAD:
  1090. case EACAPI:
  1091. case EACAPD:
  1092. case EAMA:
  1093. case EADA:
  1094. case EAA:
  1095. case EAC:
  1096. case EACPI:
  1097. case EACD:
  1098. case EAD:
  1099. case EAM:
  1100. case EAM_B:
  1101. case EADI:
  1102. case EADI_L:
  1103. case EADI_W:
  1104. case EAALL:
  1105. case EAALL_L:
  1106. case EAALL_W:
  1107. case EAALL_B:
  1108. case EAFLT:
  1109. if (ea(ip, opcode&0x3f, ap, mode) < 0)
  1110. return -1;
  1111. break;
  1112. case EADDA: /* stupid bit flop required */
  1113. t = ((opcode>>9)&0x07)|((opcode>>3)&0x38);
  1114. if (ea(ip, t, ap, EADA)< 0)
  1115. return -1;
  1116. break;
  1117. case BREAC: /* EAC JMP or CALL operand */
  1118. if (ea(ip, opcode&0x3f, ap, EAC) < 0)
  1119. return -1;
  1120. break;
  1121. case OP8: /* weird movq instruction */
  1122. ap->eatype = IMM;
  1123. ap->immediate = opcode&0xff;
  1124. if (opcode&0x80)
  1125. ap->immediate |= ~0xff;
  1126. break;
  1127. case I8: /* must be two-word opcode */
  1128. ap->eatype = IMM;
  1129. ap->immediate = ip->raw[1]&0xff;
  1130. if (ap->immediate&0x80)
  1131. ap->immediate |= ~0xff;
  1132. break;
  1133. case I16: /* 16 bit immediate */
  1134. case BR16:
  1135. ap->eatype = IMM;
  1136. if (i16(ip, &ap->immediate) < 0)
  1137. return -1;
  1138. break;
  1139. case C16: /* CAS2 16 bit immediate */
  1140. ap->eatype = IMM;
  1141. if (i16(ip, &ap->immediate) < 0)
  1142. return -1;
  1143. if (ap->immediate & 0x0e38) {
  1144. ip->errmsg = "bad CAS2W operand";
  1145. return 0;
  1146. }
  1147. break;
  1148. case I32: /* 32 bit immediate */
  1149. case BR32:
  1150. ap->eatype = IMM;
  1151. if (i32(ip, &ap->immediate) < 0)
  1152. return -1;
  1153. break;
  1154. case IV: /* immediate data depends on size field */
  1155. if (getimm(ip, ap, IV) < 0)
  1156. return -1;
  1157. break;
  1158. case BR8: /* branch displacement format */
  1159. ap->eatype = IMM;
  1160. ap->immediate = opcode&0xff;
  1161. if (ap->immediate == 0) {
  1162. if (i16(ip, &ap->immediate) < 0)
  1163. return -1;
  1164. } else if (ap->immediate == 0xff) {
  1165. if (i32(ip, &ap->immediate) < 0)
  1166. return -1;
  1167. } else if (ap->immediate & 0x80)
  1168. ap->immediate |= ~0xff;
  1169. break;
  1170. case STACK: /* Dummy operand type for Return instructions */
  1171. default:
  1172. break;
  1173. }
  1174. }
  1175. return 1;
  1176. }
  1177. static Optable *
  1178. instruction(Inst *ip)
  1179. {
  1180. ushort opcode, op2;
  1181. Optable *op;
  1182. int class;
  1183. ip->n = 0;
  1184. if (getword(ip, ip->addr) < 0)
  1185. return 0;
  1186. opcode = ip->raw[0];
  1187. if (get2(mymap, ip->addr+2, &op2) < 0)
  1188. op2 = 0;
  1189. class = (opcode>>12)&0x0f;
  1190. for (op = optables[class]; op && op->format; op++) {
  1191. if (op->opcode != (opcode&op->mask0))
  1192. continue;
  1193. if (op->op2 != (op2&op->mask1))
  1194. continue;
  1195. if (op->mask1)
  1196. ip->raw[ip->n++] = op2;
  1197. return op;
  1198. }
  1199. ip->errmsg = "Invalid opcode";
  1200. return 0;
  1201. }
  1202. static void
  1203. bprint(Inst *i, char *fmt, ...)
  1204. {
  1205. va_list arg;
  1206. va_start(arg, fmt);
  1207. i->curr = vseprint(i->curr, i->end, fmt, arg);
  1208. va_end(arg);
  1209. }
  1210. static char *regname[] =
  1211. {
  1212. "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", "A0",
  1213. "A1", "A2", "A3", "A4", "A5", "A6", "A7", "PC", "SB"
  1214. };
  1215. static void
  1216. plocal(Inst *ip, Operand *ap)
  1217. {
  1218. int ret, offset;
  1219. uvlong moved;
  1220. Symbol s;
  1221. offset = ap->disp;
  1222. if (!findsym(ip->addr, CTEXT, &s))
  1223. goto none;
  1224. moved = pc2sp(ip->addr);
  1225. if (moved == -1)
  1226. goto none;
  1227. if (offset > moved) { /* above frame - must be argument */
  1228. offset -= moved;
  1229. ret = getauto(&s, offset-mach->szaddr, CPARAM, &s);
  1230. } else /* below frame - must be automatic */
  1231. ret = getauto(&s, moved-offset, CPARAM, &s);
  1232. if (ret)
  1233. bprint(ip, "%s+%lux", s.name, offset);
  1234. else
  1235. none: bprint(ip, "%lux", ap->disp);
  1236. }
  1237. /*
  1238. * this guy does all the work of printing the base and index component
  1239. * of an EA.
  1240. */
  1241. static int
  1242. pidx(Inst *ip, int ext, int reg, char *bfmt, char *ifmt, char *nobase)
  1243. {
  1244. char *s;
  1245. int printed;
  1246. char buf[512];
  1247. printed = 1;
  1248. if (ext&0x80) { /* Base suppressed */
  1249. if (reg == 16)
  1250. bprint(ip, bfmt, "(ZPC)");
  1251. else if (nobase)
  1252. bprint(ip, nobase);
  1253. else
  1254. printed = 0;
  1255. } else /* format base reg */
  1256. bprint(ip, bfmt, regname[reg]);
  1257. if (ext & 0x40) /* index suppressed */
  1258. return printed;
  1259. switch ((ext>>9)&0x03)
  1260. {
  1261. case 0x01:
  1262. s = "*2";
  1263. break;
  1264. case 0x02:
  1265. s = "*4";
  1266. break;
  1267. case 0x03:
  1268. s = "*8";
  1269. break;
  1270. default:
  1271. if (ext&0x80)
  1272. s = "*1";
  1273. else
  1274. s = "";
  1275. break;
  1276. }
  1277. sprint(buf, "%s.%c%s", regname[(ext>>12)&0x0f], (ext&0x800) ? 'L' : 'W', s);
  1278. if (!printed)
  1279. bprint(ip, ifmt, buf);
  1280. else
  1281. bprint(ip, "(%s)", buf);
  1282. return 1;
  1283. }
  1284. static void
  1285. prindex(Inst *ip, int reg, Operand *ap)
  1286. {
  1287. short ext;
  1288. int left;
  1289. int disp;
  1290. left = ip->end-ip->curr;
  1291. if (left <= 0)
  1292. return;
  1293. ext = ap->ext;
  1294. disp = ap->disp;
  1295. /* look for static base register references */
  1296. if ((ext&0xa0) == 0x20 && reg == 14 && mach->sb && disp) {
  1297. reg = 17; /* "A6" -> "SB" */
  1298. disp += mach->sb;
  1299. }
  1300. if ((ext&0x100) == 0) { /* brief form */
  1301. if (reg == 15)
  1302. plocal(ip, ap);
  1303. else if (disp)
  1304. ip->curr += symoff(ip->curr, left, disp, CANY);
  1305. pidx(ip, ext&0xff00, reg, "(%s)", "(%s)", 0);
  1306. return;
  1307. }
  1308. switch(ext&0x3f) /* bd size, && i/is */
  1309. {
  1310. case 0x10:
  1311. if (!pidx(ip, ext, reg, "(%s)", "(%s)", 0))
  1312. bprint(ip, "#0");
  1313. break;
  1314. case 0x11:
  1315. if (pidx(ip, ext, reg, "((%s)", "((%s)", 0))
  1316. bprint(ip, ")");
  1317. else
  1318. bprint(ip, "#0");
  1319. break;
  1320. case 0x12:
  1321. case 0x13:
  1322. ip->curr += symoff(ip->curr, left, ap->outer, CANY);
  1323. if (pidx(ip, ext, reg, "((%s)", "((%s)", 0))
  1324. bprint(ip, ")");
  1325. break;
  1326. case 0x15:
  1327. if (!pidx(ip, ext, reg, "((%s))", "(%s)", 0))
  1328. bprint(ip, "#0");
  1329. break;
  1330. case 0x16:
  1331. case 0x17:
  1332. ip->curr += symoff(ip->curr, left, ap->outer, CANY);
  1333. pidx(ip, ext, reg, "((%s))", "(%s)", 0);
  1334. break;
  1335. case 0x20:
  1336. case 0x30:
  1337. if (reg == 15)
  1338. plocal(ip, ap);
  1339. else
  1340. ip->curr += symoff(ip->curr, left, disp, CANY);
  1341. pidx(ip, ext, reg, "(%s)", "(%s)", 0);
  1342. break;
  1343. case 0x21:
  1344. case 0x31:
  1345. *ip->curr++ = '(';
  1346. if (reg == 15)
  1347. plocal(ip, ap);
  1348. else
  1349. ip->curr += symoff(ip->curr, left-1, disp, CANY);
  1350. pidx(ip, ext, reg, "(%s)", "(%s)", 0);
  1351. bprint(ip, ")");
  1352. break;
  1353. case 0x22:
  1354. case 0x23:
  1355. case 0x32:
  1356. case 0x33:
  1357. ip->curr += symoff(ip->curr, left, ap->outer, CANY);
  1358. bprint(ip, "(");
  1359. if (reg == 15)
  1360. plocal(ip, ap);
  1361. else
  1362. ip->curr += symoff(ip->curr, ip->end-ip->curr, disp, CANY);
  1363. pidx(ip, ext, reg, "(%s)", "(%s)", 0);
  1364. bprint(ip, ")");
  1365. break;
  1366. case 0x25:
  1367. case 0x35:
  1368. *ip->curr++ = '(';
  1369. if (reg == 15)
  1370. plocal(ip, ap);
  1371. else
  1372. ip->curr += symoff(ip->curr, left-1, disp, CANY);
  1373. if (!pidx(ip, ext, reg, "(%s))", "(%s)", "())"))
  1374. bprint(ip, ")");
  1375. break;
  1376. case 0x26:
  1377. case 0x27:
  1378. case 0x36:
  1379. case 0x37:
  1380. ip->curr += symoff(ip->curr, left, ap->outer, CANY);
  1381. bprint(ip, "(");
  1382. if (reg == 15)
  1383. plocal(ip, ap);
  1384. else
  1385. ip->curr += symoff(ip->curr, ip->end-ip->curr, disp, CANY);
  1386. pidx(ip, ext, reg, "(%s))", "(%s)", "())");
  1387. break;
  1388. default:
  1389. bprint(ip, "??%x??", ext);
  1390. ip->errmsg = "bad EA";
  1391. break;
  1392. }
  1393. }
  1394. static void
  1395. pea(int reg, Inst *ip, Operand *ap)
  1396. {
  1397. int i, left;
  1398. left = ip->end-ip->curr;
  1399. if (left < 0)
  1400. return;
  1401. switch(ap->eatype)
  1402. {
  1403. case Dreg:
  1404. bprint(ip, "R%d", reg);
  1405. break;
  1406. case Areg:
  1407. bprint(ip, "A%d", reg);
  1408. break;
  1409. case AInd:
  1410. bprint(ip, "(A%d)", reg);
  1411. break;
  1412. case APinc:
  1413. bprint(ip, "(A%d)+", reg);
  1414. break;
  1415. case APdec:
  1416. bprint(ip, "-(A%d)", reg);
  1417. break;
  1418. case PDisp:
  1419. ip->curr += symoff(ip->curr, left, ip->addr+2+ap->disp, CANY);
  1420. break;
  1421. case PXD:
  1422. prindex(ip, 16, ap);
  1423. break;
  1424. case ADisp: /* references off the static base */
  1425. if (reg == 6 && mach->sb && ap->disp) {
  1426. ip->curr += symoff(ip->curr, left, ap->disp+mach->sb, CANY);
  1427. bprint(ip, "(SB)", reg);
  1428. break;
  1429. }
  1430. /* reference autos and parameters off the stack */
  1431. if (reg == 7)
  1432. plocal(ip, ap);
  1433. else
  1434. ip->curr += symoff(ip->curr, left, ap->disp, CANY);
  1435. bprint(ip, "(A%d)", reg);
  1436. break;
  1437. case BXD:
  1438. prindex(ip, reg+8, ap);
  1439. break;
  1440. case ABS:
  1441. ip->curr += symoff(ip->curr, left, ap->immediate, CANY);
  1442. bprint(ip, "($0)");
  1443. break;
  1444. case IMM:
  1445. *ip->curr++ = '$';
  1446. ip->curr += symoff(ip->curr, left-1, ap->immediate, CANY);
  1447. break;
  1448. case IREAL:
  1449. *ip->curr++ = '$';
  1450. ip->curr += beieeesftos(ip->curr, left-1, (void*) ap->floater);
  1451. break;
  1452. case IDBL:
  1453. *ip->curr++ = '$';
  1454. ip->curr += beieeedftos(ip->curr, left-1, (void*) ap->floater);
  1455. break;
  1456. case IPACK:
  1457. bprint(ip, "$#");
  1458. for (i = 0; i < 24 && ip->curr < ip->end-1; i++) {
  1459. _hexify(ip->curr, ap->floater[i], 1);
  1460. ip->curr += 2;
  1461. }
  1462. break;
  1463. case IEXT:
  1464. bprint(ip, "$#");
  1465. ip->curr += beieee80ftos(ip->curr, left-2, (void*)ap->floater);
  1466. break;
  1467. default:
  1468. bprint(ip, "??%x??", ap->eatype);
  1469. ip->errmsg = "bad EA type";
  1470. break;
  1471. }
  1472. }
  1473. static char *cctab[] = { "F", "T", "HI", "LS", "CC", "CS", "NE", "EQ",
  1474. "VC", "VS", "PL", "MI", "GE", "LT", "GT", "LE" };
  1475. static char *fcond[] =
  1476. {
  1477. "F", "EQ", "OGT", "OGE", "OLT", "OLE", "OGL", "OR",
  1478. "UN", "UEQ", "UGT", "UGE", "ULT", "ULE", "NE", "T",
  1479. "SF", "SEQ", "GT", "GE", "LT", "LE", "GL", "GLE",
  1480. "NGLE", "NGL", "NLE", "NLT", "NGE", "NGT", "SNE", "ST"
  1481. };
  1482. static char *cachetab[] = { "NC", "DC", "IC", "BC" };
  1483. static char *mmutab[] = { "TC", "??", "SRP", "CRP" };
  1484. static char *crtab0[] =
  1485. {
  1486. "SFC", "DFC", "CACR", "TC", "ITT0", "ITT1", "DTT0", "DTT1",
  1487. };
  1488. static char *crtab1[] =
  1489. {
  1490. "USP", "VBR", "CAAR", "MSP", "ISP", "MMUSR", "URP", "SRP",
  1491. };
  1492. static char typetab[] = { 'L', 'S', 'X', 'P', 'W', 'D', 'B', '?', };
  1493. static char sztab[] = {'?', 'B', 'W', 'L', '?' };
  1494. static void
  1495. formatins(char *fmt, Inst *ip)
  1496. {
  1497. short op, w1;
  1498. int r1, r2;
  1499. int currand;
  1500. op = ip->raw[0];
  1501. w1 = ip->raw[1];
  1502. currand = 0;
  1503. for (; *fmt && ip->curr < ip->end; fmt++) {
  1504. if (*fmt != '%')
  1505. *ip->curr++ = *fmt;
  1506. else switch(*++fmt)
  1507. {
  1508. case '%':
  1509. *ip->curr++ = '%';
  1510. break;
  1511. case 'a': /* register number; word 1:[0-2] */
  1512. *ip->curr++ = (w1&0x07)+'0';
  1513. break;
  1514. case 'c': /* condition code; opcode: [8-11] */
  1515. bprint(ip, cctab[(op>>8)&0x0f]);
  1516. break;
  1517. case 'd': /* shift direction; opcode: [8] */
  1518. if (op&0x100)
  1519. *ip->curr++ = 'L';
  1520. else
  1521. *ip->curr++ = 'R';
  1522. break;
  1523. case 'e': /* source effective address */
  1524. pea(op&0x07, ip, &ip->and[currand++]);
  1525. break;
  1526. case 'f': /* trap vector; op code: [0-3] */
  1527. bprint(ip, "%x", op&0x0f);
  1528. break;
  1529. case 'h': /* register number; word 1: [5-7] */
  1530. *ip->curr++ = (w1>>5)&0x07+'0';
  1531. break;
  1532. case 'i': /* immediate operand */
  1533. ip->curr += symoff(ip->curr, ip->end-ip->curr,
  1534. ip->and[currand++].immediate, CANY);
  1535. break;
  1536. case 'j': /* data registers; word 1: [0-2] & [12-14] */
  1537. r1 = w1&0x07;
  1538. r2 = (w1>>12)&0x07;
  1539. if (r1 == r2)
  1540. bprint(ip, "R%d", r1);
  1541. else
  1542. bprint(ip, "R%d:R%d", r2, r1);
  1543. break;
  1544. case 'k': /* k factor; word 1 [0-6] */
  1545. bprint(ip, "%x", w1&0x7f);
  1546. break;
  1547. case 'm': /* register mask; word 1 [0-7] */
  1548. bprint(ip, "%x", w1&0xff);
  1549. break;
  1550. case 'o': /* bit field offset; word1: [6-10] */
  1551. bprint(ip, "%d", (w1>>6)&0x3f);
  1552. break;
  1553. case 'p': /* conditional predicate; opcode: [0-5]
  1554. only bits 0-4 are defined */
  1555. bprint(ip, fcond[op&0x1f]);
  1556. break;
  1557. case 'q': /* 3-bit immediate value; opcode[9-11] */
  1558. r1 = (op>>9)&0x07;
  1559. if (r1 == 0)
  1560. *ip->curr++ = '8';
  1561. else
  1562. *ip->curr++ = r1+'0';
  1563. break;
  1564. case 'r': /* register type & number; word 1: [12-15] */
  1565. bprint(ip, regname[(w1>>12)&0x0f]);
  1566. break;
  1567. case 's': /* size; opcode [6-7] */
  1568. *ip->curr = sztab[((op>>6)&0x03)+1];
  1569. if (*ip->curr++ == '?')
  1570. ip->errmsg = "bad size code";
  1571. break;
  1572. case 't': /* text offset */
  1573. ip->curr += symoff(ip->curr, ip->end-ip->curr,
  1574. ip->and[currand++].immediate+ip->addr+2, CTEXT);
  1575. break;
  1576. case 'u': /* register number; word 1: [6-8] */
  1577. *ip->curr++ = ((w1>>6)&0x07)+'0';
  1578. break;
  1579. case 'w': /* bit field width; word 1: [0-4] */
  1580. bprint(ip, "%d", w1&0x0f);
  1581. break;
  1582. case 'x': /* register number; opcode: [9-11] */
  1583. *ip->curr++ = ((op>>9)&0x07)+'0';
  1584. break;
  1585. case 'y': /* register number; opcode: [0-2] */
  1586. *ip->curr++ = (op&0x07)+'0';
  1587. break;
  1588. case 'z': /* shift count; opcode: [9-11] */
  1589. *ip->curr++ = ((op>>9)&0x07)+'0';
  1590. break;
  1591. case 'A': /* register number; word 2: [0-2] */
  1592. *ip->curr++ = (ip->raw[2]&0x07)+'0';
  1593. break;
  1594. case 'B': /* float source reg; word 1: [10-12] */
  1595. *ip->curr++ = ((w1>>10)&0x07)+'0';
  1596. break;
  1597. case 'C': /* cache identifier; opcode: [6-7] */
  1598. bprint(ip, cachetab[(op>>6)&0x03]);
  1599. break;
  1600. case 'D': /* float dest reg; word 1: [7-9] */
  1601. *ip->curr++ = ((w1>>7)&0x07)+'0';
  1602. break;
  1603. case 'E': /* destination EA; opcode: [6-11] */
  1604. pea((op>>9)&0x07, ip, &ip->and[currand++]);
  1605. break;
  1606. case 'F': /* float dest register(s); word 1: [7-9] & [10-12] */
  1607. r1 = (w1>>7)&0x07;
  1608. r2 = (w1>>10)&0x07;
  1609. if (r1 == r2)
  1610. bprint(ip, "F%d", r1);
  1611. else
  1612. bprint(ip, "F%d,F%d", r2, r1);
  1613. break;
  1614. case 'H': /* MMU register; word 1 [10-13] */
  1615. bprint(ip, mmutab[(w1>>10)&0x03]);
  1616. if (ip->curr[-1] == '?')
  1617. ip->errmsg = "bad mmu register";
  1618. break;
  1619. case 'I': /* MMU function code mask; word 1: [5-8] */
  1620. bprint(ip, "%x", (w1>>4)&0x0f);
  1621. break;
  1622. case 'K': /* dynamic k-factor register; word 1: [5-8] */
  1623. bprint(ip, "%d", (w1>>4)&0x0f);
  1624. break;
  1625. case 'L': /* MMU function code; word 1: [0-6] */
  1626. if (w1&0x10)
  1627. bprint(ip, "%x", w1&0x0f);
  1628. else if (w1&0x08)
  1629. bprint(ip, "R%d",w1&0x07);
  1630. else if (w1&0x01)
  1631. bprint(ip, "DFC");
  1632. else
  1633. bprint(ip, "SFC");
  1634. break;
  1635. case 'N': /* control register; word 1: [0-11] */
  1636. r1 = w1&0xfff;
  1637. if (r1&0x800)
  1638. bprint(ip, crtab1[r1&0x07]);
  1639. else
  1640. bprint(ip, crtab0[r1&0x07]);
  1641. break;
  1642. case 'P': /* conditional predicate; word 1: [0-5] */
  1643. bprint(ip, fcond[w1&0x1f]);
  1644. break;
  1645. case 'R': /* register type & number; word 2 [12-15] */
  1646. bprint(ip, regname[(ip->raw[2]>>12)&0x0f]);
  1647. break;
  1648. case 'S': /* float source type code; word 1: [10-12] */
  1649. *ip->curr = typetab[(w1>>10)&0x07];
  1650. if (*ip->curr++ == '?')
  1651. ip->errmsg = "bad float type";
  1652. break;
  1653. case 'U': /* register number; word 2: [6-8] */
  1654. *ip->curr++ = ((ip->raw[2]>>6)&0x07)+'0';
  1655. break;
  1656. case 'Z': /* ATC level number; word 1: [10-12] */
  1657. bprint(ip, "%x", (w1>>10)&0x07);
  1658. break;
  1659. case '1': /* effective address in second operand*/
  1660. pea(op&0x07, ip, &ip->and[1]);
  1661. break;
  1662. default:
  1663. bprint(ip, "%%%c", *fmt);
  1664. break;
  1665. }
  1666. }
  1667. *ip->curr = 0; /* there's always room for 1 byte */
  1668. }
  1669. static int
  1670. dispsize(Inst *ip)
  1671. {
  1672. ushort ext;
  1673. static int dsize[] = {0, 0, 1, 2}; /* in words */
  1674. if (get2(mymap, ip->addr+ip->n*2, &ext) < 0)
  1675. return -1;
  1676. if ((ext&0x100) == 0)
  1677. return 1;
  1678. return dsize[(ext>>4)&0x03]+dsize[ext&0x03]+1;
  1679. }
  1680. static int
  1681. immsize(Inst *ip, int mode)
  1682. {
  1683. static int fsize[] = { 2, 2, 6, 12, 1, 4, 1, -1 };
  1684. static int isize[] = { 1, 1, 2, -1 };
  1685. switch(mode)
  1686. {
  1687. case EAM_B: /* byte */
  1688. case EAALL_B:
  1689. case EADI_W: /* word */
  1690. case EAALL_W:
  1691. return 1;
  1692. case EADI_L: /* long */
  1693. case EAALL_L:
  1694. return 2;
  1695. case EAFLT: /* floating point - size in bits 10-12 or word 1 */
  1696. return fsize[(ip->raw[1]>>10)&0x07];
  1697. case IV: /* size encoded in bits 6&7 of opcode word */
  1698. default:
  1699. return isize[(ip->raw[0]>>6)&0x03];
  1700. }
  1701. return -1;
  1702. }
  1703. static int
  1704. easize(Inst *ip, int ea, int mode)
  1705. {
  1706. switch((ea>>3)&0x07)
  1707. {
  1708. case 0x00:
  1709. case 0x01:
  1710. case 0x02:
  1711. case 0x03:
  1712. case 0x04:
  1713. return 0;
  1714. case 0x05:
  1715. return 1;
  1716. case 0x06:
  1717. return dispsize(ip);
  1718. case 0x07:
  1719. switch(ea&0x07)
  1720. {
  1721. case 0x00:
  1722. case 0x02:
  1723. return 1;
  1724. case 0x01:
  1725. return 2;
  1726. case 0x03:
  1727. return dispsize(ip);
  1728. case 0x04:
  1729. return immsize(ip, mode);
  1730. default:
  1731. return -1;
  1732. }
  1733. }
  1734. return -1;
  1735. }
  1736. static int
  1737. instrsize(Inst *ip, Optable *op)
  1738. {
  1739. int i, t, mode;
  1740. short opcode;
  1741. opcode = ip->raw[0];
  1742. for (i = 0; i < nelem(op->opdata) && op->opdata[i]; i++) {
  1743. mode = op->opdata[i];
  1744. switch(mode)
  1745. {
  1746. case EAPI: /* normal EA modes */
  1747. case EACA:
  1748. case EACAD:
  1749. case EACAPI:
  1750. case EACAPD:
  1751. case EAMA:
  1752. case EADA:
  1753. case EAA:
  1754. case EAC:
  1755. case EACPI:
  1756. case EACD:
  1757. case EAD:
  1758. case EAM:
  1759. case EAM_B:
  1760. case EADI:
  1761. case EADI_L:
  1762. case EADI_W:
  1763. case EAALL:
  1764. case EAALL_L:
  1765. case EAALL_W:
  1766. case EAALL_B:
  1767. case EAFLT:
  1768. t = easize(ip, opcode&0x3f, mode);
  1769. if (t < 0)
  1770. return -1;
  1771. ip->n += t;
  1772. break;
  1773. case EADDA: /* stupid bit flop required */
  1774. t = ((opcode>>9)&0x07)|((opcode>>3)&0x38);
  1775. t = easize(ip, t, mode);
  1776. if (t < 0)
  1777. return -1;
  1778. ip->n += t;
  1779. break;
  1780. case BREAC: /* EAC JMP or CALL operand */
  1781. /* easy displacements for follow set */
  1782. if ((opcode&0x038) == 0x28 || (opcode&0x3f) == 0x3a) {
  1783. if (i16(ip, &ip->and[i].immediate) < 0)
  1784. return -1;
  1785. } else {
  1786. t = easize(ip, opcode&0x3f, mode);
  1787. if (t < 0)
  1788. return -1;
  1789. ip->n += t;
  1790. }
  1791. break;
  1792. case I16: /* 16 bit immediate */
  1793. case C16: /* CAS2 16 bit immediate */
  1794. ip->n++;
  1795. break;
  1796. case BR16: /* 16 bit branch displacement */
  1797. if (i16(ip, &ip->and[i].immediate) < 0)
  1798. return -1;
  1799. break;
  1800. case BR32: /* 32 bit branch displacement */
  1801. if (i32(ip, &ip->and[i].immediate) < 0)
  1802. return -1;
  1803. break;
  1804. case I32: /* 32 bit immediate */
  1805. ip->n += 2;
  1806. break;
  1807. case IV: /* immediate data depends on size field */
  1808. t = (ip->raw[0]>>6)&0x03;
  1809. if (t < 2)
  1810. ip->n++;
  1811. else if (t == 2)
  1812. ip->n += 2;
  1813. else
  1814. return -1;
  1815. break;
  1816. case BR8: /* loony branch displacement format */
  1817. t = opcode&0xff;
  1818. if (t == 0) {
  1819. if (i16(ip, &ip->and[i].immediate) < 0)
  1820. return -1;
  1821. } else if (t == 0xff) {
  1822. if (i32(ip, &ip->and[i].immediate) < 0)
  1823. return -1;
  1824. } else {
  1825. ip->and[i].immediate = t;
  1826. if (t & 0x80)
  1827. ip->and[i].immediate |= ~0xff;
  1828. }
  1829. break;
  1830. case STACK: /* Dummy operand for Return instructions */
  1831. case OP8: /* weird movq instruction */
  1832. case I8: /* must be two-word opcode */
  1833. default:
  1834. break;
  1835. }
  1836. }
  1837. return 1;
  1838. }
  1839. static int
  1840. eaval(Inst *ip, Operand *ap, Rgetter rget)
  1841. {
  1842. int reg;
  1843. char buf[8];
  1844. reg = ip->raw[0]&0x07;
  1845. switch(ap->eatype)
  1846. {
  1847. case AInd:
  1848. sprint(buf, "A%d", reg);
  1849. return (*rget)(mymap, buf);
  1850. case PDisp:
  1851. return ip->addr+2+ap->disp;
  1852. case ADisp:
  1853. sprint(buf, "A%d", reg);
  1854. return ap->disp+(*rget)(mymap, buf);
  1855. case ABS:
  1856. return ap->immediate;
  1857. default:
  1858. return 0;
  1859. }
  1860. }
  1861. static int
  1862. m68020instlen(Map *map, uvlong pc)
  1863. {
  1864. Inst i;
  1865. Optable *op;
  1866. mymap = map;
  1867. i.addr = pc;
  1868. i.errmsg = 0;
  1869. op = instruction(&i);
  1870. if (op && instrsize(&i, op) > 0)
  1871. return i.n*2;
  1872. return -1;
  1873. }
  1874. static int
  1875. m68020foll(Map *map, uvlong pc, Rgetter rget, uvlong *foll)
  1876. {
  1877. int j;
  1878. Inst i;
  1879. ulong l;
  1880. Optable *op;
  1881. mymap = map;
  1882. i.addr = pc;
  1883. i.errmsg = 0;
  1884. op = instruction(&i);
  1885. if (op == 0 || instrsize(&i, op) < 0)
  1886. return -1;
  1887. for (j = 0; j < nelem(op->opdata) && op->opdata[j]; j++) {
  1888. switch(op->opdata[j])
  1889. {
  1890. case BREAC: /* CALL, JMP, JSR */
  1891. foll[0] = pc+2+eaval(&i, &i.and[j], rget);
  1892. return 1;
  1893. case BR8: /* Bcc, BSR, & BRA */
  1894. case BR16: /* FBcc, FDBcc, DBcc */
  1895. case BR32: /* FBcc */
  1896. foll[0] = pc+i.n*2;
  1897. foll[1] = pc+2+i.and[j].immediate;
  1898. return 2;
  1899. case STACK: /* RTR, RTS, RTD */
  1900. if (get4(map, (*rget)(map, mach->sp), &l) < 0)
  1901. return -1;
  1902. *foll = l;
  1903. return 1;
  1904. default:
  1905. break;
  1906. }
  1907. }
  1908. foll[0] = pc+i.n*2;
  1909. return 1;
  1910. }
  1911. static int
  1912. m68020inst(Map *map, uvlong pc, char modifier, char *buf, int n)
  1913. {
  1914. Inst i;
  1915. Optable *op;
  1916. USED(modifier);
  1917. mymap = map;
  1918. i.addr = pc;
  1919. i.curr = buf;
  1920. i.end = buf+n-1;
  1921. i.errmsg = 0;
  1922. op = instruction(&i);
  1923. if (!op)
  1924. return -1;
  1925. if (decode(&i, op) > 0)
  1926. formatins(op->format, &i);
  1927. if (i.errmsg) {
  1928. if (i.curr != buf)
  1929. bprint(&i, "\t\t;");
  1930. bprint(&i, "%s: ", i.errmsg);
  1931. dumpinst(&i, i.curr, i.end-i.curr);
  1932. }
  1933. return i.n*2;
  1934. }
  1935. static int
  1936. m68020das(Map *map, uvlong pc, char *buf, int n)
  1937. {
  1938. Inst i;
  1939. Optable *op;
  1940. mymap = map;
  1941. i.addr = pc;
  1942. i.curr = buf;
  1943. i.end = buf+n-1;
  1944. i.errmsg = 0;
  1945. op = instruction(&i);
  1946. if (!op)
  1947. return -1;
  1948. decode(&i, op);
  1949. if (i.errmsg)
  1950. bprint(&i, "%s: ", i.errmsg);
  1951. dumpinst(&i, i.curr, i.end-i.curr);
  1952. return i.n*2;
  1953. }