Home Esplora Aiuto
Accedi
iank
/
libreCMC
forkato da libreCMC/libreCMC
1
0
Forka 0
File
Ramo (Branch): v1.4
Rami (Branch) Tag
libreCMC
/
package
/
kernel
/
mac80211
/
patches
/
600-10-rt2x00-rt2800lib-add-RFCSR-initialization-for-RT3883.patch

600-10-rt2x00-rt2800lib-add-RFCSR-initialization-for-RT3883.patch 6.0 KB
Permalink Cronologia Originale

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178 
  1. From 99c659cf345640fd0f733cbcaf4583cc2c868ec0 Mon Sep 17 00:00:00 2001
    2. 

  2. From: Gabor Juhos <juhosg@openwrt.org>
    3. 

  3. Date: Mon, 29 Apr 2013 13:21:48 +0200
    4. 

  4. Subject: [PATCH] rt2x00: rt2800lib: add RFCSR initialization for RT3883
    5. 

  5. 

  6. Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
    7. 

  7. ---
    8. 

  8.  drivers/net/wireless/ralink/rt2x00/rt2800.h    |    1 +
    9. 

  9.  drivers/net/wireless/ralink/rt2x00/rt2800lib.c |  141 +++++++++++++++++++++++++++++++
    10. 

  10.  2 files changed, 142 insertions(+)
    11. 

  11. 

  12. --- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
    13. 

  13. +++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
    14. 

  14. @@ -2311,6 +2311,7 @@ struct mac_iveiv_entry {
    15. 

  15.  /*
    16. 

  16.   * RFCSR 2:
    17. 

  17.   */
    18. 

  18. +#define RFCSR2_RESCAL_BP		FIELD8(0x40)
    19. 

  19.  #define RFCSR2_RESCAL_EN		FIELD8(0x80)
    20. 

  20.  #define RFCSR2_RX2_EN_MT7620		FIELD8(0x02)
    21. 

  21.  #define RFCSR2_TX2_EN_MT7620		FIELD8(0x20)
    22. 

  22. --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
    23. 

  23. +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
    24. 

  24. @@ -7685,6 +7685,144 @@ static void rt2800_init_rfcsr_5350(struc
    25. 

  25.  	rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
    26. 

  26.  }
    27. 

  27.  
    28. 

  28. +static void rt2800_init_rfcsr_3883(struct rt2x00_dev *rt2x00dev)
    29. 

  29. +{
    30. 

  30. +	u8 rfcsr;
    31. 

  31. +
    32. 

  32. +	/* TODO: get the actual ECO value from the SoC */
    33. 

  33. +	const unsigned int eco = 5;
    34. 

  34. +
    35. 

  35. +	rt2800_rf_init_calibration(rt2x00dev, 2);
    36. 

  36. +
    37. 

  37. +	rt2800_rfcsr_write(rt2x00dev, 0, 0xe0);
    38. 

  38. +	rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
    39. 

  39. +	rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
    40. 

  40. +	rt2800_rfcsr_write(rt2x00dev, 3, 0x20);
    41. 

  41. +	rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
    42. 

  42. +	rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
    43. 

  43. +	rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
    44. 

  44. +	rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
    45. 

  45. +	rt2800_rfcsr_write(rt2x00dev, 8, 0x5b);
    46. 

  46. +	rt2800_rfcsr_write(rt2x00dev, 9, 0x08);
    47. 

  47. +	rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
    48. 

  48. +	rt2800_rfcsr_write(rt2x00dev, 11, 0x48);
    49. 

  49. +	rt2800_rfcsr_write(rt2x00dev, 12, 0x1a);
    50. 

  50. +	rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
    51. 

  51. +	rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
    52. 

  52. +	rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
    53. 

  53. +	rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
    54. 

  54. +
    55. 

  55. +	/* RFCSR 17 will be initialized later based on the
    56. 

  56. +	 * frequency offset stored in the EEPROM
    57. 

  57. +	 */
    58. 

  58. +
    59. 

  59. +	rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
    60. 

  60. +	rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
    61. 

  61. +	rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
    62. 

  62. +	rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
    63. 

  63. +	rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
    64. 

  64. +	rt2800_rfcsr_write(rt2x00dev, 23, 0xc0);
    65. 

  65. +	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
    66. 

  66. +	rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
    67. 

  67. +	rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
    68. 

  68. +	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
    69. 

  69. +	rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
    70. 

  70. +	rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
    71. 

  71. +	rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
    72. 

  72. +	rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
    73. 

  73. +	rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
    74. 

  74. +	rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
    75. 

  75. +	rt2800_rfcsr_write(rt2x00dev, 34, 0x20);
    76. 

  76. +	rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
    77. 

  77. +	rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
    78. 

  78. +	rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
    79. 

  79. +	rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
    80. 

  80. +	rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
    81. 

  81. +	rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
    82. 

  82. +	rt2800_rfcsr_write(rt2x00dev, 41, 0x00);
    83. 

  83. +	rt2800_rfcsr_write(rt2x00dev, 42, 0x00);
    84. 

  84. +	rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
    85. 

  85. +	rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
    86. 

  86. +	rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
    87. 

  87. +	rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
    88. 

  88. +	rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
    89. 

  89. +	rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
    90. 

  90. +	rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
    91. 

  91. +	rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
    92. 

  92. +	rt2800_rfcsr_write(rt2x00dev, 51, 0x51);
    93. 

  93. +	rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
    94. 

  94. +	rt2800_rfcsr_write(rt2x00dev, 53, 0x76);
    95. 

  95. +	rt2800_rfcsr_write(rt2x00dev, 54, 0x76);
    96. 

  96. +	rt2800_rfcsr_write(rt2x00dev, 55, 0x76);
    97. 

  97. +	rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
    98. 

  98. +	rt2800_rfcsr_write(rt2x00dev, 57, 0x3e);
    99. 

  99. +	rt2800_rfcsr_write(rt2x00dev, 58, 0x00);
    100. 

  100. +	rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
    101. 

  101. +	rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
    102. 

  102. +	rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
    103. 

  103. +	rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
    104. 

  104. +	rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
    105. 

  105. +
    106. 

  106. +	/* TODO: rx filter calibration? */
    107. 

  107. +
    108. 

  108. +	rt2800_bbp_write(rt2x00dev, 137, 0x0f);
    109. 

  109. +
    110. 

  110. +	rt2800_bbp_write(rt2x00dev, 163, 0x9d);
    111. 

  111. +
    112. 

  112. +	rt2800_bbp_write(rt2x00dev, 105, 0x05);
    113. 

  113. +
    114. 

  114. +	rt2800_bbp_write(rt2x00dev, 179, 0x02);
    115. 

  115. +	rt2800_bbp_write(rt2x00dev, 180, 0x00);
    116. 

  116. +	rt2800_bbp_write(rt2x00dev, 182, 0x40);
    117. 

  117. +	rt2800_bbp_write(rt2x00dev, 180, 0x01);
    118. 

  118. +	rt2800_bbp_write(rt2x00dev, 182, 0x9c);
    119. 

  119. +
    120. 

  120. +	rt2800_bbp_write(rt2x00dev, 179, 0x00);
    121. 

  121. +
    122. 

  122. +	rt2800_bbp_write(rt2x00dev, 142, 0x04);
    123. 

  123. +	rt2800_bbp_write(rt2x00dev, 143, 0x3b);
    124. 

  124. +	rt2800_bbp_write(rt2x00dev, 142, 0x06);
    125. 

  125. +	rt2800_bbp_write(rt2x00dev, 143, 0xa0);
    126. 

  126. +	rt2800_bbp_write(rt2x00dev, 142, 0x07);
    127. 

  127. +	rt2800_bbp_write(rt2x00dev, 143, 0xa1);
    128. 

  128. +	rt2800_bbp_write(rt2x00dev, 142, 0x08);
    129. 

  129. +	rt2800_bbp_write(rt2x00dev, 143, 0xa2);
    130. 

  130. +	rt2800_bbp_write(rt2x00dev, 148, 0xc8);
    131. 

  131. +
    132. 

  132. +	if (eco == 5) {
    133. 

  133. +		rt2800_rfcsr_write(rt2x00dev, 32, 0xd8);
    134. 

  134. +		rt2800_rfcsr_write(rt2x00dev, 33, 0x32);
    135. 

  135. +	}
    136. 

  136. +
    137. 

  137. +	rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
    138. 

  138. +	rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_BP, 0);
    139. 

  139. +	rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
    140. 

  140. +	rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
    141. 

  141. +	msleep(1);
    142. 

  142. +	rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
    143. 

  143. +	rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
    144. 

  144. +
    145. 

  145. +	rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
    146. 

  146. +	rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
    147. 

  147. +	rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
    148. 

  148. +
    149. 

  149. +	rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
    150. 

  150. +	rfcsr |= 0xc0;
    151. 

  151. +	rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
    152. 

  152. +
    153. 

  153. +	rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
    154. 

  154. +	rfcsr |= 0x20;
    155. 

  155. +	rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
    156. 

  156. +
    157. 

  157. +	rt2800_rfcsr_read(rt2x00dev, 46, &rfcsr);
    158. 

  158. +	rfcsr |= 0x20;
    159. 

  159. +	rt2800_rfcsr_write(rt2x00dev, 46, rfcsr);
    160. 

  160. +
    161. 

  161. +	rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
    162. 

  162. +	rfcsr &= ~0xee;
    163. 

  163. +	rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
    164. 

  164. +}
    165. 

  165. +
    166. 

  166.  static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
    167. 

  167.  {
    168. 

  168.  	rt2800_rf_init_calibration(rt2x00dev, 2);
    169. 

  169. @@ -8525,6 +8663,9 @@ static void rt2800_init_rfcsr(struct rt2
    170. 

  170.  	case RT3390:
    171. 

  171.  		rt2800_init_rfcsr_3390(rt2x00dev);
    172. 

  172.  		break;
    173. 

  173. +	case RT3883:
    174. 

  174. +		rt2800_init_rfcsr_3883(rt2x00dev);
    175. 

  175. +		break;
    176. 

  176.  	case RT3572:
    177. 

  177.  		rt2800_init_rfcsr_3572(rt2x00dev);
    178. 

  178.  		break;
    179.