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libreCMC
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ar71xx
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patches-4.14
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630-MIPS-ath79-fix-chained-irq-disable.patch

630-MIPS-ath79-fix-chained-irq-disable.patch 3.1 KB
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  1. --- a/arch/mips/ath79/irq.c
    2. 

  2. +++ b/arch/mips/ath79/irq.c
    3. 

  3. @@ -27,6 +27,9 @@
    4. 

  4.  #include "machtypes.h"
    5. 

  5.  
    6. 

  6.  
    7. 

  7. +static struct irq_chip ip2_chip;
    8. 

  8. +static struct irq_chip ip3_chip;
    9. 

  9. +
    10. 

  10.  static void ar934x_ip2_irq_dispatch(struct irq_desc *desc)
    11. 

  11.  {
    12. 

  12.  	u32 status;
    13. 

  13. @@ -56,8 +59,7 @@ static void ar934x_ip2_irq_init(void)
    14. 

  14.  
    15. 

  15.  	for (i = ATH79_IP2_IRQ_BASE;
    16. 

  16.  	     i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
    17. 

  17. -		irq_set_chip_and_handler(i, &dummy_irq_chip,
    18. 

  18. -					 handle_level_irq);
    19. 

  19. +		irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
    20. 

  20.  
    21. 

  21.  	irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
    22. 

  22.  }
    23. 

  23. @@ -85,7 +87,7 @@ static void qca953x_irq_init(void)
    24. 

  24.  
    25. 

  25.  	for (i = ATH79_IP2_IRQ_BASE;
    26. 

  26.  	     i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
    27. 

  27. -		irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
    28. 

  28. +		irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
    29. 

  29.  
    30. 

  30.  	irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
    31. 

  31.  }
    32. 

  32. @@ -149,15 +151,13 @@ static void qca955x_irq_init(void)
    33. 

  33.  
    34. 

  34.  	for (i = ATH79_IP2_IRQ_BASE;
    35. 

  35.  	     i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
    36. 

  36. -		irq_set_chip_and_handler(i, &dummy_irq_chip,
    37. 

  37. -					 handle_level_irq);
    38. 

  38. +		irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
    39. 

  39.  
    40. 

  40.  	irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
    41. 

  41.  
    42. 

  42.  	for (i = ATH79_IP3_IRQ_BASE;
    43. 

  43.  	     i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
    44. 

  44. -		irq_set_chip_and_handler(i, &dummy_irq_chip,
    45. 

  45. -					 handle_level_irq);
    46. 

  46. +		irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
    47. 

  47.  
    48. 

  48.  	irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
    49. 

  49.  }
    50. 

  50. @@ -228,13 +228,13 @@ static void qca956x_irq_init(void)
    51. 

  51.  
    52. 

  52.  	for (i = ATH79_IP2_IRQ_BASE;
    53. 

  53.  	     i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
    54. 

  54. -		irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
    55. 

  55. +		irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
    56. 

  56.  
    57. 

  57.  	irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
    58. 

  58.  
    59. 

  59.  	for (i = ATH79_IP3_IRQ_BASE;
    60. 

  60.  	     i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
    61. 

  61. -		irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
    62. 

  62. +		irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
    63. 

  63.  
    64. 

  64.  	irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
    65. 

  65.  
    66. 

  66. @@ -243,12 +243,40 @@ static void qca956x_irq_init(void)
    67. 

  67.  	late_time_init = &qca956x_enable_timer_cb;
    68. 

  68.  }
    69. 

  69.  
    70. 

  70. +static void ath79_ip2_disable(struct irq_data *data)
    71. 

  71. +{
    72. 

  72. +	disable_irq(ATH79_CPU_IRQ(2));
    73. 

  73. +}
    74. 

  74. +
    75. 

  75. +static void ath79_ip2_enable(struct irq_data *data)
    76. 

  76. +{
    77. 

  77. +	enable_irq(ATH79_CPU_IRQ(2));
    78. 

  78. +}
    79. 

  79. +
    80. 

  80. +static void ath79_ip3_disable(struct irq_data *data)
    81. 

  81. +{
    82. 

  82. +	disable_irq(ATH79_CPU_IRQ(3));
    83. 

  83. +}
    84. 

  84. +
    85. 

  85. +static void ath79_ip3_enable(struct irq_data *data)
    86. 

  86. +{
    87. 

  87. +	enable_irq(ATH79_CPU_IRQ(3));
    88. 

  88. +}
    89. 

  89. +
    90. 

  90.  void __init arch_init_irq(void)
    91. 

  91.  {
    92. 

  92.  	unsigned irq_wb_chan2 = -1;
    93. 

  93.  	unsigned irq_wb_chan3 = -1;
    94. 

  94.  	bool misc_is_ar71xx;
    95. 

  95.  
    96. 

  96. +	ip2_chip = dummy_irq_chip;
    97. 

  97. +	ip2_chip.irq_disable = ath79_ip2_disable;
    98. 

  98. +	ip2_chip.irq_enable = ath79_ip2_enable;
    99. 

  99. +
    100. 

  100. +	ip3_chip = dummy_irq_chip;
    101. 

  101. +	ip3_chip.irq_disable = ath79_ip3_disable;
    102. 

  102. +	ip3_chip.irq_enable = ath79_ip3_enable;
    103. 

  103. +
    104. 

  104.  	if (mips_machtype == ATH79_MACH_GENERIC_OF) {
    105. 

  105.  		irqchip_init();
    106. 

  106.  		return;
    107.