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996-rt2x00-mt7620-differentiate-based-on-SoC-CHIP_VER.patch

996-rt2x00-mt7620-differentiate-based-on-SoC-CHIP_VER.patch 16 KB
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  1. --- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
    2. 

  2. +++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
    3. 

  3. @@ -1044,6 +1044,11 @@
    4. 

  4.  #define MIMO_PS_CFG_RX_STBY_POL		FIELD32(0x00000010)
    5. 

  5.  #define MIMO_PS_CFG_RX_RX_STBY0		FIELD32(0x00000020)
    6. 

  6.  
    7. 

  7. +#define BB_PA_MODE_CFG0			0x1214
    8. 

  8. +#define BB_PA_MODE_CFG1			0x1218
    9. 

  9. +#define RF_PA_MODE_CFG0			0x121C
    10. 

  10. +#define RF_PA_MODE_CFG1			0x1220
    11. 

  11. +
    12. 

  12.  /*
    13. 

  13.   * EDCA_AC0_CFG:
    14. 

  14.   */
    15. 

  15. --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
    16. 

  16. +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
    17. 

  17. @@ -3778,14 +3778,16 @@ static void rt2800_config_channel_rf7620
    18. 

  18.  	rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
    19. 

  19.  	rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
    20. 

  20.  
    21. 

  21. -	/* Default: XO=20MHz , SDM mode */
    22. 

  22. -	rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
    23. 

  23. -	rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
    24. 

  24. -	rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
    25. 

  25. -
    26. 

  26. -	rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
    27. 

  27. -	rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
    28. 

  28. -	rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
    29. 

  29. +	if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
    30. 

  30. +		/* Default: XO=20MHz , SDM mode */
    31. 

  31. +		rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
    32. 

  32. +		rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
    33. 

  33. +		rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
    34. 

  34. +
    35. 

  35. +		rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
    36. 

  36. +		rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
    37. 

  37. +		rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
    38. 

  38. +	}
    39. 

  39.  
    40. 

  40.  	rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
    41. 

  41.  	rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
    42. 

  42. @@ -3819,18 +3821,23 @@ static void rt2800_config_channel_rf7620
    43. 

  43.  		rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
    44. 

  44.  	}
    45. 

  45.  
    46. 

  46. -	if (conf_is_ht40(conf)) {
    47. 

  47. -		rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
    48. 

  48. -		rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
    49. 

  49. -	} else {
    50. 

  50. -		rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
    51. 

  51. -		rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
    52. 

  52. +	if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
    53. 

  53. +		if (conf_is_ht40(conf)) {
    54. 

  54. +			rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
    55. 

  55. +			rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
    56. 

  56. +		} else {
    57. 

  57. +			rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
    58. 

  58. +			rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
    59. 

  59. +		}
    60. 

  60.  	}
    61. 

  61.  
    62. 

  62. -	rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
    63. 

  63. -	rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
    64. 

  64. -			  conf_is_ht40(conf) && (rf->channel == 11));
    65. 

  65. -	rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
    66. 

  66. +	if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
    67. 

  67. +	    rt2800_hw_get_chipeco(rt2x00dev) == 2) {
    68. 

  68. +		rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
    69. 

  69. +		rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
    70. 

  70. +				  conf_is_ht40(conf) && (rf->channel == 11));
    71. 

  71. +		rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
    72. 

  72. +	}
    73. 

  73.  
    74. 

  74.  	if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
    75. 

  75.  		if (conf_is_ht40(conf)) {
    76. 

  76. @@ -3929,25 +3936,29 @@ static void rt2800_config_alc(struct rt2
    77. 

  77.  	if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))
    78. 

  78.  		rt2x00_warn(rt2x00dev, "RF busy while configuring ALC\n");
    79. 

  79.  
    80. 

  80. -	if (chan->center_freq > 2457) {
    81. 

  81. -		bbp = rt2800_bbp_read(rt2x00dev, 30);
    82. 

  82. -		bbp = 0x40;
    83. 

  83. -		rt2800_bbp_write(rt2x00dev, 30, bbp);
    84. 

  84. -		rt2800_rfcsr_write(rt2x00dev, 39, 0);
    85. 

  85. -		if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
    86. 

  86. -			rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
    87. 

  87. -		else
    88. 

  88. -			rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
    89. 

  89. -	} else {
    90. 

  90. -		bbp = rt2800_bbp_read(rt2x00dev, 30);
    91. 

  91. -		bbp = 0x1f;
    92. 

  92. -		rt2800_bbp_write(rt2x00dev, 30, bbp);
    93. 

  93. -		rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
    94. 

  94. -		if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
    95. 

  95. -			rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
    96. 

  96. -		else
    97. 

  97. -			rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
    98. 

  98. +	if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
    99. 

  99. +	    rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
    100. 

  100. +		if (chan->center_freq > 2457) {
    101. 

  101. +			bbp = rt2800_bbp_read(rt2x00dev, 30);
    102. 

  102. +			bbp = 0x40;
    103. 

  103. +			rt2800_bbp_write(rt2x00dev, 30, bbp);
    104. 

  104. +			rt2800_rfcsr_write(rt2x00dev, 39, 0);
    105. 

  105. +			if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
    106. 

  106. +				rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
    107. 

  107. +			else
    108. 

  108. +				rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
    109. 

  109. +		} else {
    110. 

  110. +			bbp = rt2800_bbp_read(rt2x00dev, 30);
    111. 

  111. +			bbp = 0x1f;
    112. 

  112. +			rt2800_bbp_write(rt2x00dev, 30, bbp);
    113. 

  113. +			rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
    114. 

  114. +			if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
    115. 

  115. +				rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
    116. 

  116. +			else
    117. 

  117. +				rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
    118. 

  118. +		}
    119. 

  119.  	}
    120. 

  120. +
    121. 

  121.  	rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
    122. 

  122.  
    123. 

  123.  	rt2800_vco_calibration(rt2x00dev);
    124. 

  124. @@ -6011,18 +6022,33 @@ static int rt2800_init_registers(struct
    125. 

  125.  	} else if (rt2x00_rt(rt2x00dev, RT5350)) {
    126. 

  126.  		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
    127. 

  127.  	} else if (rt2x00_rt(rt2x00dev, RT6352)) {
    128. 

  128. -		rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
    129. 

  129. -		rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001);
    130. 

  130. -		rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
    131. 

  131. -		rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
    132. 

  132. -		rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
    133. 

  133. -		rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
    134. 

  134. -		rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
    135. 

  135. -		rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
    136. 

  136. -		rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
    137. 

  137. -				      0x3630363A);
    138. 

  138. -		rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
    139. 

  139. -				      0x3630363A);
    140. 

  140. +		if (rt2800_hw_get_chipver(rt2x00dev) <= 1) {
    141. 

  141. +			rt2800_register_write(rt2x00dev, TX_ALC_VGA3,
    142. 

  142. +					      0x00000000);
    143. 

  143. +			rt2800_register_write(rt2x00dev, BB_PA_MODE_CFG0,
    144. 

  144. +					      0x000055FF);
    145. 

  145. +			rt2800_register_write(rt2x00dev, BB_PA_MODE_CFG1,
    146. 

  146. +					      0x00550055);
    147. 

  147. +			rt2800_register_write(rt2x00dev, RF_PA_MODE_CFG0,
    148. 

  148. +					      0x000055FF);
    149. 

  149. +			rt2800_register_write(rt2x00dev, RF_PA_MODE_CFG1,
    150. 

  150. +					      0x00550055);
    151. 

  151. +		} else {
    152. 

  152. +			rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
    153. 

  153. +			rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001);
    154. 

  154. +			rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
    155. 

  155. +			rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
    156. 

  156. +			rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
    157. 

  157. +			rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
    158. 

  158. +			rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN,
    159. 

  159. +					      0x6C6C666C);
    160. 

  160. +			rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN,
    161. 

  161. +					      0x6C6C666C);
    162. 

  162. +			rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
    163. 

  163. +					      0x3630363A);
    164. 

  164. +			rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
    165. 

  165. +					      0x3630363A);
    166. 

  166. +		}
    167. 

  167.  		reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
    168. 

  168.  		rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
    169. 

  169.  		rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
    170. 

  170. @@ -7127,14 +7153,16 @@ static void rt2800_init_bbp_6352(struct
    171. 

  171.  	rt2800_bbp_write(rt2x00dev, 188, 0x00);
    172. 

  172.  	rt2800_bbp_write(rt2x00dev, 189, 0x00);
    173. 

  173.  
    174. 

  174. -	rt2800_bbp_write(rt2x00dev, 91, 0x06);
    175. 

  175. -	rt2800_bbp_write(rt2x00dev, 92, 0x04);
    176. 

  176. -	rt2800_bbp_write(rt2x00dev, 93, 0x54);
    177. 

  177. -	rt2800_bbp_write(rt2x00dev, 99, 0x50);
    178. 

  178. -	rt2800_bbp_write(rt2x00dev, 148, 0x84);
    179. 

  179. -	rt2800_bbp_write(rt2x00dev, 167, 0x80);
    180. 

  180. -	rt2800_bbp_write(rt2x00dev, 178, 0xFF);
    181. 

  181. -	rt2800_bbp_write(rt2x00dev, 106, 0x13);
    182. 

  182. +	if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
    183. 

  183. +		rt2800_bbp_write(rt2x00dev, 91, 0x06);
    184. 

  184. +		rt2800_bbp_write(rt2x00dev, 92, 0x04);
    185. 

  185. +		rt2800_bbp_write(rt2x00dev, 93, 0x54);
    186. 

  186. +		rt2800_bbp_write(rt2x00dev, 99, 0x50);
    187. 

  187. +		rt2800_bbp_write(rt2x00dev, 148, 0x84);
    188. 

  188. +		rt2800_bbp_write(rt2x00dev, 167, 0x80);
    189. 

  189. +		rt2800_bbp_write(rt2x00dev, 178, 0xFF);
    190. 

  190. +		rt2800_bbp_write(rt2x00dev, 106, 0x13);
    191. 

  191. +	}
    192. 

  192.  
    193. 

  193.  	/* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
    194. 

  194.  	rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
    195. 

  195. @@ -10408,31 +10436,36 @@ static void rt2800_init_rfcsr_6352(struc
    196. 

  196.  	rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
    197. 

  197.  	rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
    198. 

  198.  
    199. 

  199. -	rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
    200. 

  200. -	if (rt2800_clk_is_20mhz(rt2x00dev))
    201. 

  201. -		rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
    202. 

  202. -	else
    203. 

  203. -		rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
    204. 

  204. -	rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
    205. 

  205. -	rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
    206. 

  206. -	rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
    207. 

  207. -	rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
    208. 

  208. -	rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
    209. 

  209. -	rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
    210. 

  210. -	rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
    211. 

  211. -	rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
    212. 

  212. -	rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
    213. 

  213. -	rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
    214. 

  214. -	rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
    215. 

  215. -	rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
    216. 

  216. -	rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
    217. 

  217. -	rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
    218. 

  218. -	rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
    219. 

  219. -	rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
    220. 

  220. -
    221. 

  221. -	rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
    222. 

  222. -	rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
    223. 

  223. -	rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
    224. 

  224. +	if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
    225. 

  225. +		rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
    226. 

  226. +		if (rt2800_clk_is_20mhz(rt2x00dev))
    227. 

  227. +			rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
    228. 

  228. +		else
    229. 

  229. +			rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
    230. 

  230. +		rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
    231. 

  231. +		rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
    232. 

  232. +		rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
    233. 

  233. +		rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
    234. 

  234. +		rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
    235. 

  235. +		rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
    236. 

  236. +		rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
    237. 

  237. +		rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
    238. 

  238. +		rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
    239. 

  239. +		rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
    240. 

  240. +		rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
    241. 

  241. +		rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
    242. 

  242. +		rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
    243. 

  243. +		rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
    244. 

  244. +		rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
    245. 

  245. +		rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
    246. 

  246. +	}
    247. 

  247. +
    248. 

  248. +	if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
    249. 

  249. +	    rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
    250. 

  250. +		rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
    251. 

  251. +		rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
    252. 

  252. +		rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
    253. 

  253. +	}
    254. 

  254.  
    255. 

  255.  	/* Initialize RF channel register to default value */
    256. 

  256.  	rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
    257. 

  257. @@ -10498,63 +10531,71 @@ static void rt2800_init_rfcsr_6352(struc
    258. 

  258.  
    259. 

  259.  	rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
    260. 

  260.  
    261. 

  261. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
    262. 

  262. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
    263. 

  263. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
    264. 

  264. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
    265. 

  265. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
    266. 

  266. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
    267. 

  267. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
    268. 

  268. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
    269. 

  269. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
    270. 

  270. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
    271. 

  271. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
    272. 

  272. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
    273. 

  273. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
    274. 

  274. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
    275. 

  275. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
    276. 

  276. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
    277. 

  277. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
    278. 

  278. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
    279. 

  279. -	rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
    280. 

  280. -	rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
    281. 

  281. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
    282. 

  282. -	rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
    283. 

  283. -	rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
    284. 

  284. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
    285. 

  285. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
    286. 

  286. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
    287. 

  287. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
    288. 

  288. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
    289. 

  289. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
    290. 

  290. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
    291. 

  291. -
    292. 

  292. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
    293. 

  293. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
    294. 

  294. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
    295. 

  295. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
    296. 

  296. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
    297. 

  297. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
    298. 

  298. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
    299. 

  299. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
    300. 

  300. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
    301. 

  301. -
    302. 

  302. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
    303. 

  303. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
    304. 

  304. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
    305. 

  305. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
    306. 

  306. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
    307. 

  307. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
    308. 

  308. -
    309. 

  309. -	/* Initialize RF channel register for DRQFN */
    310. 

  310. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
    311. 

  311. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
    312. 

  312. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
    313. 

  313. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
    314. 

  314. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
    315. 

  315. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
    316. 

  316. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
    317. 

  317. -	rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
    318. 

  318. +	if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
    319. 

  319. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
    320. 

  320. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
    321. 

  321. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
    322. 

  322. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
    323. 

  323. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
    324. 

  324. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
    325. 

  325. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
    326. 

  326. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
    327. 

  327. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
    328. 

  328. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
    329. 

  329. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
    330. 

  330. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
    331. 

  331. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
    332. 

  332. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
    333. 

  333. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
    334. 

  334. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
    335. 

  335. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
    336. 

  336. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
    337. 

  337. +		rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
    338. 

  338. +		rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
    339. 

  339. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
    340. 

  340. +		rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
    341. 

  341. +		rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
    342. 

  342. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
    343. 

  343. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
    344. 

  344. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
    345. 

  345. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
    346. 

  346. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
    347. 

  347. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
    348. 

  348. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
    349. 

  349. +	}
    350. 

  350. +
    351. 

  351. +	if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
    352. 

  352. +	    rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
    353. 

  353. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
    354. 

  354. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
    355. 

  355. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
    356. 

  356. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
    357. 

  357. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
    358. 

  358. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
    359. 

  359. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
    360. 

  360. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
    361. 

  361. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
    362. 

  362. +
    363. 

  363. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
    364. 

  364. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
    365. 

  365. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
    366. 

  366. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
    367. 

  367. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
    368. 

  368. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
    369. 

  369. +	}
    370. 

  370. +
    371. 

  371. +	if (rt2800_hw_get_chippkg(rt2x00dev) == 0 &&
    372. 

  372. +	    rt2800_hw_get_chipver(rt2x00dev) == 1) {
    373. 

  373. +		/* Initialize RF channel register for DRQFN */
    374. 

  374. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
    375. 

  375. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
    376. 

  376. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
    377. 

  377. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
    378. 

  378. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
    379. 

  379. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
    380. 

  380. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
    381. 

  381. +		rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
    382. 

  382. +	}
    383. 

  383.  
    384. 

  384.  	/* Initialize RF DC calibration register to default value */
    385. 

  385.  	rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
    386. 

  386. @@ -10617,12 +10658,17 @@ static void rt2800_init_rfcsr_6352(struc
    387. 

  387.  	rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
    388. 

  388.  	rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
    389. 

  389.  
    390. 

  390. -	rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
    391. 

  391. -	rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
    392. 

  392. -	rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
    393. 

  393. +	if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
    394. 

  394. +		rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
    395. 

  395. +		rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
    396. 

  396. +		rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
    397. 

  397. +	}
    398. 

  398.  
    399. 

  399. -	rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
    400. 

  400. -	rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
    401. 

  401. +	if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
    402. 

  402. +	    rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
    403. 

  403. +		rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
    404. 

  404. +		rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
    405. 

  405. +	}
    406. 

  406.  
    407. 

  407.  	rt6352_enable_pa_pin(rt2x00dev, 0);
    408. 

  408.  	rt2800_r_calibration(rt2x00dev);
    409.