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996-rt2x00-mt7620-differentiate-based-on-SoC-CHIP_VER.patch 16 KB

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  1. --- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
  2. +++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
  3. @@ -1044,6 +1044,11 @@
  4. #define MIMO_PS_CFG_RX_STBY_POL FIELD32(0x00000010)
  5. #define MIMO_PS_CFG_RX_RX_STBY0 FIELD32(0x00000020)
  6. +#define BB_PA_MODE_CFG0 0x1214
  7. +#define BB_PA_MODE_CFG1 0x1218
  8. +#define RF_PA_MODE_CFG0 0x121C
  9. +#define RF_PA_MODE_CFG1 0x1220
  10. +
  11. /*
  12. * EDCA_AC0_CFG:
  13. */
  14. --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  15. +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  16. @@ -3778,14 +3778,16 @@ static void rt2800_config_channel_rf7620
  17. rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
  18. rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
  19. - /* Default: XO=20MHz , SDM mode */
  20. - rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
  21. - rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
  22. - rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
  23. -
  24. - rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
  25. - rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
  26. - rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
  27. + if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
  28. + /* Default: XO=20MHz , SDM mode */
  29. + rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
  30. + rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
  31. + rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
  32. +
  33. + rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
  34. + rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
  35. + rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
  36. + }
  37. rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
  38. rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
  39. @@ -3819,18 +3821,23 @@ static void rt2800_config_channel_rf7620
  40. rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
  41. }
  42. - if (conf_is_ht40(conf)) {
  43. - rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
  44. - rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
  45. - } else {
  46. - rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
  47. - rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
  48. + if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
  49. + if (conf_is_ht40(conf)) {
  50. + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
  51. + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
  52. + } else {
  53. + rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
  54. + rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
  55. + }
  56. }
  57. - rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
  58. - rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
  59. - conf_is_ht40(conf) && (rf->channel == 11));
  60. - rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
  61. + if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
  62. + rt2800_hw_get_chipeco(rt2x00dev) == 2) {
  63. + rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
  64. + rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
  65. + conf_is_ht40(conf) && (rf->channel == 11));
  66. + rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
  67. + }
  68. if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
  69. if (conf_is_ht40(conf)) {
  70. @@ -3929,25 +3936,29 @@ static void rt2800_config_alc(struct rt2
  71. if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY)))
  72. rt2x00_warn(rt2x00dev, "RF busy while configuring ALC\n");
  73. - if (chan->center_freq > 2457) {
  74. - bbp = rt2800_bbp_read(rt2x00dev, 30);
  75. - bbp = 0x40;
  76. - rt2800_bbp_write(rt2x00dev, 30, bbp);
  77. - rt2800_rfcsr_write(rt2x00dev, 39, 0);
  78. - if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
  79. - rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
  80. - else
  81. - rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
  82. - } else {
  83. - bbp = rt2800_bbp_read(rt2x00dev, 30);
  84. - bbp = 0x1f;
  85. - rt2800_bbp_write(rt2x00dev, 30, bbp);
  86. - rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
  87. - if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
  88. - rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
  89. - else
  90. - rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
  91. + if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
  92. + rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
  93. + if (chan->center_freq > 2457) {
  94. + bbp = rt2800_bbp_read(rt2x00dev, 30);
  95. + bbp = 0x40;
  96. + rt2800_bbp_write(rt2x00dev, 30, bbp);
  97. + rt2800_rfcsr_write(rt2x00dev, 39, 0);
  98. + if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
  99. + rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
  100. + else
  101. + rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
  102. + } else {
  103. + bbp = rt2800_bbp_read(rt2x00dev, 30);
  104. + bbp = 0x1f;
  105. + rt2800_bbp_write(rt2x00dev, 30, bbp);
  106. + rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
  107. + if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
  108. + rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
  109. + else
  110. + rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
  111. + }
  112. }
  113. +
  114. rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
  115. rt2800_vco_calibration(rt2x00dev);
  116. @@ -6011,18 +6022,33 @@ static int rt2800_init_registers(struct
  117. } else if (rt2x00_rt(rt2x00dev, RT5350)) {
  118. rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
  119. } else if (rt2x00_rt(rt2x00dev, RT6352)) {
  120. - rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
  121. - rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001);
  122. - rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
  123. - rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
  124. - rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
  125. - rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
  126. - rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
  127. - rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
  128. - rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
  129. - 0x3630363A);
  130. - rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
  131. - 0x3630363A);
  132. + if (rt2800_hw_get_chipver(rt2x00dev) <= 1) {
  133. + rt2800_register_write(rt2x00dev, TX_ALC_VGA3,
  134. + 0x00000000);
  135. + rt2800_register_write(rt2x00dev, BB_PA_MODE_CFG0,
  136. + 0x000055FF);
  137. + rt2800_register_write(rt2x00dev, BB_PA_MODE_CFG1,
  138. + 0x00550055);
  139. + rt2800_register_write(rt2x00dev, RF_PA_MODE_CFG0,
  140. + 0x000055FF);
  141. + rt2800_register_write(rt2x00dev, RF_PA_MODE_CFG1,
  142. + 0x00550055);
  143. + } else {
  144. + rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
  145. + rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001);
  146. + rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
  147. + rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x00000000);
  148. + rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
  149. + rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
  150. + rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN,
  151. + 0x6C6C666C);
  152. + rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN,
  153. + 0x6C6C666C);
  154. + rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
  155. + 0x3630363A);
  156. + rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
  157. + 0x3630363A);
  158. + }
  159. reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
  160. rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
  161. rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
  162. @@ -7127,14 +7153,16 @@ static void rt2800_init_bbp_6352(struct
  163. rt2800_bbp_write(rt2x00dev, 188, 0x00);
  164. rt2800_bbp_write(rt2x00dev, 189, 0x00);
  165. - rt2800_bbp_write(rt2x00dev, 91, 0x06);
  166. - rt2800_bbp_write(rt2x00dev, 92, 0x04);
  167. - rt2800_bbp_write(rt2x00dev, 93, 0x54);
  168. - rt2800_bbp_write(rt2x00dev, 99, 0x50);
  169. - rt2800_bbp_write(rt2x00dev, 148, 0x84);
  170. - rt2800_bbp_write(rt2x00dev, 167, 0x80);
  171. - rt2800_bbp_write(rt2x00dev, 178, 0xFF);
  172. - rt2800_bbp_write(rt2x00dev, 106, 0x13);
  173. + if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
  174. + rt2800_bbp_write(rt2x00dev, 91, 0x06);
  175. + rt2800_bbp_write(rt2x00dev, 92, 0x04);
  176. + rt2800_bbp_write(rt2x00dev, 93, 0x54);
  177. + rt2800_bbp_write(rt2x00dev, 99, 0x50);
  178. + rt2800_bbp_write(rt2x00dev, 148, 0x84);
  179. + rt2800_bbp_write(rt2x00dev, 167, 0x80);
  180. + rt2800_bbp_write(rt2x00dev, 178, 0xFF);
  181. + rt2800_bbp_write(rt2x00dev, 106, 0x13);
  182. + }
  183. /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
  184. rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
  185. @@ -10408,31 +10436,36 @@ static void rt2800_init_rfcsr_6352(struc
  186. rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
  187. rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
  188. - rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
  189. - if (rt2800_clk_is_20mhz(rt2x00dev))
  190. - rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
  191. - else
  192. - rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
  193. - rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
  194. - rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
  195. - rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
  196. - rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
  197. - rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
  198. - rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
  199. - rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
  200. - rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
  201. - rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
  202. - rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
  203. - rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
  204. - rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
  205. - rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
  206. - rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
  207. - rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
  208. - rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
  209. -
  210. - rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
  211. - rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
  212. - rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
  213. + if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
  214. + rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
  215. + if (rt2800_clk_is_20mhz(rt2x00dev))
  216. + rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
  217. + else
  218. + rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
  219. + rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
  220. + rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
  221. + rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
  222. + rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
  223. + rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
  224. + rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
  225. + rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
  226. + rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
  227. + rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
  228. + rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
  229. + rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
  230. + rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
  231. + rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
  232. + rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
  233. + rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
  234. + rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
  235. + }
  236. +
  237. + if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
  238. + rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
  239. + rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
  240. + rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
  241. + rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
  242. + }
  243. /* Initialize RF channel register to default value */
  244. rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
  245. @@ -10498,63 +10531,71 @@ static void rt2800_init_rfcsr_6352(struc
  246. rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
  247. - rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
  248. - rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
  249. - rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
  250. - rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
  251. - rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
  252. - rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
  253. - rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
  254. - rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
  255. - rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
  256. - rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
  257. - rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
  258. - rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
  259. - rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
  260. - rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
  261. - rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
  262. - rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
  263. - rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
  264. - rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
  265. - rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
  266. - rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
  267. - rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
  268. - rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
  269. - rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
  270. - rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
  271. - rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
  272. - rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
  273. - rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
  274. - rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
  275. - rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
  276. - rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
  277. -
  278. - rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
  279. - rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
  280. - rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
  281. - rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
  282. - rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
  283. - rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
  284. - rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
  285. - rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
  286. - rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
  287. -
  288. - rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
  289. - rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
  290. - rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
  291. - rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
  292. - rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
  293. - rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
  294. -
  295. - /* Initialize RF channel register for DRQFN */
  296. - rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
  297. - rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
  298. - rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
  299. - rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
  300. - rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
  301. - rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
  302. - rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
  303. - rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
  304. + if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
  305. + rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
  306. + rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
  307. + rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
  308. + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
  309. + rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
  310. + rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
  311. + rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
  312. + rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
  313. + rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
  314. + rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
  315. + rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
  316. + rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
  317. + rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
  318. + rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
  319. + rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
  320. + rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
  321. + rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
  322. + rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
  323. + rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
  324. + rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
  325. + rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
  326. + rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
  327. + rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
  328. + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
  329. + rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
  330. + rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
  331. + rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
  332. + rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
  333. + rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
  334. + rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
  335. + }
  336. +
  337. + if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
  338. + rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
  339. + rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
  340. + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
  341. + rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
  342. + rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
  343. + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
  344. + rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
  345. + rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
  346. + rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
  347. + rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
  348. +
  349. + rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
  350. + rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
  351. + rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
  352. + rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
  353. + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
  354. + rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
  355. + }
  356. +
  357. + if (rt2800_hw_get_chippkg(rt2x00dev) == 0 &&
  358. + rt2800_hw_get_chipver(rt2x00dev) == 1) {
  359. + /* Initialize RF channel register for DRQFN */
  360. + rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
  361. + rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
  362. + rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
  363. + rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
  364. + rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
  365. + rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
  366. + rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
  367. + rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
  368. + }
  369. /* Initialize RF DC calibration register to default value */
  370. rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
  371. @@ -10617,12 +10658,17 @@ static void rt2800_init_rfcsr_6352(struc
  372. rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
  373. rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
  374. - rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
  375. - rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
  376. - rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
  377. + if (rt2800_hw_get_chipver(rt2x00dev) > 1) {
  378. + rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
  379. + rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
  380. + rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
  381. + }
  382. - rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
  383. - rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
  384. + if (rt2800_hw_get_chipver(rt2x00dev) > 1 &&
  385. + rt2800_hw_get_chipeco(rt2x00dev) >= 2) {
  386. + rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
  387. + rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
  388. + }
  389. rt6352_enable_pa_pin(rt2x00dev, 0);
  390. rt2800_r_calibration(rt2x00dev);