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@@ -13,15 +13,6 @@
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* add tuning control via ctl file;
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* this driver is little-endian specific.
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*/
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-
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-#ifdef FS
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-#include "all.h"
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-#include "io.h"
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-#include "mem.h"
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-#include "../ip/ip.h"
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-
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-#else
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-
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#include "u.h"
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#include "../port/lib.h"
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#include "mem.h"
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@@ -30,22 +21,10 @@
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#include "io.h"
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#include "../port/error.h"
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#include "../port/netif.h"
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-#endif /* FS */
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#include "etherif.h"
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#include "ethermii.h"
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-#include "compat.h"
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-
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-/* from pci.c */
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-enum
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-{ /* command register (pcidev->pcr) */
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- IOen = (1<<0),
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- MEMen = (1<<1),
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- MASen = (1<<2),
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- MemWrInv = (1<<4),
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- PErrEn = (1<<6),
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- SErrEn = (1<<8),
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-};
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+
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enum {
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Ctrl = 0x00000000, /* Device Control */
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Status = 0x00000008, /* Device Status */
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@@ -194,8 +173,6 @@ enum { /* EEPROM content offsets */
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Ea = 0x00, /* Ethernet Address */
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Cf = 0x03, /* Compatibility Field */
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Pba = 0x08, /* Printed Board Assembly number */
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- /* in fs kernel, Icw1 is defined in io.h; changed it here */
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-#define Icw1 Igbe_icw1
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Icw1 = 0x0A, /* Initialization Control Word 1 */
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Sid = 0x0B, /* Subsystem ID */
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Svid = 0x0C, /* Subsystem Vendor ID */
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@@ -580,7 +557,6 @@ static char* statistics[Nstatistics] = {
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"TCP Segmentation Context Fail",
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};
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-#ifndef FS
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static long
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igbeifstat(Ether* edev, void* a, long n, ulong offset)
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{
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@@ -592,8 +568,6 @@ igbeifstat(Ether* edev, void* a, long n, ulong offset)
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ctlr = edev->ctlr;
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qlock(&ctlr->slock);
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p = malloc(2*READSTR);
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- if (p == nil)
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- panic("igbeifstat: no mem");
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l = 0;
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for(i = 0; i < Nstatistics; i++){
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r = csr32r(ctlr, Statistics+i*4);
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@@ -704,7 +678,6 @@ igbectl(Ether* edev, void* buf, long n)
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return n;
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}
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-#endif /* FS */
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static void
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igbepromiscuous(void* arg, int on)
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@@ -744,7 +717,9 @@ igberballoc(void)
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static void
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igberbfree(Block* bp)
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{
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- BLKRESET(bp);
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+ bp->rp = bp->lim - Rbsz;
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+ bp->wp = bp->rp;
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+
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ilock(&igberblock);
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bp->next = igberbpool;
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igberbpool = bp;
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@@ -767,14 +742,14 @@ igbelim(void* ctlr)
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}
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static void
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-igbelproc(PROCARG(void *arg))
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+igbelproc(void* arg)
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{
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Ctlr *ctlr;
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Ether *edev;
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MiiPhy *phy;
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int ctrl, r;
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- edev = GETARG(arg);
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+ edev = arg;
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ctlr = edev->ctlr;
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for(;;){
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if(ctlr->mii == nil || ctlr->mii->curphy == nil)
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@@ -811,7 +786,8 @@ print("lproc status ok\n");
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ctrl |= Fd;
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}
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break;
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- case (0x100E<<16)|0x8086: /* 82540 */
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+ case (0x100E<<16)|0x8086: /* 82540EM */
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+ case (0x101E<<16)|0x8086: /* 82540EPLP */
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break;
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}
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@@ -859,6 +835,7 @@ igbetxinit(Ctlr* ctlr)
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case (0x1004<<16)|0x8086: /* 82543GC */
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case (0x1008<<16)|0x8086: /* 82544EI */
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case (0x100E<<16)|0x8086: /* 82440EM */
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+ case (0x101E<<16)|0x8086: /* 82540EPLP */
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r = 8;
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break;
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}
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@@ -889,7 +866,8 @@ igbetxinit(Ctlr* ctlr)
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switch(ctlr->id){
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default:
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break;
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- case (0x100E<<16)|0x8086:
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+ case (0x100E<<16)|0x8086: /* 82540EM */
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+ case (0x101E<<16)|0x8086: /* 82540EPLP */
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r = csr32r(ctlr, Txdctl);
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r &= ~WthreshMASK;
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r |= Gran|(4<<WthreshSHIFT);
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@@ -936,7 +914,7 @@ igbetransmit(Ether* edev)
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*/
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tdt = ctlr->tdt;
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while(NEXT(tdt, ctlr->ntd) != tdh){
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- if((bp = etheroq(edev)) == nil)
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+ if((bp = qget(edev->oq)) == nil)
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break;
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td = &ctlr->tdba[tdt];
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td->addr[0] = PCIWADDR(bp->rp);
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@@ -1016,6 +994,7 @@ igberxinit(Ctlr* ctlr)
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switch(ctlr->id){
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case (0x100E<<16)|0x8086: /* 82540EM */
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+ case (0x101E<<16)|0x8086: /* 82540EPLP */
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csr32w(ctlr, Radv, 64);
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break;
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}
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@@ -1034,7 +1013,7 @@ igberim(void* ctlr)
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}
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static void
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-igberproc(PROCARG(void *arg))
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+igberproc(void* arg)
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{
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Rd *rd;
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Block *bp;
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@@ -1042,7 +1021,7 @@ igberproc(PROCARG(void *arg))
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int r, rdh;
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Ether *edev;
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- edev = GETARG(arg);
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+ edev = arg;
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ctlr = edev->ctlr;
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igberxinit(ctlr);
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@@ -1073,7 +1052,7 @@ igberproc(PROCARG(void *arg))
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if((rd->status & Reop) && rd->errors == 0){
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bp = ctlr->rb[rdh];
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ctlr->rb[rdh] = nil;
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- INCRPTR(bp, rd->length);
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+ bp->wp += rd->length;
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bp->next = nil;
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if(!(rd->status & Ixsm)){
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ctlr->ixsm++;
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@@ -1083,9 +1062,7 @@ igberproc(PROCARG(void *arg))
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* (and valid as errors == 0).
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*/
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ctlr->ipcs++;
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-#ifndef FS
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bp->flag |= Bipck;
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-#endif
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}
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if(rd->status & Tcpcs){
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/*
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@@ -1093,16 +1070,12 @@ igberproc(PROCARG(void *arg))
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* (and valid as errors == 0).
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*/
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ctlr->tcpcs++;
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-#ifndef FS
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bp->flag |= Btcpck|Budpck;
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-#endif
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}
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-#ifndef FS
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bp->checksum = rd->checksum;
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bp->flag |= Bpktck;
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-#endif
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}
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- ETHERIQ(edev, bp, 1);
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+ etheriq(edev, bp, 1);
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}
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else if(ctlr->rb[rdh] != nil){
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freeb(ctlr->rb[rdh]);
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@@ -1147,8 +1120,6 @@ igbeattach(Ether* edev)
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ctlr->rb = malloc(ctlr->nrd*sizeof(Block*));
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ctlr->tb = malloc(ctlr->ntd*sizeof(Block*));
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- if (ctlr->tb == nil)
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- panic("igbeattach: no mem");
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if(waserror()){
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while(ctlr->nrb > 0){
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@@ -1411,6 +1382,7 @@ igbemii(Ctlr* ctlr)
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break;
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case (0x1008<<16)|0x8086: /* 82544EI*/
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case (0x100E<<16)|0x8086: /* 82540EM */
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+ case (0x101E<<16)|0x8086: /* 82540EPLP */
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ctrl &= ~(Frcdplx|Frcspd);
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csr32w(ctlr, Ctrl, ctrl);
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ctlr->mii->mir = igbemiimir;
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@@ -1560,6 +1532,7 @@ at93c46r(Ctlr* ctlr)
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areq = 0;
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break;
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case (0x100E<<16)|0x8086: /* 82540EM */
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+ case (0x101E<<16)|0x8086: /* 82540EPLP */
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areq = 1;
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csr32w(ctlr, Eecd, eecd|Areq);
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for(i = 0; i < 1000; i++){
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@@ -1600,22 +1573,20 @@ release:
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static void
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igbedetach(Ctlr* ctlr)
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{
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- int r, s;
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+ int r;
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/*
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* Perform a device reset to get the chip back to the
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* power-on state, followed by an EEPROM reset to read
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* the defaults for some internal registers.
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*/
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- s = splhi(); /* in case reset generates an interrupt */
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csr32w(ctlr, Imc, ~0);
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csr32w(ctlr, Rctl, 0);
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csr32w(ctlr, Tctl, 0);
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- delay(100); /* was 10 */
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+ delay(10);
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csr32w(ctlr, Ctrl, Devrst);
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- delay(100); /* new */
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while(csr32r(ctlr, Ctrl) & Devrst)
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;
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@@ -1627,6 +1598,7 @@ igbedetach(Ctlr* ctlr)
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default:
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break;
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case (0x100E<<16)|0x8086: /* 82540EM */
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+ case (0x101E<<16)|0x8086: /* 82540EPLP */
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r = csr32r(ctlr, Manc);
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r &= ~Arpen;
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csr32w(ctlr, Manc, r);
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@@ -1634,14 +1606,12 @@ igbedetach(Ctlr* ctlr)
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}
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csr32w(ctlr, Imc, ~0);
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- delay(100); /* new */
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while(csr32r(ctlr, Icr))
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;
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- splx(s);
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}
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-int
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-etherigbereset(Ctlr* ctlr)
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+static int
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+igbereset(Ctlr* ctlr)
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{
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int ctrl, i, pause, r, swdpio, txcw;
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@@ -1770,6 +1740,7 @@ igbepci(void)
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case (0x1004<<16)|0x8086: /* 82543GC - copper */
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case (0x1008<<16)|0x8086: /* 82544EI - copper */
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case (0x100E<<16)|0x8086: /* 82540EM - copper */
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+ case (0x101E<<16)|0x8086: /* 82540EPLP - copper */
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break;
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}
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@@ -1778,46 +1749,27 @@ igbepci(void)
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print("igbe: can't map %8.8luX\n", p->mem[0].bar);
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continue;
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}
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-
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- /*
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- * from etherga620.c:
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- * If PCI Write-and-Invalidate is enabled set the max write DMA
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- * value to the host cache-line size (32 on Pentium or later).
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- */
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- if(p->pcr & MemWrInv){
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- cls = pcicfgr8(p, PciCLS) * 4;
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- if(cls != CACHELINESZ)
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- pcicfgw8(p, PciCLS, CACHELINESZ/4);
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- }
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-
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cls = pcicfgr8(p, PciCLS);
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switch(cls){
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default:
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- print("igbe: unexpected CLS - %d bytes\n",
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- cls*sizeof(long));
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+ print("igbe: unexpected CLS - %d\n", cls*4);
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break;
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case 0x00:
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case 0xFF:
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- /* alphapc 164lx returns 0 */
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- print("igbe: unusable PciCLS: %d, using %d longs\n",
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- cls, CACHELINESZ/sizeof(long));
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- cls = CACHELINESZ/sizeof(long);
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- pcicfgw8(p, PciCLS, cls);
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- break;
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+ print("igbe: unusable CLS\n");
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+ continue;
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case 0x08:
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case 0x10:
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break;
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}
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ctlr = malloc(sizeof(Ctlr));
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- if (ctlr == nil)
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- panic("ibgepci: no mem");
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ctlr->port = port;
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ctlr->pcidev = p;
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ctlr->id = (p->did<<16)|p->vid;
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ctlr->cls = cls*4;
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ctlr->nic = KADDR(ctlr->port);
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- if(etherigbereset(ctlr)){
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+ if(igbereset(ctlr)){
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free(ctlr);
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continue;
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}
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@@ -1867,21 +1819,18 @@ igbepnp(Ether* edev)
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edev->attach = igbeattach;
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edev->transmit = igbetransmit;
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edev->interrupt = igbeinterrupt;
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-#ifndef FS
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edev->ifstat = igbeifstat;
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edev->ctl = igbectl;
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edev->arg = edev;
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edev->promiscuous = igbepromiscuous;
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-#endif
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+
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return 0;
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}
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-#ifndef FS
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void
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etherigbelink(void)
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{
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addethercard("i82543", igbepnp);
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addethercard("igbe", igbepnp);
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}
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-#endif
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