trap.c 7.3 KB

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  1. #include "u.h"
  2. #include "lib.h"
  3. #include "mem.h"
  4. #include "dat.h"
  5. #include "fns.h"
  6. #include "io.h"
  7. #include "ureg.h"
  8. void intr0(void), intr1(void), intr2(void), intr3(void);
  9. void intr4(void), intr5(void), intr6(void), intr7(void);
  10. void intr8(void), intr9(void), intr10(void), intr11(void);
  11. void intr12(void), intr13(void), intr14(void), intr15(void);
  12. void intr16(void);
  13. void intr24(void), intr25(void), intr26(void), intr27(void);
  14. void intr28(void), intr29(void), intr30(void), intr31(void);
  15. void intr32(void), intr33(void), intr34(void), intr35(void);
  16. void intr36(void), intr37(void), intr38(void), intr39(void);
  17. void intr64(void);
  18. void intrbad(void);
  19. /*
  20. * 8259 interrupt controllers
  21. */
  22. enum
  23. {
  24. Int0ctl= 0x20, /* control port (ICW1, OCW2, OCW3) */
  25. Int0aux= 0x21, /* everything else (ICW2, ICW3, ICW4, OCW1) */
  26. Int1ctl= 0xA0, /* control port */
  27. Int1aux= 0xA1, /* everything else (ICW2, ICW3, ICW4, OCW1) */
  28. Icw1= 0x10, /* select bit in ctl register */
  29. Ocw2= 0x00,
  30. Ocw3= 0x08,
  31. EOI= 0x20, /* non-specific end of interrupt */
  32. Elcr1= 0x4D0, /* Edge/Level Triggered Register */
  33. Elcr2= 0x4D1,
  34. };
  35. int int0mask = 0xff; /* interrupts enabled for first 8259 */
  36. int int1mask = 0xff; /* interrupts enabled for second 8259 */
  37. int i8259elcr; /* mask of level-triggered interrupts */
  38. /*
  39. * trap/interrupt gates
  40. */
  41. Segdesc ilt[256];
  42. enum
  43. {
  44. Maxhandler= 32, /* max number of interrupt handlers */
  45. };
  46. typedef struct Handler Handler;
  47. struct Handler
  48. {
  49. void (*r)(Ureg*, void*);
  50. void *arg;
  51. Handler *next;
  52. };
  53. struct
  54. {
  55. Handler *ivec[256];
  56. Handler h[Maxhandler];
  57. int nextfree;
  58. } halloc;
  59. void
  60. sethvec(int v, void (*r)(void), int type, int pri)
  61. {
  62. ilt[v].d0 = ((ulong)r)&0xFFFF|(KESEL<<16);
  63. ilt[v].d1 = ((ulong)r)&0xFFFF0000|SEGP|SEGPL(pri)|type;
  64. }
  65. void
  66. setvec(int v, void (*r)(Ureg*, void*), void *arg)
  67. {
  68. Handler *h;
  69. if(halloc.nextfree >= Maxhandler)
  70. panic("out of interrupt handlers");
  71. h = &halloc.h[halloc.nextfree++];
  72. h->next = halloc.ivec[v];
  73. h->r = r;
  74. h->arg = arg;
  75. halloc.ivec[v] = h;
  76. /*
  77. * enable corresponding interrupt in 8259
  78. */
  79. if((v&~0x7) == VectorPIC){
  80. int0mask &= ~(1<<(v&7));
  81. outb(Int0aux, int0mask);
  82. } else if((v&~0x7) == VectorPIC+8){
  83. int1mask &= ~(1<<(v&7));
  84. outb(Int1aux, int1mask);
  85. }
  86. }
  87. void
  88. trapdisable(void)
  89. {
  90. outb(Int0aux, 0xFF);
  91. outb(Int1aux, 0xFF);
  92. }
  93. void
  94. trapenable(void)
  95. {
  96. outb(Int0aux, int0mask);
  97. outb(Int1aux, int1mask);
  98. }
  99. /*
  100. * set up the interrupt/trap gates
  101. */
  102. void
  103. trapinit(void)
  104. {
  105. int i, x;
  106. /*
  107. * set all interrupts to panics
  108. */
  109. for(i = 0; i < 256; i++)
  110. sethvec(i, intrbad, SEGTG, 0);
  111. /*
  112. * 80386 processor (and coprocessor) traps
  113. */
  114. sethvec(0, intr0, SEGTG, 0);
  115. sethvec(1, intr1, SEGTG, 0);
  116. sethvec(2, intr2, SEGTG, 0);
  117. sethvec(3, intr3, SEGTG, 0);
  118. sethvec(4, intr4, SEGTG, 0);
  119. sethvec(5, intr5, SEGTG, 0);
  120. sethvec(6, intr6, SEGTG, 0);
  121. sethvec(7, intr7, SEGTG, 0);
  122. sethvec(8, intr8, SEGTG, 0);
  123. sethvec(9, intr9, SEGTG, 0);
  124. sethvec(10, intr10, SEGTG, 0);
  125. sethvec(11, intr11, SEGTG, 0);
  126. sethvec(12, intr12, SEGTG, 0);
  127. sethvec(13, intr13, SEGTG, 0);
  128. sethvec(14, intr14, SEGTG, 0);
  129. sethvec(15, intr15, SEGTG, 0);
  130. sethvec(16, intr16, SEGTG, 0);
  131. /*
  132. * device interrupts
  133. */
  134. sethvec(24, intr24, SEGIG, 0);
  135. sethvec(25, intr25, SEGIG, 0);
  136. sethvec(26, intr26, SEGIG, 0);
  137. sethvec(27, intr27, SEGIG, 0);
  138. sethvec(28, intr28, SEGIG, 0);
  139. sethvec(29, intr29, SEGIG, 0);
  140. sethvec(30, intr30, SEGIG, 0);
  141. sethvec(31, intr31, SEGIG, 0);
  142. sethvec(32, intr32, SEGIG, 0);
  143. sethvec(33, intr33, SEGIG, 0);
  144. sethvec(34, intr34, SEGIG, 0);
  145. sethvec(35, intr35, SEGIG, 0);
  146. sethvec(36, intr36, SEGIG, 0);
  147. sethvec(37, intr37, SEGIG, 0);
  148. sethvec(38, intr38, SEGIG, 0);
  149. sethvec(39, intr39, SEGIG, 0);
  150. /*
  151. * tell the hardware where the table is (and how long)
  152. */
  153. putidt(ilt, sizeof(ilt)-1);
  154. /*
  155. * Set up the first 8259 interrupt processor.
  156. * Make 8259 interrupts start at CPU vector VectorPIC.
  157. * Set the 8259 as master with edge triggered
  158. * input with fully nested interrupts.
  159. */
  160. outb(Int0ctl, Icw1|0x01); /* ICW1 - edge triggered, master,
  161. ICW4 will be sent */
  162. outb(Int0aux, VectorPIC); /* ICW2 - interrupt vector offset */
  163. outb(Int0aux, 0x04); /* ICW3 - have slave on level 2 */
  164. outb(Int0aux, 0x01); /* ICW4 - 8086 mode, not buffered */
  165. /*
  166. * Set up the second 8259 interrupt processor.
  167. * Make 8259 interrupts start at CPU vector VectorPIC+8.
  168. * Set the 8259 as master with edge triggered
  169. * input with fully nested interrupts.
  170. */
  171. outb(Int1ctl, Icw1|0x01); /* ICW1 - edge triggered, master,
  172. ICW4 will be sent */
  173. outb(Int1aux, VectorPIC+8); /* ICW2 - interrupt vector offset */
  174. outb(Int1aux, 0x02); /* ICW3 - I am a slave on level 2 */
  175. outb(Int1aux, 0x01); /* ICW4 - 8086 mode, not buffered */
  176. outb(Int1aux, int1mask);
  177. /*
  178. * pass #2 8259 interrupts to #1
  179. */
  180. int0mask &= ~0x04;
  181. outb(Int0aux, int0mask);
  182. /*
  183. * Set Ocw3 to return the ISR when ctl read.
  184. */
  185. outb(Int0ctl, Ocw3|0x03);
  186. outb(Int1ctl, Ocw3|0x03);
  187. /*
  188. * Check for Edge/Level register.
  189. * This check may not work for all chipsets.
  190. * First try a non-intrusive test - the bits for
  191. * IRQs 13, 8, 2, 1 and 0 must be edge (0). If
  192. * that's OK try a R/W test.
  193. */
  194. x = (inb(Elcr2)<<8)|inb(Elcr1);
  195. if(!(x & 0x2107)){
  196. outb(Elcr1, 0);
  197. if(inb(Elcr1) == 0){
  198. outb(Elcr1, 0x20);
  199. if(inb(Elcr1) == 0x20)
  200. i8259elcr = x;
  201. outb(Elcr1, x & 0xFF);
  202. print("ELCR: %4.4uX\n", i8259elcr);
  203. }
  204. }
  205. }
  206. /*
  207. * dump registers
  208. */
  209. static void
  210. dumpregs(Ureg *ur)
  211. {
  212. print("FLAGS=%lux TRAP=%lux ECODE=%lux PC=%lux\n",
  213. ur->flags, ur->trap, ur->ecode, ur->pc);
  214. print(" AX %8.8lux BX %8.8lux CX %8.8lux DX %8.8lux\n",
  215. ur->ax, ur->bx, ur->cx, ur->dx);
  216. print(" SI %8.8lux DI %8.8lux BP %8.8lux\n",
  217. ur->si, ur->di, ur->bp);
  218. print(" CS %4.4lux DS %4.4lux ES %4.4lux FS %4.4lux GS %4.4lux\n",
  219. ur->cs & 0xFF, ur->ds & 0xFFFF, ur->es & 0xFFFF, ur->fs & 0xFFFF, ur->gs & 0xFFFF);
  220. print(" CR0 %8.8lux CR2 %8.8lux CR3 %8.8lux\n",
  221. getcr0(), getcr2(), getcr3());
  222. }
  223. /*
  224. * All traps
  225. */
  226. void
  227. trap(Ureg *ur)
  228. {
  229. int v;
  230. int c;
  231. Handler *h;
  232. ushort isr;
  233. v = ur->trap;
  234. /*
  235. * tell the 8259 that we're done with the
  236. * highest level interrupt (interrupts are still
  237. * off at this point)
  238. */
  239. c = v&~0x7;
  240. isr = 0;
  241. if(c==VectorPIC || c==VectorPIC+8){
  242. isr = inb(Int0ctl);
  243. outb(Int0ctl, EOI);
  244. if(c == VectorPIC+8){
  245. isr |= inb(Int1ctl)<<8;
  246. outb(Int1ctl, EOI);
  247. }
  248. }
  249. if(v>=256 || (h = halloc.ivec[v]) == 0){
  250. if(v >= VectorPIC && v < VectorPIC+16){
  251. v -= VectorPIC;
  252. /*
  253. * Check for a default IRQ7. This can happen when
  254. * the IRQ input goes away before the acknowledge.
  255. * In this case, a 'default IRQ7' is generated, but
  256. * the corresponding bit in the ISR isn't set.
  257. * In fact, just ignore all such interrupts.
  258. */
  259. if(isr & (1<<v))
  260. print("unknown interrupt %d pc=0x%lux\n", v, ur->pc);
  261. return;
  262. }
  263. switch(v){
  264. case 0x02: /* NMI */
  265. print("NMI: nmisc=0x%2.2ux, nmiertc=0x%2.2ux, nmiesc=0x%2.2ux\n",
  266. inb(0x61), inb(0x70), inb(0x461));
  267. return;
  268. default:
  269. dumpregs(ur);
  270. panic("exception/interrupt %d", v);
  271. return;
  272. }
  273. }
  274. /*
  275. * call the trap routines
  276. */
  277. do {
  278. (*h->r)(ur, h->arg);
  279. h = h->next;
  280. } while(h);
  281. }
  282. extern void realmode0(void); /* in l.s */
  283. extern int realmodeintr;
  284. extern Ureg realmoderegs;
  285. void
  286. realmode(int intr, Ureg *ureg)
  287. {
  288. realmoderegs = *ureg;
  289. realmodeintr = intr;
  290. trapdisable();
  291. realmode0();
  292. trapenable();
  293. *ureg = realmoderegs;
  294. }